Updated copyright info for the issues reported after running
check-legal test.
Signed-off-by: Yogesh Gaur
Reviewed-by: York Sun
---
Legally NXP and Freescale Semiconductor are same entity.
Changes for v2:
- Rebase to top as per York's comment.
drivers/net/fsl-mc/dpbp.c
Updated copyright info for the issues reported after running
check-legal test.
Signed-off-by: Yogesh Gaur
---
Legally NXP and Freescale Semiconductor are same entity.
drivers/net/fsl-mc/dpbp.c | 2 +-
drivers/net/fsl-mc/dpio/dpio.c | 2 +-
drivers/net/fsl-mc/dpmac.c | 2
PL is deployed successfully in lazyapply method.
Signed-off-by: Yogesh Gaur
v1: Incorporated York's review comments.
---
drivers/net/fsl-mc/mc.c | 4 +++-
include/fdt_support.h | 3 +++
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/
PL is deployed successfully in lazyapply method.
Signed-off-by: Yogesh Gaur
---
drivers/net/fsl-mc/mc.c | 6 +-
include/fdt_support.h | 3 +++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index f36fe06..ab2cce1 100644
--- a/dr
: Yogesh Gaur
---
board/freescale/ls1088a/ls1088a.c | 2 +-
board/freescale/ls2080a/ls2080a.c | 2 +-
board/freescale/ls2080aqds/ls2080aqds.c | 2 +-
board/freescale/ls2080ardb/ls2080ardb.c | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/board/freescale/ls1088a
For case when MC is loaded but DPL is not deployed perform MC
object [DPBP, DPIO, DPNI and DPRC] cleanup.
Signed-off-by: Yogesh Gaur
---
drivers/net/fsl-mc/mc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index 9d25cd1
Add MT35XU512ABA1G12 parameters to NOR flash parameters array.
The MT35XU512ABA1G12 only supports 1 bit mode and 8 bits. It can't support
dual and quad. Supports subsector erase with 4KB granularity, have support
of FSR(flag status register) and flash size is 64MB.
Signed-off-by: Yogesh
Add MT35XU512ABA1G12 parameters to NOR flash parameters array.
The MT35XU512ABA1G12 only supports 1 bit mode and 8 bits. It can't support
dual and quad. Supports subsector erase with 4KB granularity, have support
of FSR(flag status register) and flash size is 64MB.
Signed-off-by: Yogesh
Add MT35XU512ABA1G12 parameters to NOR flash parameters array. Since the
manufactory ID is changed to 0x2C, add it for micron and using it for
relevant settings.
The MT35XU512ABA1G12 only supports 1 bit mode and 8 bits. It can't support
dual and quad. Supports subsector erase with 4KB granularity,
Add entry for MT35XU512ABA1G12 flash in spi_flash_ids[] table.
This flash supports subsector erase with 4KB granularity, have support
of FSR(flag status register) and flash size is 64MB.
Support of this flash is required for the upcoming NXP FlexSPI controller.
Signed-off-by: Yogesh Gaur
On LS2081ARDB both QSPI and DSPI are having flash n25q512a of micron family
which supports EAR Read/Write cmds, thus enable CONFIG_SPI_FLASH_BAR config.
Else only lower 16MiB accessible for these flashes.
Signed-off-by: Yogesh Gaur
---
Depends on :
https://patchwork.ozlabs.org/patch/755920
Earlier when MC is loaded but DPL is not deployed results in FDT fix-up
code execution hang.
For this case now print message on console and returns success instead of
return -ENODEV.
This update allows to continue fdt fixup execution.
Signed-off-by: Yogesh Gaur
Signed-off-by: Priyanka Jain
When MC is loaded, but DPL is not deployed, it results in FDT fix-up
code execution hang.
To resolve this, returns success instead of return -ENODEV and print message
on console.
This update allows to continue fdt fixup execution.
Signed-off-by: Yogesh Gaur
Signed-off-by: Priyanka Jain
Earlier when MC is loaded but DPL is not deployed results in FDT fix-up
code execution hang.
For this case now print message on console and returns success instead of
return -ENODEV.
This update allows to continue fdt fixup execution.
Signed-off-by: Yogesh Gaur
Signed-off-by: Priyanka Jain
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