ed-by: Linus Walleij
Reviewed-by: Yann Gautier
Signed-off-by: Marek Vasut
Signed-off-by: Alexandre Torgue
Signed-off-by: Yann Gautier
---
arch/arm/dts/stm32h743.dtsi | 2 --
arch/arm/dts/stm32mp131.dtsi | 2 --
arch/arm/dts/stm32mp151.dtsi | 3 ---
3 files changed, 7 deletions(-)
diff --
On STM32MP135F-DK, the SD card detect GPIO is GPIOH4.
Backport of the Linux patch:
https://lore.kernel.org/linux-arm-kernel/20220921160334.3227138-1-yann.gaut...@foss.st.com/
Signed-off-by: Yann Gautier
Signed-off-by: Alexandre Torgue
---
arch/arm/dts/stm32mp135f-dk.dts | 2 +-
1 file changed
their DT.
Signed-off-by: Yann Gautier
---
There are 2 checkpatch warnings:
drivers/mmc/stm32_sdmmc2.c:40: warning: Use 'if (IS_ENABLED(CONFIG...))'
instead of '#if or #ifdef' where possible
drivers/mmc/stm32_sdmmc2.c:580: warning: Use 'if (IS_ENABLED(CONFIG...))
The UHS modes for SD, HS200 and HS400 modes for eMMC are not supported
by the stm32_sdmmc2 driver.
Make it clear by removing the corresponding caps after parsing the DT.
Signed-off-by: Yann Gautier
---
drivers/mmc/stm32_sdmmc2.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mmc
To support dual data rate with STM32 sdmmc2 driver, the dedicated bit
(DDR - BIT(18)) needs to be set in the CLKRC register. Clock bypass
(no divider) is not allowed in this case. This is required for the
eMMC DDR modes.
Signed-off-by: Yann Gautier
---
drivers/mmc/stm32_sdmmc2.c | 5 -
1
On 8/18/22 14:06, Sughosh Ganu wrote:
hi Yann,
On Thu, 18 Aug 2022 at 13:35, Yann Gautier wrote:
On 8/17/22 14:43, Sughosh Ganu wrote:
Enabling capsule update functionality on the platform requires
populating information on the images that are to be updated using the
functionality. Do so
On 8/17/22 14:43, Sughosh Ganu wrote:
Enabling capsule update functionality on the platform requires
populating information on the images that are to be updated using the
functionality. Do so for the DK2 board.
Signed-off-by: Sughosh Ganu
Reviewed-by: Patrick Delaunay
Reviewed-by: Ilias Apalod
: Patrice Chotard
Cc: Patrick Delaunay
Hi Marek,
Reviewed-by: Yann Gautier
Best regards,
Yann
pdf
Signed-off-by: Yann Gautier
---
drivers/mmc/mmc-uclass.c | 14 ++
drivers/mmc/mmc.c| 15 +++
include/mmc.h| 13 +
3 files changed, 42 insertions(+)
diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c
index 37c3843902..c7a832c
For the correct power cycle sequence with stm32_sdmmc2, the write of the
power cycle value in PWRCTL field of SDMMC_POWER register is now done in
stm32_sdmmc2_host_power_cycle() and no more in stm32_sdmmc2_pwrcycle().
Signed-off-by: Yann Gautier
---
drivers/mmc/stm32_sdmmc2.c | 13
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