Thank you, I understand.
Regards,
Xiang W
Heinrich Schuchardt 于2023年10月31日周二 20:09写道：
>
> On 10/31/23 09:53, Xiang W wrote:
> > setjmp can be called in set_resume.
>
> Unfortunately this is not possible. A longjmp buffer only stores
> register values and not the stack cont
Sorry! I missed it.
Regards,
Xiang W
Leo Liang 于2023年10月31日周二 14:47写道：
>
> Hi Xiang,
> On Tue, Oct 31, 2023 at 02:16:22PM +0800, merle w wrote:
> > drivers/rng/riscv_zkr_rng.c:10:10: fatal error: interrupt.h: No such
> > file or directory
> > 10 | #include
> >
setjmp can be called in set_resume.
Regards,
Xiang W
Heinrich Schuchardt 于2023年10月29日周日 16:56写道：
>
> If CSRs like seed are readable by S-mode, may not be determinable by
> S-mode. For safe driver probing allow to resume via a longjmp after an
> exception.
>
> Signed-off-by: H
在 2023-02-10星期五的 07:25 +，Leo Liang写道：
> Hi Xiang,
>
> On Fri, Feb 03, 2023 at 03:24:37PM +0100, David Abdurachmanov wrote:
> > On Mon, Jan 3, 2022 at 1:13 PM Leo Liang wrote:
> > >
> > > On Thu, Dec 30, 2021 at 01:55:15AM +0800, Xiang W wrote:
> > >
The bar of the structure virtio_pci_cap is the index, and each base
address occupies 4 bytes, so it needs to be multiplied by 4.
This patch fixes a bug reported by Felix Yan
https://lists.denx.de/pipermail/u-boot/2022-August/492779.html
Signed-off-by: Xiang W
Tested-by: Felix Yan
---
drivers
,"addr":"0x0","drive":"libvirt-2-format","id":"virtio-disk0","bootindex":1}'
>
> \
> -nographic
>
> --
> Regards,
> Felix Yan
Please try my patch and let me know the test results
diff --git a/drivers/virtio/virtio_pci_modern.c
b/drivers/virtio/virtio_pci_modern.c
index 880a12cc28..cfde4007f5 100644
--- a/drivers/virtio/virtio_pci_modern.c
+++ b/drivers/virtio/virtio_pci_modern.c
@@ -466,7 +466,7 @@ static void __iomem *virtio_pci_map_capability(struct
udevice *udev,
unsigned long mask =
PCI_REGION_TYPE | PCI_REGION_SYS_MEMORY | PCI_REGION_RO;
unsigned long flags = PCI_REGION_MEM;
- u8 *p = dm_pci_map_bar(udev, PCI_BASE_ADDRESS_0 + cap->bar, cap->offset,
+ u8 *p = dm_pci_map_bar(udev, PCI_BASE_ADDRESS_0 + 4 * cap->bar,
cap->offset,
cap->length, mask, flags);
return (void __iomem *)p;
Regards,
Xiang W
在 2021-12-29星期三的 17:23 +0800，Leo Liang写道：
> Hi Xiang,
> On Wed, Dec 22, 2021 at 07:32:53AM +0800, Xiang W wrote:
> > Various specifications of riscv allow the number of hart to be
> > greater than 32. The limit of 32 is determined by
> > gd->arch.available_harts. We ca
cal Interruptor
Specification.
Test on sifive unmatched.
Signed-off-by: Xiang W
---
Changes since v1:
* When NR_CPUS is very large, the value of GD_AVAILABLE_HARTS will
overflow the immediate range of ld/lw. This patch fixes this
problem
arch/riscv/Kconfig | 4 ++--
arch/ri
cal Interruptor
Specification.
Test on sifive unmatched.
Signed-off-by: Xiang W
---
arch/riscv/Kconfig | 4 ++--
arch/riscv/cpu/start.S | 19 ++-
arch/riscv/include/asm/global_data.h | 4 +++-
arch/riscv/lib/smp.c | 2 +-
4 fi
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