From: Vitor Soares
Add the new PID4 to the ConfigBlock handling:
- 0098 Aquila iMX95 Hexa 16GB WB IT
- 0099 Verdin AM62P Quad 2GB WB IT
- 0201 SMARC iMX95 Hexa 8GB IT
- 0202 SMARC iMX95 Hexa 4GB WB IT
- 0203 SMARC iMX95 Hexa 4GB ET
- 0204 SMARC iMX95 Hexa 2GB WB IT
- 0205 SMARC iMX95 Hexa
From: Vitor Soares
Add PID4 0096 Toradex SMARC iMX95 Hexa 8GB WB IT to config block handling.
Signed-off-by: Vitor Soares
---
board/toradex/common/tdx-cfg-block.c | 1 +
board/toradex/common/tdx-cfg-block.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/board/toradex/common/tdx-cfg
From: Vitor Soares
This series adds support for the new Toradex SMARC i.MX8MP
System-on-Module (SoM), along with necessary
updates to Toradex config block and device tree synchronization.
1. Syncs imx8mp.dtsi with Linux v6.15-rc1;
2. Introduces Toradex SMARC iMX95 8GB WB IT (PID 0096) in
From: Vitor Soares
Add support for the Toradex SMARC iMX8MP.
Link:
https://www.toradex.com/computer-on-modules/smarc-arm-family/nxp-imx-8m-plus
Link: https://www.toradex.com/products/carrier-board/smarc-development-board-kit
Signed-off-by: Vitor Soares
---
The support for the Linux Kernel has
From: Vitor Soares
Sync imx8mp.dtsi with Linux v6.15-rc1.
Signed-off-by: Vitor Soares
---
arch/arm/dts/imx8mp.dtsi | 413 +--
1 file changed, 355 insertions(+), 58 deletions(-)
diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi
index
From: Vitor Soares
The module pid4 currently corresponds to the index of the toradex_module
array. If a new pid4 is introduced that does not follow the sequence of
the previous entries, it will create a gap in the array.
To address this, embed pid4 within the toradex_som structure and
implement
On Mon, 2024-11-25 at 11:48 +0100, Francesco Dolcini wrote:
> +Fabio
>
> since he is the one normally picking patches from board/toradex/.
>
> On Fri, Nov 22, 2024 at 06:27:22PM +0000, Vitor Soares wrote:
> > From: Vitor Soares
> >
> > The module pid4 currentl
From: Vitor Soares
The module pid4 currently corresponds to the index of the toradex_module
array. If a new pid4 is introduced that does not follow the sequence of
the previous entries, it will create a gap in the array.
To address this, embed pid4 within the toradex_som structure and
implement
On Fri, 2024-11-22 at 11:32 +, Vitor Soares wrote:
> From: Vitor Soares
>
> The module pid4 currently corresponds to the index of the toradex_module
> array. If a new pid4 is introduced that does not follow the sequence of
> the previous entries, it will create a gap in the
From: Vitor Soares
The module pid4 currently corresponds to the index of the toradex_module
array. If a new pid4 is introduced that does not follow the sequence of
the previous entries, it will create a gap in the array.
To address this, embed pid4 within the toradex_som structure and
implement
From: Vitor Soares
With the introduction of downstream Linux 6.6, the iMX8MP VPU block
control node in DTS was renamed "blk-ctl@3833" and will not match
the ones found in `node_path_imx8mp` resulting in the node not being
disabled on the VPU-less variants.
Add an extra node_path
From: Vitor Soares
Enable USB host as well as USB gadget and DFU support for a53 and r5
configs. Also, enable UUU fastboot support to download files with
the UUU tool from a53.
Additionally, configure usb0 to peripheral mode and add extra
environment for DFU use.
Signed-off-by: Vitor Soares
From: Vitor Soares
During the boot, the EFI loader maps the memory from ram_top to ram_end
as EFI_BOOT_SERVICES_DATA. When LMB does boot_fdt_add_mem_rsv_regions()
to OPTEE, TFA, R5, and M4F DMA/memory "no-map" for the kernel it produces
the following error message:
ERROR: reserving
From: Vitor Soares
On imx8m[m|p|q].dtsi, upstream Linux uses different names for NPU/VPU
IP block nodes. It leads variants without such HW block having it
enabled by default.
This patch adds the upstream Linux node's paths to the disable list while
keep the compatibility with downstream
From: Vitor Soares
The same U-Boot binary is compatible with multiple Verdin AM62 board
variants. However, some of the SoC models can only operate at a maximum
speed of 1 GHz.
Previously, the boards with lower-speed grades were running at
overclocked speeds, leading to kernel complaints about
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