A CHAN [4] => 18 (Primary)2 (Primary) 6 (Primary)
BCDMA CHAN RING[4] => 18 (Primary)2 (Primary) 6 (Primary)
Signed-off-by: Sparsh Kumar
Signed-off-by: Sebin Francis
Signed-off-by: Vishal Mahaveer
---
This patch is based on commit 743c15b9fd (Merge patch
With the latest TIFS firmware, an additional virtual interrupt and
event is reserved for TIFS usage on am62x and am62ax devices.
Update the rm-cfg to reflect this new reservation.
Signed-off-by: Vishal Mahaveer
---
board/ti/am62ax/rm-cfg.yaml | 8
board/ti/am62x/rm-cfg.yaml | 8
Minor formatting updates to the rm board configuration file for
am62x and am62ax boards.
Signed-off-by: Vishal Mahaveer
---
board/ti/am62ax/rm-cfg.yaml | 454 +---
board/ti/am62x/rm-cfg.yaml | 445 +--
2 files changed, 326
Share the MCU GPIO interrupts between A53 core and DM R5 core. Allocating
2 instances each to A53 and DM R5.
Signed-off-by: Vishal Mahaveer
---
board/ti/am62ax/rm-cfg.yaml | 16 ++--
board/ti/am62x/rm-cfg.yaml | 16 ++--
2 files changed, 28 insertions(+), 4 deletions
: Vishal Mahaveer
---
board/ti/am62ax/rm-cfg.yaml | 46 +++--
1 file changed, 29 insertions(+), 17 deletions(-)
diff --git a/board/ti/am62ax/rm-cfg.yaml b/board/ti/am62ax/rm-cfg.yaml
index 422f6fef98..6e15366431 100644
--- a/board/ti/am62ax/rm-cfg.yaml
+++ b/board/ti
Updates as a result of TIFS core now reserving a virtual interrupt
for enabling interrupts between DM to TIFS core. Because of this
change other virtual interrupt counts decrease by one.
Signed-off-by: Vishal Mahaveer
---
board/ti/am62ax/rm-cfg.yaml | 22 +++---
board/ti/am62x
e/ti-linux-firmware/log/?h=ti-linux-firmware
SHA: e891ddc65c55bfa7111e4f45834b7c26444dff72
U-boot boot log -
https://gist.github.com/vishalmti/6b38fb80d557478131d5aaed5aeb3596
Vishal Mahaveer (4):
board: ti: am62x/am62ax: Formatting updates to board config files
board: ti: am62ax: Add C7
PLL calibration needs to be enabled when operating in non fractional
mode. Add the sequence to do a fast calibration when using PLL
in this mode.
Signed-off-by: Vishal Mahaveer
---
drivers/clk/ti/clk-k3-pll.c | 81 ++---
1 file changed, 75 insertions(+), 6
DRA71x processors are reduced pin and software compatible
derivative of DRA72 processors. Add support for detection
of SR2.1 version of DRA71x family of processors.
Signed-off-by: Vishal Mahaveer
---
arch/arm/include/asm/arch-omap5/omap.h | 1 +
arch/arm/include/asm/omap_common.h | 1
Update op_mode_rx flag based on CONFIG_QSPI_QUAD_SUPPORT flag,
instead of platform.
Signed-off-by: Vishal Mahaveer
Reviewed-by: Jagan Teki
---
Re-sending, because missed copying Tom Rini
http://marc.info/?l=u-boot&m=143948953129327&w=2
drivers/spi/ti_qspi.c |2 +-
1 files ch
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