+ Marek,
Hi,
On 3/14/25 5:53 AM, tkuw584...@gmail.com wrote:
> spansion_sr_ready() needs to support parallel memories configuration,
> that reads status register value from each devices and combines the
> status bits, likewise read_sr() and read_fsr().
SNOR_F_HAS_PARALLEL describes 2 flashes tha
eon.com/dgdl/Infineon-S28HS02GT_S28HS04GT_S28HL02GT_S28HL04GT_2Gb_4Gb_SEMPER_Flash_Octal_interface_1.8V_3.0V-DataSheet-v01_00-EN.pdf?fileId=8ac78c8c7e7124d1017f0631e33714d9
> Signed-off-by: Takahiro Kuwano
Reviewed-by: Tudor Ambarus
> ---
> drivers/mtd/spi/spi-nor-ids.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff
.com/dgdl/Infineon-S28HS256T_S28HL256T_256Mb_SEMPER_Flash_Octal_interface_1_8V_3-DataSheet-v02_00-EN.pdf?fileId=8ac78c8c8fc2dd9c018fc66787aa0657
> Signed-off-by: Takahiro Kuwano
Reviewed-by: Tudor Ambarus
> ---
> drivers/mtd/spi/spi-nor-ids.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/mtd/spi/spi-nor-i
On 12/10/24 3:20 AM, Abbarapu, Venkatesh wrote:
> Tudor, Do you want me to implement separate
> spi_nor_erase()/spi_nor_read()/spi_nor_write() for the parallel/stacked
> configurations?
I lean towards it, it will spare maintainers and contributors of dealing
with this temporary situation. The
On 12/5/24 4:29 AM, Venkatesh Yadav Abbarapu wrote:
> Add SPI_NOR_OCTAL_DTR_READ flags to micron flashes
> mt35xu01g and mt35xu02g. Also move them under
> CONFIG_SPI_FLASH_MT35XU config, so that in driver
> mt35xu512aba_fixups will be applied.
Why? What problem are you trying to solve? Should w
+ Marek
use get_maintainers script please
On 11/18/24 9:05 AM, Venkatesh Yadav Abbarapu wrote:
> Fix the read issue for 4byte address width by passing the entire
> length to the read function, split the memory of 16MB size banks
> only when the address width is 3byte. Also update the size when
>
On 12/3/24 11:48 AM, Abbarapu, Venkatesh wrote:
>
>
>> -Original Message-----
>> From: Tudor Ambarus
>> Sent: Tuesday, December 3, 2024 4:08 PM
>> To: Abbarapu, Venkatesh ; u-boot@lists.denx.de;
>> j-humphr...@ti.com
>> Cc: Simek, Michal ; ja..
On 11/29/24 10:22 AM, Venkatesh Yadav Abbarapu wrote:
> Enable mt35xu512aba_fixups for all mt35 series flashes to work
> in DTR mode, and return after nor->fixups is updated, otherwise
what DTR mode, 8D-8D-8D you mean?
> it will get overwritten with macronix_octal_fixups.
> This flash works in
+ Marek
Hi, Marek!
On 11/22/24 9:47 AM, Venkatesh Yadav Abbarapu wrote:
> with initial testing conducted on the
> Tenzing-se1 board using STR mode for basic erase, write,
> and readback operations.
Would you please advise us what are the minimum testing requirements for
a flash addition/update t
On 11/22/24 9:26 AM, Venkatesh Yadav Abbarapu wrote:
> Enable mt35xu512aba_fixups for all mt35 series flashes to work
> in DTR mode, and return after nor->fixups is updated, otherwise
> it will get overwritten with macronix_octal_fixups.
> This flash works in DTR mode only if CONFIG_SPI_FLASH_MT
On 11/22/24 9:40 AM, Venkatesh Yadav Abbarapu wrote:
> Add support for Winbond 256MB flash W25Q02NW which supports 4byte
> opcodes and also dual and quad read.
>
> Signed-off-by: Algapally Santosh Sagar
> Signed-off-by: Venkatesh Yadav Abbarapu
> ---
> drivers/mtd/spi/spi-nor-ids.c | 5 +
Hi,
On 11/22/24 9:47 AM, Venkatesh Yadav Abbarapu wrote:
> Added support for Macronix OSPI flash parts MX25UM51345G
> and MX66UM2G45G, with initial testing conducted on the
> Tenzing-se1 board using STR mode for basic erase, write,
> and readback operations.
>
> Signed-off-by: Tejas Bhumkar
> Si
On 10/28/24 8:27 AM, Prasad Kummari wrote:
> @@ -1155,7 +1155,35 @@ static int spi_nor_erase(struct mtd_info *mtd, struct
> erase_info *instr)
>
> if (len == mtd->size &&
> !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) {
> - ret = spi_nor_erase_c
Hi, Michal,
On 10/30/24 3:20 PM, Michal Simek wrote:
> Jagan is aware that we are using this configuration for quite a long
> time and we are still here and not leaving.
Okay, great. Would be good if you/your team can allocate time and
review/test patches that are improving/fixing the stacked/par
On 10/30/24 4:56 PM, Tom Rini wrote:
> On Wed, Oct 30, 2024 at 04:20:32PM +0100, Michal Simek wrote:
>>
>>
>> On 10/30/24 15:49, Tudor Ambarus wrote:
>>>
>>>
>>> On 10/30/24 2:17 PM, Jagan Teki wrote:
>>>> On Wed, Oct 30, 2024 at 4:15
On 10/30/24 2:17 PM, Jagan Teki wrote:
> On Wed, Oct 30, 2024 at 4:15 PM Tudor Ambarus
> wrote:
>>
>>
>>
>> On 10/30/24 10:33 AM, Jagan Teki wrote:
>>> Hi Marek,
>>>
>>> On Sun, Oct 27, 2024 at 1:48 AM Marek Vasut
>>> wrote:
I'd like to get Cc'ed to u-boot's SPI NOR patches to help review them.
The ultimate goal is to have an aligned approach in u-boot and linux.
Signed-off-by: Tudor Ambarus
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 38c714c
t")
>> Signed-off-by: Marek Vasut
>> ---
>> Cc: Andre Przywara
>> Cc: Ashok Reddy Soma
>> Cc: Jagan Teki
>> Cc: Michael Walle
>> Cc: Michal Simek
>> Cc: Patrice Chotard
>> Cc: Patrick Delaunay
>> Cc: Pratyush Yadav
>> C
+ Amit
ugh, the parallel/stacked SPI NOR thingy was applied in u-boot. We
rejected it in linux, this support shall be above SPI NOR. How about
reverting the support until we have an agreement in linux?
Or, if we want to still keep it until we come with a better approach, it
would be good if Amit
On 9/12/24 11:07 AM, Robert Marko wrote:
> On Tue, Sep 10, 2024 at 9:55 AM Tudor Ambarus wrote:
>>
>> Hiya,
>>
>> Please specify which linux commit this patch follows. It helps reviewers
>> and gives credit to the linux author.
>
> Hi,
> There isn&#x
On 08.08.2024 09:00, tkuw584...@gmail.com wrote:
> From: Takahiro Kuwano
>
> Synchronize set_4byte() with Linux v6.10 as much as possible.
Let's aim for spi-nor/for-v6.12.
>
> Introduce {nor, params}->set_4byte_addr_mode().
> The params->set_4byte_addr_mode is initialized with one of the
>
On 25.04.2024 17:36, Robert Marko wrote:
> Winbond W25Q256FV and W25Q256JV share the same JEDEC ID, but only
> W25Q256JV fully supports 4-byte OPCODE-s.
>
> In order to differentiate between them we can use the SFDP header version
> and apply a fixup post BFPT.
>
> Based on upstream Linux comm
On 08.08.2024 09:00, tkuw584...@gmail.com wrote:
> From: Takahiro Kuwano
>
> This patch partially ports the Linux commit:
> 4e53ab0c292d ("mtd: spi-nor: Set the 4-Byte Address Mode method based on
>SFDP data")
>
> BFPT[DWORD(16)] defines the methods to enter and exit the 4-Byt
Hiya,
Please specify which linux commit this patch follows. It helps reviewers
and gives credit to the linux author.
Thanks,
ta
On 08.08.2024 09:00, tkuw584...@gmail.com wrote:
> From: Takahiro Kuwano
>
> Our SFDP parsing is everything we need to support all basic operations
> of a flash device. If the flash isn't found in our in-kernel flash
> database, gracefully fall back to a driver described solely by its SFDP
> t
On 08.08.2024 09:00, tkuw584...@gmail.com wrote:
> From: Takahiro Kuwano
>
> This flag is not used in INFO table so checking info->flags has no
> effect.
>
> Signed-off-by: Takahiro Kuwano
this patch can be send on its own I guess. Maybe Jagan can take it now:
Revie
UAL_READ | SPI_NOR_QUAD_READ)
> + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
you probably chose to keep the second entry to have some sort of
alphabetical order. I'd keep the first entry as the second entry was
never used anyway, then reorder alphabetically if one cares. Just
nitpicks so fine by me either way:
Reviewed-by: Tudor Ambarus
> },
> {
> INFO("w25q32dw", 0xef6016, 0, 64 * 1024, 64,
},
> { INFO("s28hs01gt", 0x345b1b, 0, 256 * 1024, 512,
> SPI_NOR_OCTAL_DTR_READ) },
> - { INFO("s28hs02gt", 0x345b1c, 0, 256 * 1024, 1024,
> SPI_NOR_OCTAL_DTR_READ) },
> + { INFO("s28hs02gt", 0x345b1c, 0, 256 * 1024, 10
On 30.08.2024 08:00, tkuw584...@gmail.com wrote:
> From: Takahiro Kuwano
>
> Infineon S28HS256T is 256Mb Octal SPI device which has same
> functionalities with 512Mb and 1Gb parts.
>
> Signed-off-by: Takahiro Kuwano
> Reviewed-by: Pratyush Yadav
Revie
an directly revert the offending commit as it dropped support
for the 4b opcodes. Looks good anyway:
Reviewed-by: Tudor Ambarus
> Signed-off-by: Marek Vasut
> Reviewed-by: Michal Simek
> ---
> Cc: Andre Przywara
> Cc: Ashok Reddy Soma
> Cc: Dhruva Gole
> Cc: Jagan Tek
On 4/29/24 15:17, Pratyush Yadav wrote:
> On Thu, Apr 25 2024, tkuw584...@gmail.com wrote:
>
>> From: Takahiro Kuwano
>
> I wonder how authorship should work for such patches. Patches 1, 2, and
> 6 in this series are very close to what my patches did for Linux. So I
> wonder who should get au
amp;
> + nor->info->flags & SPI_NOR_OCTAL_DTR_READ)
> + nor->fixups = ¯onix_octal_fixups;
we still have the mfr checks in u-boot, sigh.
sounds sane:
Acked-by: Tudor Ambarus
> #endif /* SPI_FLASH_MACRONIX */
> }
>
ch follows the upstream linux commit:
> 5273cc6df984("mtd: spi-nor: core: Call spi_nor_post_sfdp_fixups() only
> when SFDP is defined")
this shall be the first information in the commit message.
Acked-by: Tudor Ambarus
>
> Signed-off-by: Takahiro Kuwano
> ---
> d
sure multi-pass
> programming is not attempted on the flash.
>
> Signed-off-by: Takahiro Kuwano
Acked-by: Tudor Ambarus
> ---
> drivers/mtd/spi/spi-nor-core.c | 14 ++
> 1 file changed, 14 insertions(+)
>
> diff --git a/drivers/mtd/spi/spi-nor-core.c b
enable() and/or setup() hooks that called later on.
> Just moving those to late_init() does not change functionality.
>
> Suggested-by: Tudor Ambarus
> Signed-off-by: Takahiro Kuwano
Acked-by: Tudor Ambarus
On 4/15/24 08:09, Takahiro Kuwano wrote:
> Hi Tudor,
Hi!
>
> On 4/15/2024 3:47 PM, Tudor Ambarus wrote:
>>
>>
>> On 4/15/24 05:33, tkuw584...@gmail.com wrote:
>>> From: Takahiro Kuwano
>>>
>>> default_init() fixup hook should be used t
On 4/15/24 05:33, tkuw584...@gmail.com wrote:
> From: Takahiro Kuwano
>
> This series is equivalent to the one for Linux MTD submitted by
> Pratyush Yadav.
>
> https://patchwork.ozlabs.org/project/linux-mtd/list/?series=217759&state=*
Ah, I see you specified it here. I'd argue it's better to
On 4/15/24 05:33, tkuw584...@gmail.com wrote:
> diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
> index 8f371a5213..773afd4040 100644
> --- a/drivers/mtd/spi/spi-nor-core.c
> +++ b/drivers/mtd/spi/spi-nor-core.c
> @@ -3459,6 +3459,13 @@ static void s25_default_init(s
it.
>
> Signed-off-by: Takahiro Kuwano
Please specify when a patch follows linux upstream. This follows the
following upstream linux commit:
afd473e85827 ("mtd: spi-nor: core: Allow flashes to specify MTD writesize")
Acked-by: Tudor Ambarus
On 4/15/24 05:33, tkuw584...@gmail.com wrote:
> From: Takahiro Kuwano
>
> default_init() fixup hook should be used to initialize flash parameters
> when its information is not provided in SFDP. To support that case, it
> needs to take flash_parameter structure like as other hooks.
>
> Signed-
the author. If something breaks all
parties can be involved.
This patch replicates the following upstream linux commit:
f669e74be820 ("ubi: Do not zero out EC and VID on ECC-ed NOR flashes")
Acked-by: Tudor Ambarus
Cheers,
ta
-by: Tudor Ambarus
Signed-off-by: Takahiro Kuwano
Reviewed-by: Tudor Ambarus
---
drivers/mtd/spi/spi-nor-core.c | 8
include/linux/mtd/spi-nor.h| 8
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor
register. This is useful for both readability and future possible addition
of Octal STR mode support.
Fixes: ea9a22f7e79c ("mtd: spi-nor-core: Add support for Cypress Semper flash")
Suggested-by: Tudor Ambarus
Signed-off-by: Takahiro Kuwano
Reviewed-by: Tudor Ambarus
---
include/lin
t any bitflips. Restoring the offsets
as they were before, makes the PMECC on sama5d3x capable of correcting
bitflips.
Fixes: 786f888b74 ("sama5d3: Fix Galois Field Table offsets")
Signed-off-by: Tudor Ambarus
---
arch/arm/mach-at91/include/mach/sama5d3.h | 4 ++--
1 file changed, 2 i
Enable NAND on mmc defconfig for greater flexibility and for consistency
reasons. All our other boards that have a NAND flash integrated, enable
NAND regardless of the type of the defconfig.
Signed-off-by: Tudor Ambarus
---
configs/sam9x60ek_mmc_defconfig | 7 +++
1 file changed, 7
nd other
u-boot mtd drivers has been adopted, where a heuristic implemented
by nand_check_erased_ecc_chunk() is used in order to detect and
correct empty sectors.
Tested with sama5d3_xplained and sam9x60-ek.
Signed-off-by: Kai Stuhlemmer (ebee Engineering)
Tested-by: Tudor Ambarus
[ta:
hing is fine.
Fixes: 3225f34e5c ("ARM: atmel: add sama5d3xek support")
Signed-off-by: Tudor Ambarus
---
arch/arm/mach-at91/include/mach/sama5d3.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h
b/arch/arm/mach-at91/include/m
ned-off-by: Kai Stuhlemmer (ebee Engineering)
[ta: update commit message]
Signed-off-by: Tudor Ambarus
---
arch/arm/mach-at91/include/mach/sam9x60.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-at91/include/mach/sam9x60.h
b/arch/arm/mach-at91/include/mach
at91: Convert SPL_GENERATE_ATMEL_PMECC_HEADER to
Kconfig")
Signed-off-by: Tudor Ambarus
---
configs/sama5d36ek_cmp_mmc_defconfig | 1 +
configs/sama5d36ek_cmp_nandflash_defconfig | 1 +
configs/sama5d36ek_cmp_spiflash_defconfig | 1 +
configs/sama5d3_xplained_mmc_defconfig | 1
store CONFIG_PMECC_CAP value.
Fixes: 57f76c2a47 ("configs: at91: remove SPL_GENERATE_ATMEL_PMECC_HEADER from
non-nand configs")
Signed-off-by: Tudor Ambarus
---
configs/at91sam9n12ek_mmc_defconfig | 1 +
configs/at91sam9n12ek_spiflash_defconfig| 1 +
configs/at91sam9x5ek
nto u-boot NAND memory area, and then read back. PMECC could not
correct the errors. With these everything is fine.
Kai Stuhlemmer (ebee Engineering) (1):
sam9x60.h: Fix Galois Field Table offsets
Tudor Ambarus (3):
configs: at91: Fix the involuntarily disablement of NAND PMECC
configs: at91:
51 matches
Mail list logo
