U-Boot Root Hub
1 Hub (5 Gb/s, 0mA)
U-Boot XHCI Host Controller
1 Hub (480 Mb/s, 0mA)
| U-Boot Root Hub
|
+-2 Mass Storage (480 Mb/s, 224mA)
SanDisk Dual Drive 04019c9b2e1a58f24ee318c3c123aa5
Please share you thoughts.
Thanks and Regards
--
Suniel Mahesh
Embedded Linux and Kernel Engineer
Amarula Solutions India
Please review and comment on this changeset.
Regards
Suniel
From: Michael Trimarchi
Add the needed DT overrides and configs to enable UART in SPL.
Cc: Fabio Estevam
Signed-off-by: Michael Trimarchi
Tested-by: Suniel Mahesh
---
Note:
Tested this patch on Engicam Starter Kit with I.CORE - M6 (MCIMX6Q7CVT08AC) SOM.
---
arch/arm/dts/imx6qdl-icore-u
Hi Andre,
On Mon, Jun 14, 2021 at 3:44 AM Andre Przywara wrote:
>
> On Sat, 12 Jun 2021 10:17:08 +0530
> Suniel Mahesh wrote:
>
> > Hi All,
> >
> > I am working on an Allwinner R16 and H3 based targets and I am implementing
> > system update.
> >
> &
ards
--
Suniel Mahesh
Embedded Linux and Kernel Engineer
Amarula Solutions India
On Sat, Mar 6, 2021 at 10:28 AM Suniel Mahesh
wrote:
>
> Hi All,
>
> We are trying to implement HABv4 on an IMX8M Mini based target.
>
> I have followed this discussion[1] and the patch[2].
> [1] http://u-boot.10912.n7.nabble.com/Habv4-on-imx8m-tt437232.htm
working on IMX8M Mini secure boot:
Please suggest how should we go about.
Thanks and Regards
--
Suniel Mahesh
Embedded Linux and Kernel Engineer
Amarula Solutions India
_
00.00.00 0x1d87 0x0100 Bridge device 0x04
=> nvme scan
=> nvme info
Device 0: Vendor: 0x15b7 Rev: 21110001 Prod: 2031C2440521
Type: Hard Disk
Capacity: 244198.3 MB = 238.4 GB (500118192 x 512)
=> nvme device
IDE device 0: Vendor: 0x15b7 Rev: 21110001 Prod: 2031C2440521
Type: Hard Disk
Capacity: 244198.3 MB = 238.4 GB (500118192 x 512)
Tested-by: Suniel Mahesh
>
> Jagan.
PX30.Core C.TOUCH Carrier board.
+
config TARGET_ODROID_GO2
bool "ODROID_GO2"
diff --git a/board/rockchip/evb_px30/MAINTAINERS
b/board/rockchip/evb_px30/MAINTAINERS
index 48fba4e046..2634a0aa8d 100644
--- a/board/rockchip/evb_px30/MAINTAINERS
+++ b/board/rockchip/evb_px30
From: Jagan Teki
This would be useful and recommended boot flow for new boards
which has doesn't have the DDR support yet in mainline.
Sometimes it is very useful for debugging mainline DDR support.
Documen it for px30 boot flow.
Signed-off-by: Jagan Teki
---
Changes for v2:
- no changes
do
From: Jagan Teki
Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose
carrier board with capacitive touch interface.
Genaral features:
- TFT 10.1" industrial, 1280x800 LVDS display
- Ethernet 10/100
- Wifi/BT
- USB Type A/OTG
- Audio Out
- CAN
- LVDS panel connector
SOM's like PX30.Core ne
From: Michael Trimarchi
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
General features:
- Rockchip PX30
- Up to 2GB DDR4
- eMMC 4 GB expandible
- rest of PX30 features
PX30.Core needs to mount on top of Engicam baseboards for creating
complete platform boards.
Possible baseboa
From: Jagan Teki
Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
Evaluation Board.
Genaral features:
- LCD 7" C.Touch
- microSD slot
- Ethernet 1Gb
- Wifi/BT
- 2x LVDS Full HD interfaces
- 3x USB 2.0
- 1x USB 3.0
- HDMI Out
- Mini PCIe
- MIPI CSI
- 2x CAN
- Audio Out
SOM's l
From: Jagan Teki
TARGET_EVB_PX30 can be possible to use other px30 boards.
Add the help text for existing EVB, so-that the new boards
which are resuing this config option can mention their board
help text.
This would help to track which boards are using EVB_PX30 config.
Signed-off-by: Jagan Te
+ b/board/rockchip/evb_px30/MAINTAINERS
@@ -5,3 +5,9 @@ F: board/rockchip/evb_px30
F: include/configs/evb_px30.h
F: configs/evb-px30_defconfig
F: configs/firefly-px30_defconfig
+
+PX30-Core-EDIMM2.2
+M: Jagan Teki
+M: Suniel Mahesh
+S: Maintained
+F: configs/px30-core
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
PX30.Core needs to mount on top of Engicam baseboards for creating
complete platform boards.
Possible baseboards are,
- EDIMM2.2 Starter Kit
- C.TOUCH 2.0 10.1" Open Frame
Right now boot support is working via Rockchip miniloader, wi
Hi kever,
On Tue, Jul 21, 2020 at 8:43 AM Kever Yang
wrote:
>
> On 2020/7/20 下午6:53, Jagan Teki wrote:
> > Hi Kever,
> >
> > On Sat, Jul 18, 2020 at 5:41 PM Kever Yang
> wrote:
> >> Hi Jagan,
> >>
> >> On 2020/7/10 下午11:50, Jagan Teki
On Fri, Jul 10, 2020 at 9:21 PM Jagan Teki
wrote:
> From: Suniel Mahesh
>
> Rockchip RK808 PMIC provides an integrated RTC module. It is
> commonly used with Rockchip SoCs. Add basic support to access
> date and time.
>
> Signed-off-by: Jagan Teki
>
Signed-off-by: Suni
On Sun, May 24, 2020 at 3:52 PM Hugh Cole-Baker wrote:
>
> > On 20 May 2020, at 13:08, Jagan Teki wrote:
> >
> > It seems like SPI boot on rk3399 with TPL based is unable to return
> > from ROM or switching to from TPL to SPL is unsuccessful.
> >
> > I have verified board_init_f on spl.c and the
On Wed, May 20, 2020 at 5:39 PM Jagan Teki
wrote:
> It seems like SPI boot on rk3399 with TPL based is unable to return
> from ROM or switching to from TPL to SPL is unsuccessful.
>
> I have verified board_init_f on spl.c and the control is not even
> reached here. On the other hand the SPL-alone
ver
>
> On 2020/4/23 上午12:11, su...@amarulasolutions.com wrote:
> > From: Suniel Mahesh
> >
> > RK808 PMIC is a multi functional device with an RTC. In order to access
> > RTC, bind to its parent device i.e. RK808 PMIC.
> >
> > Signed-off-by: Suniel Mahesh
e HCLK_HOST0:
> + rk_setreg(&priv->cru->clksel_con[20], BIT(5));
> + break;
> + case HCLK_HOST0_ARB:
> + rk_setreg(&priv->cru->clksel_con[20], BIT(6));
> + break;
> + case HCLK_HOST1:
> + rk_setreg(&priv->cru->clksel_con[20], BIT(7));
> + break;
> + case HCLK_HOST1_ARB:
> + rk_setreg(&priv->cru->clksel_con[20], BIT(8));
> + break;
> + default:
> + debug("%s: unsupported clk %ld\n", __func__, clk->id);
> + return -ENOENT;
> + }
> +
> + return 0;
> +}
> +
> static struct clk_ops rk3399_clk_ops = {
> .get_rate = rk3399_clk_get_rate,
> .set_rate = rk3399_clk_set_rate,
> #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
> .set_parent = rk3399_clk_set_parent,
> #endif
> + .enable = rk3399_clk_enable,
> + .disable = rk3399_clk_disable,
> };
>
> #ifdef CONFIG_SPL_BUILD
> --
> 2.17.1
>
Tested-by: Suniel Mahesh #roc-rk3399-pc
C_RK8XX=y
> CONFIG_REGULATOR_PWM=y
> CONFIG_REGULATOR_RK8XX=y
> CONFIG_PWM_ROCKCHIP=y
> CONFIG_RAM_RK3399_LPDDR4=y
> +CONFIG_DM_RESET=y
> CONFIG_BAUDRATE=150
> CONFIG_DEBUG_UART_SHIFT=2
> CONFIG_ROCKCHIP_SPI=y
> --
> 2.17.1
>
Tested-by: Suniel Mahesh #roc-rk3399-pc
ckchip_pcie_phy_init(struct rockchip_pcie_phy *phy)
> +{
> + int ret;
> +
> + ret = clk_enable(&phy->refclk);
> + if (ret) {
> + dev_err(dev, "failed to enable refclk clock\n");
> + return ret;
> + }
> +
> + ret = reset_assert(&phy->phy_rst);
> + if (ret) {
> + dev_err(dev, "failed to assert phy reset\n");
> + goto err_reset;
> + }
> +
> + return 0;
> +
> +err_reset:
> + clk_disable(&phy->refclk);
> + return ret;
> +}
> +
> +static int rockchip_pcie_phy_exit(struct rockchip_pcie_phy *phy)
> +{
> + clk_disable(&phy->refclk);
> +
> + return 0;
> +}
> +
> +static struct rockchip_pcie_phy_ops pcie_phy_ops = {
> + .init = rockchip_pcie_phy_init,
> + .power_on = rockchip_pcie_phy_power_on,
> + .power_off = rockchip_pcie_phy_power_off,
> + .exit = rockchip_pcie_phy_exit,
> +};
> +
> +int rockchip_pcie_phy_get(struct udevice *dev)
> +{
> + struct rockchip_pcie *priv = dev_get_priv(dev);
> + struct rockchip_pcie_phy *phy_priv = &priv->rk_phy;
> + ofnode phy_node;
> + u32 phandle;
> + int ret;
> +
> + phandle = dev_read_u32_default(dev, "phys", 0);
> + phy_node = ofnode_get_by_phandle(phandle);
> + if (!ofnode_valid(phy_node)) {
> + dev_err(dev, "failed to found pcie-phy\n");
> + return -ENODEV;
> + }
> +
> + phy_priv->reg_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> +
> + ret = clk_get_by_index_nodev(phy_node, 0, &phy_priv->refclk);
> + if (ret) {
> + dev_err(dev, "failed to get refclk clock phandle\n");
> + return ret;
> + }
> +
> + ret = reset_get_by_index_nodev(phy_node, 0, &phy_priv->phy_rst);
> + if (ret) {
> + dev_err(dev, "failed to get phy reset phandle\n");
> + return ret;
> + }
> +
> + phy_priv->ops = &pcie_phy_ops;
> + priv->phy = phy_priv;
> +
> + return 0;
> +}
> --
> 2.17.1
>
Tested-by: Suniel Mahesh #roc-rk3399-pc
_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001)
> +#define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002)
> +#define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040)
> +#define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0)
> +#define PCIE_CLIENT_BASIC_STATUS1 0x0048
> +#define PCIE_CLIENT_LINK_STATUS_UP GENMASK(21, 20)
> +#define PCIE_CLIENT_LINK_STATUS_MASK GENMASK(21, 20)
> +#define PCIE_LINK_UP(x) \
> + (((x) & PCIE_CLIENT_LINK_STATUS_MASK) ==
> PCIE_CLIENT_LINK_STATUS_UP)
> +#define PCIE_RC_NORMAL_BASE0x80
> +#define PCIE_LM_BASE 0x90
> +#define PCIE_LM_VENDOR_ID (PCIE_LM_BASE + 0x44)
> +#define PCIE_LM_VENDOR_ROCKCHIP0x1d87
> +#define PCIE_LM_RCBAR (PCIE_LM_BASE + 0x300)
> +#define PCIE_LM_RCBARPIE BIT(19)
> +#define PCIE_LM_RCBARPIS BIT(20)
> +#define PCIE_RC_BASE 0xa0
> +#define PCIE_RC_CONFIG_DCR (PCIE_RC_BASE + 0x0c4)
> +#define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18
> +#define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26
> +#define PCIE_RC_PCIE_LCAP (PCIE_RC_BASE + 0x0cc)
> +#define PCIE_RC_PCIE_LCAP_APMS_L0S BIT(10)
> +#define PCIE_ATR_BASE 0xc0
> +#define PCIE_ATR_OB_ADDR0(i) (PCIE_ATR_BASE + 0x000 + (i) *
> 0x20)
> +#define PCIE_ATR_OB_ADDR1(i) (PCIE_ATR_BASE + 0x004 + (i) *
> 0x20)
> +#define PCIE_ATR_OB_DESC0(i) (PCIE_ATR_BASE + 0x008 + (i) *
> 0x20)
> +#define PCIE_ATR_OB_DESC1(i) (PCIE_ATR_BASE + 0x00c + (i) *
> 0x20)
> +#define PCIE_ATR_IB_ADDR0(i) (PCIE_ATR_BASE + 0x800 + (i) * 0x8)
> +#define PCIE_ATR_IB_ADDR1(i) (PCIE_ATR_BASE + 0x804 + (i) * 0x8)
> +#define PCIE_ATR_HDR_MEM 0x2
> +#define PCIE_ATR_HDR_IO0x6
> +#define PCIE_ATR_HDR_CFG_TYPE0 0xa
> +#define PCIE_ATR_HDR_CFG_TYPE1 0xb
> +#define PCIE_ATR_HDR_RID BIT(23)
> +
> +#define PCIE_ATR_OB_REGION0_SIZE (32 * 1024 * 1024)
> +#define PCIE_ATR_OB_REGION_SIZE(1 * 1024 * 1024)
> +
> +struct rockchip_pcie {
> + fdt_addr_t axi_base;
> + fdt_addr_t apb_base;
> + int first_busno;
> + struct udevice *dev;
> +
> + /* resets */
> + struct reset_ctl core_rst;
> + struct reset_ctl mgmt_rst;
> + struct reset_ctl mgmt_sticky_rst;
> + struct reset_ctl pipe_rst;
> + struct reset_ctl pm_rst;
> + struct reset_ctl pclk_rst;
> + struct reset_ctl aclk_rst;
> +
> + /* gpio */
> + struct gpio_desc ep_gpio;
> +
> + /* vpcie regulators */
> + struct udevice *vpcie12v;
> + struct udevice *vpcie3v3;
> + struct udevice *vpcie1v8;
> + struct udevice *vpcie0v9;
> +};
> --
> 2.17.1
>
Tested-by: Suniel Mahesh #roc-rk3399-pc
gt; rk_setreg(&priv->cru->clksel_con[20], BIT(8));
> break;
> + case SCLK_PCIEPHY_REF:
> + rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
> + break;
> default:
> debug("%s: unsupported clk %ld\n", __func__, clk->id);
> return -ENOENT;
> --
> 2.17.1
>
Tested-by: Suniel Mahesh #roc-rk3399-pc
e HCLK_HOST0:
> + rk_setreg(&priv->cru->clksel_con[20], BIT(5));
> + break;
> + case HCLK_HOST0_ARB:
> + rk_setreg(&priv->cru->clksel_con[20], BIT(6));
> + break;
> + case HCLK_HOST1:
> + rk_setreg(&priv->cru->clksel_con[20], BIT(7));
> + break;
> + case HCLK_HOST1_ARB:
> + rk_setreg(&priv->cru->clksel_con[20], BIT(8));
> + break;
> + default:
> + debug("%s: unsupported clk %ld\n", __func__, clk->id);
> + return -ENOENT;
> + }
> +
> + return 0;
> +}
> +
> static struct clk_ops rk3399_clk_ops = {
> .get_rate = rk3399_clk_get_rate,
> .set_rate = rk3399_clk_set_rate,
> #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
> .set_parent = rk3399_clk_set_parent,
> #endif
> + .enable = rk3399_clk_enable,
> + .disable = rk3399_clk_disable,
> };
>
> #ifdef CONFIG_SPL_BUILD
> --
> 2.17.1
>
Tested-by: Suniel Mahesh # roc-rk3399-pc
On Thu, Mar 26, 2020 at 3:33 PM Kever Yang
wrote:
>
> On 2020/3/25 下午11:37, su...@amarulasolutions.com wrote:
> > From: Suniel Mahesh
> >
> > roc-rk3399-pc has an FE1.1 USB 2.0 HUB which connects two USB ports
> > (HOST1 and HOST2). For end devices to work we need
Hi Kever,
On Thu, Apr 2, 2020 at 8:16 PM Suniel Mahesh
wrote:
> On Thu, Apr 2, 2020 at 6:32 PM Kever Yang
> wrote:
> >
> > Hi Sunil, Jagan,
> >
> > What suppose to be for LEDs status base on this patch and patch[0]?
>
May I know the reason why this p
niel
>
>
> Thanks,
>
> - Kever
>
> [0] https://patchwork.ozlabs.org/patch/1258094/
>
> On 2020/4/2 下午8:52, su...@amarulasolutions.com wrote:
>
> From: Suniel Mahesh
>
> In case of a power interruption, human intervention is required which
> is not desirable if the
+ board_early_init_f();
> +
> #if !defined(CONFIG_TPL) || defined(CONFIG_SPL_OS_BOOT)
> debug("\nspl:init dram\n");
> ret = uclass_get_device(UCLASS_RAM, 0, &dev);
> --
> 2.17.1
>
Tested-by: Suniel Mahesh
("DRAM init failed: %d\n", ret);
> return;
> }
> +
> +#ifdef CONFIG_TPL_BANNER_PRINT
> + printascii("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - " \
> + U_BOOT_TIME ")\n");
> +#endif
> }
>
> int board_return_to_bootrom(struct spl_image_info *spl_image,
> --
> 2.17.1
>
Tested-by: Suniel Mahesh
board_early_init_f();
> +
> ret = uclass_get_device(UCLASS_RAM, 0, &dev);
> if (ret) {
> printf("DRAM init failed: %d\n", ret);
> --
> 2.17.1
>
Tested-by: Suniel Mahesh
; + spl_gpio_output(gpio0, GPIO(BANK_A, 2), 0);
> + }
> +
> +/* 4. Turn on red LED, termed as full power */
> spl_gpio_output(gpio0, GPIO(BANK_B, 5), 1);
>
> return 0;
> --
> 2.17.1
>
Tested-by: Suniel Mahesh
- printf("Reset cause: %s\n", get_reset_cause());
> + printf("Reset cause: %s\n", cause);
> +
> + /**
> +* reset_reason env is used by rk3288, due to special use case
> +* to figure it the boot behavior. so keep this as it is.
> +*/
> + env_set("reset_reason", cause);
>
> /* TODO print operating temparature and clock */
>
> return 0;
> }
> +#endif
> --
> 2.17.1
>
Tested-by: Suniel Mahesh
Hi stefano,
Can you please review this patch, Its been a longtime since its arrival on the
list, and still lying there untouched.
Regards
Suniel
On 02/09/19 19:13, suni...@techveda.org wrote:
> From: Suniel Mahesh
>
> Enable driver model for SPI and SPI_FLASH to remove the
Hi all,
On 14/09/19 12:55, Sam Protsenko wrote:
> Hi Grygorii,
>
> On Fri, Sep 13, 2019 at 8:58 PM Grygorii Strashko
> wrote:
>>
>>
>>
>> On 12/09/2019 19:33, Sam Protsenko wrote:
>>> Hi Stefan,
>>>
>>> On Thu, Sep 12, 2019 at 5:38 PM Stefan Roese wrote:
Hi Sam,
On 12.09.19
On 13/09/19 23:28, Grygorii Strashko wrote:
>
>
> On 12/09/2019 19:33, Sam Protsenko wrote:
>> Hi Stefan,
>>
>> On Thu, Sep 12, 2019 at 5:38 PM Stefan Roese wrote:
>>>
>>> Hi Sam,
>>>
>>> On 12.09.19 15:45, Sam Protsenko wrote:
Hi Suniel,
After transition to DM WDT, watchdog timer
Hi Sam,
On 12/09/19 22:03, Sam Protsenko wrote:
> Hi Stefan,
>
> On Thu, Sep 12, 2019 at 5:38 PM Stefan Roese wrote:
>>
>> Hi Sam,
>>
>> On 12.09.19 15:45, Sam Protsenko wrote:
>>> Hi Suniel,
>>>
>>> After transition to DM WDT, watchdog timer on BeagleBone Black resets
>>> the board after 1 minu
On 17/07/19 22:58, Tom Rini wrote:
> On Fri, Jul 12, 2019 at 02:53:47PM +0530, suni...@techveda.org wrote:
>
>> From: Suniel Mahesh
>>
>> This patch disables DM watchdog support for SPL builds and uses
>> the legacy omap watchdog on TI AM335x chipsets.
>>
>
On 02/07/19 01:55, Marek Vasut wrote:
> On 7/1/19 8:45 AM, Suniel Mahesh wrote:
>> Hi Marek,
>>
>> May I know if this patch series is still under review ?
>
> I guess Stefano is taking them for next ... or ?
>
Hi Marek/Stefano,
Because of this entry "Make SP
On 02/07/19 01:55, Marek Vasut wrote:
> On 7/1/19 8:45 AM, Suniel Mahesh wrote:
>> Hi Marek,
>>
>> May I know if this patch series is still under review ?
>
> I guess Stefano is taking them for next ... or ?
>
Hi Marek,
Because of this change set applied to u-bo
Agreed with frank. My patches for watchdog DM conversion depends on this change
set.
tested on AM335x based Beaglebone Black
Tested-by: Suniel Mahesh
Regards
--
Suniel Mahesh
Embedded Linux, Kernel & U-Boot engineer
https://github.com/sunielmahesh
www.tuxtrons.com
https://github.com/tech
based BeagleBone Black, and they look good.
Regards
--
Suniel Mahesh
Embedded Linux, Kernel & U-Boot engineer
https://github.com/sunielmahesh
www.tuxtrons.com
https://github.com/techveda
Hyderabad, India
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h
oblem.
Regards
--
Suniel Mahesh
Embedded Linux, Kernel & U-Boot engineer
https://github.com/sunielmahesh
www.tuxtrons.com
https://github.com/techveda
Hyderabad, India
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Hi,
Is this patch under review ?
facing the same problem on TI Based AM33XX platform.
--
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Looks like a detailed explanation of the problem and a patch has already been
submitted.
http://u-boot.10912.n7.nabble.com/PATCH-1-3-board-r-move-initr-serial-to-be-called-before-initr-watchdog-tc369705.html
Regards
--
Suniel Mahesh
Embedded Linux, Kernel & U-Boot engineer
https://github
=>
stdio_init_tables => initr_serial => initr_watchdog
Couldn't find an explanation for such behaviour ?
Is it ok to move initr_watchdog() ahead and after initr_serial() in board_r.c ?
pointers please.
The watchdog DM driver has successfully got binded (checked the debug log).
Thank
Hi Patrick,
thanks for the pointer and I understood your point.
CONFIG_SYS_MALLOC_LEN is defined as SZ_32M which should be enough i guess ?
still trying to figure out what is causing that error.
--
Sent from: http://u-boot.10912.n7.nabble.com/
_
ame..
Any pointers on what could be the issue ?
Regards
--
Suniel Mahesh
Embedded Linux, Kernel & U-Boot engineer
https://github.com/sunielmahesh
www.tuxtrons.com
https://github.com/techveda
Hyderabad, India
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On 26/06/19 16:49, Marek Vasut wrote:
> On 6/26/19 12:54 PM, Jagan Teki wrote:
>> On Wed, Jun 26, 2019 at 4:07 PM Stefan Roese wrote:
>>>
>>> On 26.06.19 11:53, Suniel Mahesh wrote:
>>>> Hi,
>>>>
>>>> I am trying to convert watchdo
driver model in SPL - by Simon Glass)
2. The stack allocated for SPL in SRAM is 6KB and 12799 bytes for RAM Exec
vectors,
tracing data and static variables. can we do something here, by borrowing some
bytes ?
Or any possible solutions ?
Regards
--
Suniel Mahesh
_
acity: No
Capacity: 1.9 GiB
Bus Width: 4-bit
Erase Group Size: 512 Bytes
Thanks
Regards
--
Suniel Mahesh
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On Friday 18 August 2017 01:00 PM, Jaehoon Chung wrote:
> On 08/04/2017 06:34 PM, Suniel Mahesh wrote:
>> On Monday 17 July 2017 04:38 PM, Jaehoon Chung wrote:
>>> On 06/20/2017 01:53 AM, suni...@techveda.org wrote:
>>>> From: Suniel Mahesh
>>>>
>>
On Monday 17 July 2017 04:38 PM, Jaehoon Chung wrote:
> On 06/20/2017 01:53 AM, suni...@techveda.org wrote:
>> From: Suniel Mahesh
>>
>> priv pointer should be freed before returning with an error value
>> from exynos_dwmci_get_config().
>>
>> Signed-off-by:
On Monday 17 July 2017 04:38 PM, Jaehoon Chung wrote:
> On 06/19/2017 04:33 PM, suni...@techveda.org wrote:
>> From: Suniel Mahesh
>>
>> __be32_to_cpu() accepts argument of type __be32. This patch changes type of
>> the buffer in ALLOC_CACHE_ALIGN_BUFFER macro to _
On Tuesday 06 June 2017 05:37 AM, Tom Rini wrote:
> On Tue, Jun 06, 2017 at 12:42:21AM +0530, suni...@techveda.org wrote:
>
>> From: Suniel Mahesh
>>
>> Interrupt-parent property is defined in the root node as
>> "interrupt-parent = <&intc>".
On Tuesday 02 May 2017 04:19 PM, Jagan Teki wrote:
On Sat, Apr 29, 2017 at 12:32 AM, wrote:
From: Suniel Mahesh
.probe method has been assigned twice when declaring a
a driver with U_BOOT_DRIVER(). Removed one of them.
Thanks,
Can you mark the details here like which commit has done this
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