return ret;
> + return -EINVAL;
> }
> nfc->addr_base[chip_cs] = addr;
> }
>
Hi Andrew
Reviewed-by: Patrice Chotard
Thanks
Patrice
: Add STM32MP13x SPL specific DT additions
ARM: dts: stm32: Add SPL specifics for DH STM32MP13xx DHCOR DHSBC
ARM: dts: stm32: Switch defconfig to SPL for DH STM32MP13xx DHCOR DHSBC
Patrice Chotard (6):
ARM: stm32mp: Add STM32MP23 support
ARM: dts: stm32: Add stm32mp235f-dk-u
On 7/28/25 15:08, Patrice Chotard wrote:
> Fix STMicroelectronics spelling in comments.
>
> Signed-off-by: Patrice Chotard
> ---
>
> arch/arm/include/asm/arch-am33xx/mem.h | 2 +-
> arch/arm/include/asm/arch-omap5/mem.h | 2 +-
> include/configs/stm32mp25_st_com
On 7/28/25 09:19, Patrice Chotard wrote:
> From: Patrick Delaunay
>
> Since SYS_MALLOC_F_LEN increasing to 0x210 on STM32MP13, the
> pre-console buffer is overlapped by stack (0xC040 + 0x210),
> so the this buffer must be moved just before the bootstage to avoid is
On 6/26/25 10:22, Patrice Chotard wrote:
> Enable OF_UPSTREAM_BUILD_VENDOR and set OF_UPSTREAM_VENDOR.
>
> Signed-off-by: Patrice Chotard
> ---
>
> configs/stm32mp13_defconfig | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/configs/st
On 6/26/25 10:08, Patrice Chotard wrote:
> Add STM32MP23 support which is a cost optimized of STM32MP25.
> More details available at:
> https://www.st.com/en/microcontrollers-microprocessors/stm32mp2-series.html
>
> Signed-off-by: Patrice Chotard
> ---
>
> arch/
On 6/26/25 10:17, Patrice Chotard wrote:
> Cosmetic update to replace space by tab in sys_proto.h
>
> Signed-off-by: Patrice Chotard
> ---
>
> .../arm/mach-stm32mp/include/mach/sys_proto.h | 32 +--
> 1 file changed, 16 insertions(+), 16 deletions(-)
&
On 6/26/25 10:08, Patrice Chotard wrote:
> Add U-Boot specific file for stm32mp235f-dk board
>
> Signed-off-by: Patrice Chotard
> ---
>
> arch/arm/dts/stm32mp23-u-boot.dtsi | 104
> arch/arm/dts/stm32mp235f-dk-u-boot.dtsi | 27 ++
&g
On 7/28/25 10:47, Patrice CHOTARD wrote:
>
>
> On 7/24/25 13:37, Andrew Goodbody wrote:
>> Smatch reported a warning about a shift macro being used as a mask. Make
>> the obvious changes to make this register read calculation work the same
>> as the previous ones.
On 7/30/25 14:53, Patrice Chotard wrote:
> STM32F4/F7 and H7 series doesn't have a clear reset register, so
> set_clr field must be set to false.
>
> Fixes: 0994a627c278 ("reset: stm32mp25: add stm32mp25 reset driver")
>
> Signed-off-by: Patrice Chotard
>
On 7/7/25 22:20, Alice Guo (OSS) wrote:
> From: Alice Guo
>
> Commit aa7bdc1af505 ("clk: scmi: manage properly the clk identifier with
> CFF") enables CONFIG_CLK_AUTO_ID, so need to use clk_get_id() to get the
> real SCMI CLK ID, otherwise wrong ID is used when set clk parent.
>
> Fixes: aa7b
ad from QSPI NOR respectively,
> etzpc bus switch to simple-bus to prevent interference from TFABOOT
> specific configuration, and RCC configuration to define clock tree
> configuration used by this platform.
>
> Reviewed-by: Patrice Chotard
> Signed-off-by: Marek Vasut
> ---
&
chips which are not used on STM32MP13xx DHCOR are
> moved into STM32MP15xx DHSOM defconfigs. Changes to STM32MP13xx DHCOR
> defconfig then enable SPL support, CCF in SPL to configure clock, pin
> configuration support in SPL, and OpTee OS start support in U-Boot.
>
> Reviewed-by: Patri
On 6/30/25 02:10, Marek Vasut wrote:
> Add DRAM settings for 512 MiB of DRAM variant of DH STM32MP13xx DHCOR DHSBC.
>
> Reviewed-by: Patrice Chotard
> Signed-off-by: Marek Vasut
> ---
> Cc: Cheick Traore
> Cc: Fabrice Gasnier
> Cc: Gatien Chevallier
> Cc: L
, and syscon-reboot node so U-Boot
> can reset the system without having to rely on PSCI call.
>
> Reviewed-by: Patrice Chotard
> Signed-off-by: Marek Vasut
> ---
> Cc: Cheick Traore
> Cc: Fabrice Gasnier
> Cc: Gatien Chevallier
> Cc: Lionel Debieve
> Cc: Pascal Zimmer
On 6/30/25 02:10, Marek Vasut wrote:
> Add default STM32MP13xx debug UART initialization. This is similar
> to STM32MP15xx debug UART initialization, except the RCC registers
> are at different offsets and the UART pinmux pins are different.
>
> Reviewed-by: Patrice Chotard
On 6/30/25 02:10, Marek Vasut wrote:
> Factor out common parts of STM32MP15xx DRAM controller configuration DT
> description into stm32mp1-ddr.dtsi and introduce stm32mp13-ddr.dtsi which
> describes STM32MP13xx DRAM controller configuration in DT.
>
> Reviewed-by: Patrice Chotar
be placed in DRAM.
>
> Reviewed-by: Patrice Chotard
> Signed-off-by: Marek Vasut
> ---
> Cc: Cheick Traore
> Cc: Fabrice Gasnier
> Cc: Gatien Chevallier
> Cc: Lionel Debieve
> Cc: Pascal Zimmermann
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: Simon
On 6/30/25 02:10, Marek Vasut wrote:
> The STM32MP13xx PMIC initialization for DDR3 DRAM type is similar
> to the STM32MP15xx PMIC initialization, except the VTT rail is not
> enabled. Fill in the STM32MP13xx support.
>
> Reviewed-by: Patrice Chotard
> Signed-off-by: Marek
On 6/30/25 02:10, Marek Vasut wrote:
> Introduce Kconfig options used by SPL on STM32MP13xx and isolate
> the Kconfig options only used in case TFA BL2 is used as a SPL
> behind CONFIG_TFABOOT dependency.
>
> Reviewed-by: Patrice Chotard
> Signed-off-by: Marek Vasut
> --
On 6/30/25 02:10, Marek Vasut wrote:
> Add hardware initialization for the STM32MP13xx in SPL. This is
> similar to STM32MP15xx except the code has to enable MCE to bring
> DRAM controller up later.
>
> Reviewed-by: Patrice Chotard
> Signed-off-by: Marek Vasut
> ---
>
On 6/30/25 08:17, Patrice CHOTARD wrote:
>
>
> On 6/30/25 02:09, Marek Vasut wrote:
>> The stm32-reset-core.h is located in drivers/reset/stm32/ , it has to
>> be included using "stm32-reset-core.h" and not ,
>> otherwise the build fails. Fix it.
>>
On 7/28/25 11:04, Patrice CHOTARD wrote:
>
>
> On 6/20/25 17:50, Cheick Traore wrote:
>> Enable the following configs:
>>
>> - CONFIG_MFD_STM32_TIMERS: enables support for the STM32 multifunction
>>timer
>> - CONFIG_
On 7/28/25 11:03, Patrice CHOTARD wrote:
>
>
> On 6/20/25 17:49, Cheick Traore wrote:
>> Add support for STM32MP25 SoC.
>> IPIDR register is used to check the hardware configuration register
>> when available to gather the number of complementary outputs.
>>
On 7/28/25 11:03, Patrice CHOTARD wrote:
>
>
> On 6/20/25 17:49, Cheick Traore wrote:
>> Add support for STM32MP25 SoC.
>> Identification and hardware configuration registers allow to read the
>> timer version and capabilities (counter width, ...).
>> So, r
STM32F4/F7 and H7 series doesn't have a clear reset register, so
set_clr field must be set to false.
Fixes: 0994a627c278 ("reset: stm32mp25: add stm32mp25 reset driver")
Signed-off-by: Patrice Chotard
---
drivers/reset/stm32/stm32-reset.c | 2 +-
1 file changed, 1 insertion
On 7/29/25 06:05, Marek Vasut wrote:
> On 6/29/25 9:08 PM, Marek Vasut wrote:
>
> Hi,
>
diff --git a/arch/arm/mach-stm32mp/Kconfig.13x b/arch/arm/mach-
stm32mp/Kconfig.13x
index bc8b3f8cf77..cecf9e3b8c7 100644
--- a/arch/arm/mach-stm32mp/Kconfig.13x
+++ b/arch/arm/mac
Fix STMicroelectronics spelling in comments.
Signed-off-by: Patrice Chotard
---
arch/arm/include/asm/arch-am33xx/mem.h | 2 +-
arch/arm/include/asm/arch-omap5/mem.h | 2 +-
include/configs/stm32mp25_st_common.h | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm
F is not set
> +CONFIG_MFD_STM32_TIMERS=y
> CONFIG_CMD_MEMINFO=y
> CONFIG_CMD_MEMTEST=y
> +CONFIG_DM_PWM=y
> +CONFIG_PWM_STM32=y
> CONFIG_CMD_CLK=y
> CONFIG_CMD_FUSE=y
> CONFIG_CMD_GPIO=y
> +CONFIG_CMD_PWM=y
> # CONFIG_CMD_LOADB is not set
> CONFIG_CMD_MMC=y
> CONFIG_CMD_CACHE=y
Hi Cheick
Reviewed-by: Patrice Chotard
Thanks
_pwm_ops = {
>
> static const struct udevice_id stm32_pwm_ids[] = {
> { .compatible = "st,stm32-pwm" },
> + { .compatible = "st,stm32mp25-pwm" },
> { }
> };
>
Hi Cheick
Reviewed-by: Patrice Chotard
Thanks
; return 0;
> }
> @@ -60,13 +89,16 @@ static int stm32_timers_probe(struct udevice *dev)
>
> priv->rate = clk_get_rate(&clk);
>
> - stm32_timers_get_arr_size(dev);
> + ret = stm32_timers_probe_hwcfgr(dev);
> + if (ret)
> + clk_disable(&clk);
>
> return ret;
> }
>
> static const struct udevice_id stm32_timers_ids[] = {
> { .compatible = "st,stm32-timers" },
> + { .compatible = "st,stm32mp25-timers", .data = STM32MP25_TIM_IPIDR },
> {}
> };
>
Hi Cheick
Reviewed-by: Patrice Chotard
Thanks
L1FRACR_FRACN1_SHIFT) + 1;
>
> vco = (pllsrc / divm1) * divn1;
> rate = (pllsrc * fracn1) / (divm1 * 8192);
>
> ---
> base-commit: 3532f1f5edfc97c9dcea723cdeb732eda44bc669
> change-id: 20250724-clk_stm32-b097d32f3fe9
>
> Best regards,
Hi Andrew
Reviewed-by: Patrice Chotard
Thanks
C000= Load Address of U-Bootwith CONFIG_TEXT_BASE
Fixes: 93c962c7af7e ("configs: stm32mp13: increase SYS_MALLOC_F_LEN to
0x21")
Signed-off-by: Patrick Delaunay
Signed-off-by: Patrice Chotard
---
arch/arm/mach-stm32mp/Kconfig.13x | 2 +-
1 file changed, 1 inser
On 6/30/25 08:17, Patrice CHOTARD wrote:
>
>
> On 6/30/25 02:09, Marek Vasut wrote:
>> The stm32-reset-core.h is located in drivers/reset/stm32/ , it has to
>> be included using "stm32-reset-core.h" and not ,
>> otherwise the build fails. Fix it.
>>
river")
> Signed-off-by: Marek Vasut
> ---
> Cc: Gabriel Fernandez
> Cc: Mattijs Korpershoek
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: Sebastian Reichel
> Cc: Simon Glass
> Cc: Tom Rini
> Cc: u-boot@lists.denx.de
> Cc: uboot-st...@st-md-mailma
Enable OF_UPSTREAM_BUILD_VENDOR and set OF_UPSTREAM_VENDOR.
Signed-off-by: Patrice Chotard
---
configs/stm32mp13_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configs/stm32mp13_defconfig b/configs/stm32mp13_defconfig
index ecd4f866fe9..bf07dfe8b6a 100644
--- a/configs
Cosmetic update to replace space by tab in sys_proto.h
Signed-off-by: Patrice Chotard
---
.../arm/mach-stm32mp/include/mach/sys_proto.h | 32 +--
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h
b/arch/arm/mach
Add STM32MP23 support which is a cost optimized of STM32MP25.
More details available at:
https://www.st.com/en/microcontrollers-microprocessors/stm32mp2-series.html
Signed-off-by: Patrice Chotard
---
arch/arm/mach-stm32mp/Kconfig | 27 +++
arch/arm/mach-stm32mp/Kconfig.23x
Add U-Boot specific file for stm32mp235f-dk board
Signed-off-by: Patrice Chotard
---
arch/arm/dts/stm32mp23-u-boot.dtsi | 104
arch/arm/dts/stm32mp235f-dk-u-boot.dtsi | 27 ++
2 files changed, 131 insertions(+)
create mode 100644 arch/arm/dts/stm32mp23-u
ARM: stm32: Auto-detect ROM API table on STM32MP15xx
clk: stm32mp13: Fix typo in STM32MP13 RCC driver
clk: stm32mp13: Add SPL support and clock tree init to STM32MP13 RCC
driver
ram: stm32mp1: Add STM32MP13xx support
tools: stm32image: Add support for STM32 Image V2.0
Patrice
+U-Boot mailing list i forgot to set.
On 6/9/25 14:40, Patrice CHOTARD wrote:
> Hi all
>
> Since commit c5d685b8993c ("usb: dwc2: Unify flush and reset logic with
> v4.20a support") on next branch
> "ums" command is broken, we got the following issue on ST
On 6/9/25 15:20, Sumit Garg wrote:
> Hi Dario,
>
> On Sat, Jun 07, 2025 at 11:37:09AM +0200, Dario Binacchi wrote:
>> Allow expanding possible configurations for the same peripheral,
>> consistent with the scheme adopted in Linux.
>>
>> Signed-off-by: Dario Binacchi
>> Link:
>> https://lore.k
On 6/7/25 11:37, Dario Binacchi wrote:
> The series adds support for stm32h747-discovery board.
>
> Detailed information can be found at:
> https://www.st.com/en/evaluation-tools/stm32h747i-disco.html
>
>
> Dario Binacchi (9):
> ARM: dts: stm32h7-pinctrl: add _a suffix to u[s]art_pins phand
On 5/27/25 15:27, Patrice Chotard wrote:
>
> Add clock and reset drivers support for STM32MP2 platforms:
> - add SCMI clock protocol v2.0 support
> - introduce CONFIG_CLK_AUTO_ID flag to support unique clk ID
> when several clock providers are in use.
> - add STM3
On 6/9/25 10:34, Patrice CHOTARD wrote:
>
>
> On 6/9/25 10:07, Lukasz Majewski wrote:
>> Hi Patrice,
>>
>>> On 6/7/25 11:37, Dario Binacchi wrote:
>>>> The board includes an STM32H747XI SoC with the following resources:
>>>> - 2 Mbytes
On 5/21/25 16:40, Patrice CHOTARD wrote:
>
>
> On 5/12/25 18:45, Marek Vasut wrote:
>> The ROM API table location is passed to the SPL by BootROM in register r0,
>> make use of this, store the content of r0 and later use it to access the
>> ROM API table to de
On 5/27/25 17:59, Patrice CHOTARD wrote:
>
>
> On 5/12/25 19:09, Marek Vasut wrote:
>> Add support for generating STM32 Image V2.0, which is used by STM32MP13xx.
>> The image header layout is similar to STM32MP15xx STM32 Image V1.0, but is
>> different enough to jus
On 5/27/25 17:48, Patrice CHOTARD wrote:
>
>
> On 5/12/25 19:09, Marek Vasut wrote:
>> Add support for configuring DRAM controller on STM32MP13xx SoC.
>> The DRAM controller is basically identical to the DWC controller
>> on STM32MP15xx SoC, except the bus wid
On 5/27/25 17:47, Patrice CHOTARD wrote:
>
>
> On 5/12/25 19:08, Marek Vasut wrote:
>> Add SPL support and clock tree init to STM32MP13 RCC driver. This
>> consists of two parts, make SCMI into an optional dependency and
>> add clock tree initialization. The SCMI
On 5/27/25 17:47, Patrice CHOTARD wrote:
>
>
> On 5/12/25 19:08, Marek Vasut wrote:
>> Add SPL support and clock tree init to STM32MP13 RCC driver. This
>> consists of two parts, make SCMI into an optional dependency and
>> add clock tree initialization. The SCMI
On 5/21/25 16:40, Patrice CHOTARD wrote:
>
>
> On 5/12/25 18:51, Marek Vasut wrote:
>> Fix basic typo, missing t in security . No functional change .
>>
>> Signed-off-by: Marek Vasut
>> ---
>> Cc: Patrice Chotard
>> Cc: Patrick Delaunay
>>
On 5/21/25 15:59, Patrice CHOTARD wrote:
>
>
> On 5/12/25 18:44, Marek Vasut wrote:
>> The DBGMCU block is available at address 0x50081000 both on STM32MP13xx
>> and on STM32MP15xx . There is no reason to limit the DBGMCU macro being
>> set only on STM32MP
On 5/21/25 15:50, Patrice CHOTARD wrote:
>
>
> On 5/12/25 18:44, Marek Vasut wrote:
>> The STM32MP13xx has only 128 kiB of SYSRAM starting at address 0x2ffe .
>> The STM32MP15xx has 256 kiB of SYSRAM starting at address 0x2ffc . Make
>> sure both SoCs
On 5/21/25 15:47, Patrice CHOTARD wrote:
>
>
> On 5/12/25 18:11, Marek Vasut wrote:
>> Drop a space after tab, no functional change.
>>
>> Signed-off-by: Marek Vasut
>> ---
>> Cc: Patrice Chotard
>> Cc: Patrick Delaunay
>> Cc: Simon Glass
On 5/19/25 13:23, Patrice Chotard wrote:
> From: Simeon Marijon
>
> TAMP backup registers will be exposed as nvmem cells.
>
> Each registers ([0..127] for STM32MP2, [0..31] for STM32MP1) could be
> exposed as nvmem cells under the nvram node in device tree
>
> Signe
gt; +++ b/drivers/clk/stm32/clk-stm32h7.c
>>> @@ -114,6 +114,7 @@
>>> #defineQSPISRC_PER_CK 3
>>>
>>> #define PWR_CR30x0c
>>> +#define PWR_CR3_LDOEN BIT(1)
>>> #define PWR_CR3_SCUEN
/*
> + * Copyright (C) 2025 Dario Binacchi
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#include
> +#include
> +
> +/* For booting Linux, use the first 16MB of memory */
> +#define CFG_SYS_BOOTMAPSZSZ_16M
> +
> +#define CFG_SYS_FLASH_BASE 0x0800
> +
> +#define CFG_SYS_HZ_CLOCK 100
> +
> +#define BOOT_TARGET_DEVICES(func) \
> + func(MMC, mmc, 0)
> +
> +#include
> +#define CFG_EXTRA_ENV_SETTINGS \
> + "kernel_addr_r=0xD0008000\0"\
> + "fdtfile=stm32h747i-disco.dtb\0"\
> + "fdt_addr_r=0xD0408000\0" \
> + "scriptaddr=0xD0418000\0" \
> + "pxefile_addr_r=0xD0428000\0" \
> + "ramdisk_addr_r=0xD0438000\0" \
> + BOOTENV
> +
> +#endif /* __CONFIG_H */
Reviewed-by: Patrice Chotard
Thanks
Patrice
,
&g
d";
> + pinctrl-0 = <ðernet_rmii>;
> + pinctrl-names = "default";
> + phy-mode = "rmii";
> + phy-handle = <&phy0>;
> +
> + mdio0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
&
UART8_CK>;
> + };
> +
> usart1: serial@40011000 {
> compatible = "st,stm32h7-uart";
> reg = <0x40011000 0x400>;
Reviewed-by: Patrice Chotard
Thanks
Patrice
pins2 {
> + pinmux = ; /* USART1_RX */
> + bias-disable;
> + };
> + };
> +
> usart2_pins_a: usart2-0 {
> pins1 {
> pinmux = ; /* USART2_TX */
Reviewed-by: Patrice Chotard
Thanks
Patrice
pins2 {
> + pinmux = ; /* UART8_RX */
> + bias-disable;
> + };
> + };
> +
> usart1_pins_a: usart1-0 {
> pins1 {
> pinmux = ; /* USART1_TX */
Reviewed-by: Patrice Chotard
Thanks
Patrice
+#define UART7_CK 132
> #define HDMICEC_CK 133
> #define I2C3_CK 134
> #define I2C2_CK 135
Reviewed-by: Patrice Chotard
Thanks
Patrice
- st,stm32h743i-eval
>- const: st,stm32h743
> + - items:
> + - enum:
> + - st,stm32h747i-disco
> + - const: st,stm32h747
>- items:
>- enum:
>- st,stm32h750i-art-pi
Reviewed-by: Patrice Chotard
Thanks
Patrice
ctrl-names = "default";
> status = "disabled";
> };
>
> &usart3 {
> pinctrl-names = "default";
> - pinctrl-0 = <&usart3_pins>;
> + pinctrl-0 = <&usart3_pins_a>;
> dmas = <&dmamux1 45 0x400 0x05>,
> <&dmamux1 46 0x400 0x05>;
> dma-names = "rx", "tx";
> @@ -221,7 +221,7 @@
> };
>
> &uart4 {
> - pinctrl-0 = <&uart4_pins>;
> + pinctrl-0 = <&uart4_pins_a>;
> pinctrl-names = "default";
> status = "okay";
> };
Reviewed-by: Patrice Chotard
Thanks
Patrice
ox/config.mk
> +++ b/arch/sandbox/config.mk
> @@ -3,7 +3,7 @@
>
> PLATFORM_CPPFLAGS += -D__SANDBOX__ -U_FORTIFY_SOURCE
> PLATFORM_CPPFLAGS += -fPIC -ffunction-sections -fdata-sections
> -PLATFORM_LIBS += -lrt
> +PLATFORM_LIBS += -lrt -lpthread
> SDL_CONFIG ?= sdl2-config
>
On 6/4/25 15:56, Tom Rini wrote:
> On Wed, Jun 04, 2025 at 03:33:31PM +0530, Anshul Dalal wrote:
>> Hi Raymond,
>>
>> On Wed Jun 4, 2025 at 2:30 AM IST, Raymond Mao wrote:
>>> Hi Tom,
>>>
>>> On Tue, 3 Jun 2025 at 15:23, Tom Rini wrote:
On Tue, Jun 03, 2025 at 02:00:23PM -0400, Raymon
On 6/4/25 08:50, Michael Nazzareno Trimarchi wrote:
> Hi
>
> On Wed, Jun 4, 2025 at 8:48 AM Michael Nazzareno Trimarchi
> wrote:
>>
>> Hi Patrice
>>
>> On Wed, Jun 4, 2025 at 8:46 AM Patrice CHOTARD
>> wrote:
>>>
>>>
>>
On 6/4/25 08:14, Michael Nazzareno Trimarchi wrote:
> Hi
>
> On Wed, Jun 4, 2025 at 8:02 AM Patrice CHOTARD
> wrote:
>>
>>
>>
>> On 5/27/25 15:27, Patrice Chotard wrote:
>>> From: Patrick Delaunay
>>>
>>> Add a new config CONF
On 5/27/25 15:27, Patrice Chotard wrote:
> From: Gabriel Fernandez
>
> Implement STM32MP25 reset drivers using stm32-core-reset API.
> This reset stm32-reset-core API and will be able to use DT binding
> index started from 0.
>
> This patch also moves legacy reset into
On 5/27/25 15:27, Patrice Chotard wrote:
> From: Valentin Caron
>
> Since clock protocol 2.0, SCMI specification add an option field
> "clock_enable_delay" to CLOCK_ATTRIBUTES command.
>
> scmi_read_resp_from_smt() will return an error ("Buffer too small"
On 5/27/25 15:27, Patrice Chotard wrote:
> From: Gabriel Fernandez
>
> Check clock security to avoid access at boot time.
>
> Signed-off-by: Gabriel Fernandez
> Signed-off-by: Patrice Chotard
> Cc: Lukasz Majewski
> Cc: Sean Anderson
> ---
>
> (no ch
On 5/27/25 15:27, Patrice Chotard wrote:
> From: Patrick Delaunay
>
> Each clock identifier needs to be unique when CCF is activated,
> and it is not respected today by SCMI clock driver.
>
> This patch supports a unique clk id by using the uclass API
> clk_get_id()
On 5/27/25 15:27, Patrice Chotard wrote:
> From: Patrick Delaunay
>
> Add a new config CONFIG_CLK_AUTO_ID to support a unique clk id
> for all the clock providers, managed by clk uclass, when the clock
> reference arg[0] is the same.
>
> When the CONFIG is activated, th
On 5/27/25 15:27, Patrice Chotard wrote:
> From: Gabriel Fernandez
>
> Add clock driver support for STM32MP25 SoCs.
>
> Signed-off-by: Gabriel Fernandez
> Signed-off-by: Valentin Caron
> Signed-off-by: Patrice Chotard
> Cc: Lukasz Majewski
> Cc: Sean Anderson
On 5/27/25 15:27, Patrice Chotard wrote:
> From: Patrick Delaunay
>
> Add private uclass data for "stm32-usbphyc-clk" as it is not done
> by the driver model.
>
> This clk struct is needed by CCF to save the unique id used to identify
> each clock.
>
On 5/27/25 15:27, Patrice Chotard wrote:
> From: Patrick Delaunay
>
> Update the existing test dm_test_clk_ccf() with new CLK_ID macro.
>
> Signed-off-by: Patrick Delaunay
> Signed-off-by: Patrice Chotard
> Cc: Lukasz Majewski
> Cc: Sean Anderson
> --
On 5/27/25 15:27, Patrice Chotard wrote:
> From: Gabriel Fernandez
>
> In RCC the ops of the CCF registered CLK device can be called directly,
> this patch avoid recursive call of clk_ function done by CCF clock
> framework which update the clock information, for example
On 5/27/25 15:27, Patrice Chotard wrote:
> From: Patrick Delaunay
>
> Update CLK ID to avoid 0 id, used for dummy clock with CCF
> and to allow selection by clk_get_by_id, used to
> get private data associated to the UCLASS_CLK device
>
> Signed-off-by: Patrick Dela
On 5/27/25 15:27, Patrice Chotard wrote:
> From: Patrick Delaunay
>
> Update the sandbox driver to allow support of the
> CONFIG_CLK_AUTO_ID by using the new API clk_get_id()
> to get the internal SANDBOX identifier.
>
> With CONFIG_CLK_AUTO_ID, clk->id have
alue
1522 /19 stm32mp15_basic
Completed: 19 total built, 19 newly), duration 0:07:48, rate 0.04
Thanks
Patrice
> ---
> Cc: Cheick Traore
> Cc: Fabrice Gasnier
> Cc: Gatien Chevallier
> Cc: Lionel Debieve
> Cc: Pascal Zimmermann
> Cc: Patrice Cho
t; Cc: Fabrice Gasnier
> Cc: Gatien Chevallier
> Cc: Lionel Debieve
> Cc: Pascal Zimmermann
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: Simon Glass
> Cc: Sughosh Ganu
> Cc: Tom Rini
> Cc: u-b...@dh-electronics.com
> Cc: u-boot@lists.denx.de
> Cc: uboot-st...@s
by: Marek Vasut
> ---
> Cc: Cheick Traore
> Cc: Fabrice Gasnier
> Cc: Gatien Chevallier
> Cc: Lionel Debieve
> Cc: Pascal Zimmermann
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: Simon Glass
> Cc: Sughosh Ganu
> Cc: Tom Rini
> Cc: u-b...@dh-ele
, and syscon-reboot node so U-Boot
> can reset the system without having to rely on PSCI call.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Cheick Traore
> Cc: Fabrice Gasnier
> Cc: Gatien Chevallier
> Cc: Lionel Debieve
> Cc: Pascal Zimmermann
> Cc: Patrice Chotard
On 5/12/25 19:21, Marek Vasut wrote:
> Add DRAM settings for 512 MiB of DRAM variant of DH STM32MP13xx DHCOR DHSBC.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Cheick Traore
> Cc: Fabrice Gasnier
> Cc: Gatien Chevallier
> Cc: Lionel Debieve
> Cc: Pascal Zimmer
sut
> ---
> Cc: Cheick Traore
> Cc: Fabrice Gasnier
> Cc: Gatien Chevallier
> Cc: Lionel Debieve
> Cc: Pascal Zimmermann
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: Simon Glass
> Cc: Sughosh Ganu
> Cc: Tom Rini
> Cc: u-b...@dh-electronics.com
; ---
> Cc: Cheick Traore
> Cc: Fabrice Gasnier
> Cc: Gatien Chevallier
> Cc: Lionel Debieve
> Cc: Pascal Zimmermann
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: Simon Glass
> Cc: Sughosh Ganu
> Cc: Tom Rini
> Cc: u-b...@dh-electronics.com
Traore
> Cc: Fabrice Gasnier
> Cc: Gatien Chevallier
> Cc: Lionel Debieve
> Cc: Pascal Zimmermann
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: Simon Glass
> Cc: Sughosh Ganu
> Cc: Tom Rini
> Cc: u-b...@dh-electronics.com
> Cc: u-boot@lists.denx.de
> Cc
be placed in DRAM.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Cheick Traore
> Cc: Fabrice Gasnier
> Cc: Gatien Chevallier
> Cc: Lionel Debieve
> Cc: Pascal Zimmermann
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: Simon Glass
> Cc: Sughosh Ganu
>
le
> new file mode 100644
> index 000..a70d4b445db
> --- /dev/null
> +++ b/arch/arm/mach-stm32/stm32h7/Makefile
> @@ -0,0 +1,6 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +# (C) Copyright 2025
> +# Johannes Krottmayer
> +
> +obj-y += lowlevel.o
Hi Johannes
Reviewed-by: Patrice Chotard
Thanks
Patrice
bg(dev, "Not already started\n");
> + break;
> + default:
> + /* Optional SMCWD_GET_TIMELEFT not implemented */
> + break;
> + }
> +
> return 0;
> }
>
Reviewed-by: Patrice Chotard
Thanks
Patrice
- Rename RCC_USB2CFGR to RCC_USBHCFGR
Gabriel Fernandez (4):
clk: stm32mp25: Add clock driver support
clk: stm32mp25: implement clock check security function
clk: stm32: fix clock counter
reset: stm32mp25: add stm32mp25 reset driver
Patrice Chotard (2):
ARM: dts: stm32: switch from fix
On 5/8/25 23:24, Johannes Krottmayer wrote:
> The pins for USART1 have must be changed to other values, to
> support the STM32H747 discovery board.
>
> Signed-off-by: Johannes Krottmayer
> Cc: Patrick Delaunay
> Cc: Patrice Chotard
> ---
> dts/upstream/src/arm/st/
On 5/12/25 19:21, Marek Vasut wrote:
> Add hardware initialization for the STM32MP13xx in SPL. This is
> similar to STM32MP15xx except the code has to enable MCE to bring
> DRAM controller up later.
>
> Signed-off-by: Marek Vasut
Reviewed-by: Patrice Chotard
Thanks
Patri
c: Fabrice Gasnier
> Cc: Gatien Chevallier
> Cc: Lionel Debieve
> Cc: Pascal Zimmermann
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: Simon Glass
> Cc: Sughosh Ganu
> Cc: Tom Rini
> Cc: u-b...@dh-electronics.com
> Cc: u-boot@lists.denx.de
> Cc: uboot-
ode at least attempts to align the V1 and V2 image handling where
> possible.
>
> Signed-off-by: Marek Vasut
Reviewed-by: Patrice Chotard
Thanks
Patrice
> ---
> Cc: Ilias Apalodimas
> Cc: Julien Masson
> Cc: Mattijs Korpershoek
> Cc: Patrice Chotard
> Cc: Patrick Delauna
ew PLL2000 for
> PLL1 on STM32MP13xx .
>
> Signed-off-by: Marek Vasut
Huge work !!
Reviewed-by: Patrice Chotard
Thanks
Patrice
> ---
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: Sean Anderson
> Cc: Tom Rini
> Cc: u-boot@lists.denx.de
> Cc: uboot-st...@st-md
ame way.
>
> Signed-off-by: Marek Vasut
Reviewed-by: Patrice Chotard
Thanks
Patrice
> ---
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: Simon Glass
> Cc: Tom Rini
> Cc: u-boot@lists.denx.de
> Cc: uboot-st...@st-md-mailman.stormreply
On 5/8/25 23:23, Johannes Krottmayer wrote:
> These patch series adds support for the STM32H747 discovery
> board from STMicroelectronics.
>
> Johannes Krottmayer (10):
> arm: mach-stm32: stm32h7: add initial lowlevel early function
> arm: mach-stm32: stm32h7: add initial Makefile
> arm:
rlr = readl(priv->base + IWDG_RLR);
> + writel(rlr, priv->base + IWDG_RLR);
> + ret = readl_poll_timeout(priv->base + IWDG_SR, sr, sr & SR_RVU,
> + TIMEOUT_US);
> + if (!ret)
> + wdt_set_force_autostart(dev);
> +
> + writel(KR_KEY_DWA, priv->base + IWDG_KR);
> + }
> +
> dev_dbg(dev, "IWDG init done\n");
>
> return 0;
Reviewed-by: Patrice Chotard
Thanks
Patrice
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