On 2/10/14, Guillaume Gardet wrote:
> Hi,
>
>
> Le 10/02/2014 10:22, Mj Embd a écrit :
>> Hi,
>>
>> Compiled Head and flashed u-boot.bin for arndale config. No display on
>> terminal in uboot.
>> Switched to linaro git (u-boot-linaro-stable.git) and u-
Hi,
Compiled Head and flashed u-boot.bin for arndale config. No display on
terminal in uboot.
Switched to linaro git (u-boot-linaro-stable.git) and u-boot log is showing up.
Something wrong?
--
-mj
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a) step 1 - compile and build the bin / etf
b) step 2 - create an asm - objdump -DS
c) find the lds file
d) locate uboot.map
start from __start. (keep an arm manual handy) & begin.
:)
On 1/23/14, JYOTI DUBEY wrote:
> Can anyone tell how to understand the flow of u-boot source code? I am
> worki
When "64-bit ARMv9" was announced ?
On Thu, Sep 26, 2013 at 4:46 AM, Scott Wood wrote:
> On Tue, 2013-09-17 at 16:37 +0800, FengHua wrote:
> >
> >
> > > -原始邮件-
> > > 发件人: "Scott Wood"
> > > 发送时间: 2013年9月17日 星期二
> > > 收件人: feng...@phytium.com.cn
> > > 抄送: u-boot@lists.denx.de, tr...@ti.
Hi York,
I was thinking about your problem and this could be a solution
mpc85xx uses a family of ddr controllers.
I believe they would be migrated to LayerScape,
Freescale has also i.mx4/5/6 series and coming i.mx8, that series
uses/might use another ddr controller
Option1
As you suggested which
On Fri, Sep 20, 2013 at 6:12 AM, Christoffer Dall <
christoffer.d...@linaro.org> wrote:
> On Fri, Sep 20, 2013 at 03:20:15AM +0530, Mj Embd wrote:
> > Just checking, is the mcr p15,0,r1,c1,c1,0 in sync with the following
> text
> > . I could be wrong here, just checking
&
On Fri, Sep 20, 2013 at 4:05 AM, Peter Maydell wrote:
> On 20 September 2013 06:55, Mj Embd wrote:
> > Hello Andre,
> > I need a bit clarification here, if you read the next line after the line
> > you have quoted. It clearly says that you can use a MCR to change from
> &
mends that software does not alter SCR.NS
in any mode except Monitor mode. ARM deprecates changing SCR.NS in any
other mode."
On Fri, Sep 20, 2013 at 3:09 AM, Mj Embd wrote:
>
>
>
> On Fri, Sep 20, 2013 at 3:01 AM, Andre Przywara > wrote:
>
>> On 09/19/2013 10:
Just checking, is the mcr p15,0,r1,c1,c1,0 in sync with the following text
. I could be wrong here, just checking
B1.5.1 Arm Arch Ref Manual
-
To avoid security holes, software must not:
-
— Change from Secure to Non-secure state by using an MSR or CPS
instruction
to swit
On Fri, Sep 20, 2013 at 3:01 AM, Andre Przywara
wrote:
> On 09/19/2013 10:38 PM, Mj Embd wrote:
>
>> Hello Christoffer,
>>
>> I agree with both of you points.
>>
>> What I found different in 2 approaches is that in your approach
>> S->Monitor->
handlers.
I was just suggesting that the best approach to be used ...
Best Regards,
mj
On 9/20/13, Christoffer Dall wrote:
> On Fri, Sep 20, 2013 at 01:27:48AM +0530, Mj Embd wrote:
>> two quick points
>> (a) xen already has a mode_switch code, so AFAIK xen might not use it
>
On 9/20/13, Christoffer Dall wrote:
> On Thu, Sep 19, 2013 at 10:00:03PM +0530, Mj Embd wrote:
>> Hi Andre,
>>
>> There is another approach taken in xen. (xen/arch/arm/mode_switch.S)
>> Which do you think is the better approach
>>
> Hi there,
>
>
Hi Andre,
There is another approach taken in xen. (xen/arch/arm/mode_switch.S)
Which do you think is the better approach
Regards
-mj
On 9/19/13, Andre Przywara wrote:
> While actually switching to non-secure state is one thing, another
> part of this process is to make sure that we still have f
Hi @Samsung,
Great that you have starting posting 5420 patches, one basic question
(a) What is the booting procedure for the secondary cores
(b) What is the booting procedure for the Little Secondary cores...
Would you be pushing the patches for these as well
On 9/19/13, Simon Glass wrote:
Thanks for replying Simon. Comments inline
On 9/18/13, Simon Glass wrote:
> Hi MJ,
>
> On Wed, Sep 18, 2013 at 12:41 AM, MJ embd wrote:
>> Hi Simon/All,
>>
>> Any comments
>>
>> On 9/17/13, Simon Glass wrote:
>>> Hi,
>>>
>>> Yo
Thanks, after a long google I figured it out. Will write a post about
it on my blog.
On 9/19/13, Simon Glass wrote:
> Hi MJ,
>
> On Mon, Sep 16, 2013 at 8:23 PM, MJ embd wrote:
>
>> PS: Last message was sent without body, please ignore
>>
>> 0 down vote fa
gt; Simon
> On Sep 16, 2013 8:26 PM, "MJ embd" wrote:
>
>> Reminder, Please can anyone respond
>>
>> On 9/16/13, MJ embd wrote:
>> > Hi,
>> >
>> > I was trying to understand the booting (till linux) on samsung exynos
>> >
Trivial Question, Which part of the SPL code uses HEAP?
On 9/16/13, Prabhakar Kushwaha wrote:
>
> Signed-off-by: Prabhakar Kushwaha
> ---
>
> Add support of 2 stage NAND boot loader in cornet platforms using SPL
> framework.
> This will be helpful for those SoC which has less internal SRAM(128K)
Few quick comments
1) wouldnt it be better to create a .S file and move big chunk of
inline assembly there
2) can the multiple occurences of .word be substituted with something else?
On 9/17/13, Alexander Tarasikov wrote:
> ---
> arch/arm/lib/bootm.c | 89
>
t; and modules (if applicable)?
>
> In my mind, I am thinking to restructure arch/powerpc/cpu/mpc8xxx/ddr/
> to driver/ddr/fsl/ so the same driver can be shared as far as the DDR IP
> is the same (or similar).
>
> York
>
>
> On 09/17/2013 09:34 AM, MJ embd wrote:
>> H
Hi York,
There is no generic driver. AFAIK. Having worked on both mpc85xx and ARM
I can tell you about samsung 5250. There are 2 uboots (one spl and other main).
In case of sd/mmc boot the internal rom copies the spl uboot to iRAM
and the spl boot loader initialises the DDR3.
you can check for b
--
-mj
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Reminder, Please can anyone respond
On 9/16/13, MJ embd wrote:
> Hi,
>
> I was trying to understand the booting (till linux) on samsung exynos
> 5250. As this is my first on ARM Cortex. I have a few questions, so
> following is a step by step understanding and [Q] mentions the
PS: Last message was sent without body, please ignore
0 down vote favorite
I am trying to understand a second level makefile of uboot (this
makefile was in a sub directory)
a) What is the difference between $(COBJS:.o=.c) and COBJS := test_main.o
b) What is the meaning of $(call cmd
Hi,
I was trying to understand the booting (till linux) on samsung exynos
5250. As this is my first on ARM Cortex. I have a few questions, so
following is a step by step understanding and [Q] mentions the
question I am asking
[1] At POR (Power on Reset) the Internal Boot rom code executes, and
ch
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