From: LekKit <50500857+lek...@users.noreply.github.com>
Fix compile warning with !CONFIG_FDT_64BIT by
casting the variable in the debug print.
Signed-off-by: Eva Kurchatova
Reported-by: Leo Yu-Chi Liang
---
drivers/video/simplefb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Use CSR_UCCTLCOMMAND instead of CSR_MCCTLCOMMAND
to do cache flush operation in M-mode and S-mode.
Signed-off-by: Leo Yu-Chi Liang
---
arch/riscv/cpu/andes/cache.c| 4 +---
arch/riscv/include/asm/arch-andes/csr.h | 2 +-
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a
Cache could be enabled in harts_early_init board-specific hook,
so remove cache enablement in start.S
Signed-off-by: Leo Yu-Chi Liang
---
arch/riscv/cpu/start.S | 4
1 file changed, 4 deletions(-)
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index a9e1935692..8e58f641f1
Signed-off-by: Leo Yu-Chi Liang
---
drivers/cache/cache-andes-l2.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/cache/cache-andes-l2.c b/drivers/cache/cache-andes-l2.c
index 45d29f2fbd..bc6f7ed7c1 100644
--- a/drivers/cache/cache-andes-l2.c
+++ b/drivers
Use CSR_UCCTLCOMMAND instead of CSR_MCCTLCOMMAND
to do cache flush operation in M-mode and S-mode.
Signed-off-by: Leo Yu-Chi Liang
---
arch/riscv/cpu/andes/cache.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/riscv/cpu/andes/cache.c b/arch/riscv/cpu/andes/cache.c
Signed-off-by: Leo Yu-Chi Liang
---
arch/riscv/Kconfig| 4 +-
arch/riscv/cpu/{andesv5 => andes}/Kconfig | 4 +-
arch/riscv/cpu/{andesv5 => andes}/Makefile| 0
arch/riscv/cpu/{andesv5 => andes}/cache.c | 12 +++---
arch/riscv/cpu/{andesv5 =>
Signed-off-by: Leo Yu-Chi Liang
---
arch/riscv/Kconfig| 2 +-
arch/riscv/cpu/{andesv5 => andes}/Kconfig | 4 +-
arch/riscv/cpu/{andesv5 => andes}/Makefile| 0
arch/riscv/cpu/{andesv5 => andes}/cache.c | 12 +++---
arch/riscv/cpu/{andesv5 =>
Signed-off-by: Leo Yu-Chi Liang
---
arch/riscv/Kconfig| 2 +-
arch/riscv/cpu/{andesv5 => andes}/Kconfig | 4 +-
arch/riscv/cpu/{andesv5 => andes}/Makefile| 0
arch/riscv/cpu/{andesv5 => andes}/cache.c | 12 +++---
arch/riscv/cpu/{andesv5 =>
There could be two memory allocation scheme in SPL phase.
Explicitly print the corresponding error message.
Signed-off-by: Leo Yu-Chi Liang
---
common/spl/spl_fit.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index
Enable MISC_INIT_R for ae350 to support CPU name detection
and re-sync the configs via make savedefconfig.
Signed-off-by: Leo Yu-Chi Liang
---
configs/ae350_rv32_defconfig | 5 +++--
configs/ae350_rv32_spl_defconfig | 5 +++--
configs/ae350_rv32_spl_xip_defconfig | 5 +++--
configs
Detect CPU name through marchid and then save it to env.
Signed-off-by: Leo Yu-Chi Liang
---
board/AndesTech/ae350/ae350.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/board/AndesTech/ae350/ae350.c b/board/AndesTech/ae350/ae350.c
index bef9e3149e..4e53fee5d2
Andes CPU supports cache and TLB ECC.
Enable them by default.
Signed-off-by: Leo Yu-Chi Liang
---
arch/riscv/cpu/andesv5/cpu.c| 3 ++-
arch/riscv/include/asm/arch-andes/csr.h | 3 +++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch
Andes CPU has memboost feature including prefetch,
write-around and non-blocking load. Enable them by default.
Signed-off-by: Leo Yu-Chi Liang
---
arch/riscv/cpu/andesv5/cpu.c| 9 -
arch/riscv/include/asm/arch-andes/csr.h | 6 ++
2 files changed, 14 insertions(+), 1
Kconfig provides SYS_[I|D]CACHE_OFF config options to switch off caches.
Provide the corresponding implementation to the options.
Signed-off-by: Leo Yu-Chi Liang
---
arch/riscv/cpu/andesv5/cpu.c | 25 -
board/AndesTech/ae350/ae350.c | 3 ++-
2 files changed, 18
Signed-off-by: Leo Yu-Chi Liang
---
arch/riscv/include/asm/arch-andes/csr.h | 20
arch/riscv/include/asm/csr.h| 1 +
2 files changed, 9 insertions(+), 12 deletions(-)
diff --git a/arch/riscv/include/asm/arch-andes/csr.h
b/arch/riscv/include/asm/arch-andes
Detect CPU name through marchid and then save it to env.
Signed-off-by: Leo Yu-Chi Liang
---
board/AndesTech/ae350/ae350.c | 20
1 file changed, 20 insertions(+)
diff --git a/board/AndesTech/ae350/ae350.c b/board/AndesTech/ae350/ae350.c
index bef9e3149e..9faf46d96e 100644
Andes CPU supports cache and TLB ECC.
Enable them by default.
Signed-off-by: Leo Yu-Chi Liang
---
arch/riscv/cpu/andesv5/cpu.c| 1 +
arch/riscv/include/asm/arch-andes/csr.h | 3 +++
2 files changed, 4 insertions(+)
diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5
Andes CPU has memboost feature including prefetch,
write-around and non-blocking load. Enable them by default.
Signed-off-by: Leo Yu-Chi Liang
---
arch/riscv/cpu/andesv5/cpu.c| 7 +++
arch/riscv/include/asm/arch-andes/csr.h | 6 ++
2 files changed, 13 insertions(+)
diff
Kconfig provides SYS_[I|D]CACHE_OFF config options
to switch off caches. Implement the corresponding options.
Signed-off-by: Leo Yu-Chi Liang
---
arch/riscv/cpu/andesv5/cpu.c | 9 +++--
board/AndesTech/ae350/ae350.c | 3 ++-
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a
Signed-off-by: Leo Yu-Chi Liang
---
arch/riscv/include/asm/arch-andes/csr.h | 19 ---
1 file changed, 8 insertions(+), 11 deletions(-)
diff --git a/arch/riscv/include/asm/arch-andes/csr.h
b/arch/riscv/include/asm/arch-andes/csr.h
index 393d51c6dd..93aa8b2343 100644
--- a/arch
Adjust the initial stack pointer address to 0x1000(256M)
Signed-off-by: Leo Yu-Chi Liang
---
Change v1 -> v2:
* Modify the address from 0x100(16MB) to 0x1000(256MB)
---
configs/ae350_rv32_spl_defconfig | 6 +++---
configs/ae350_rv32_spl_xip_defconfig | 6 +++---
conf
The current ae350-related defconfigs could also
support newer Andes CPU IP, so modify the names of CPU
from ax25 to andesv5, and board name from ax25-ae350 to ae350.
Signed-off-by: Leo Yu-Chi Liang
Reviewed-by: Yu Chien Peter Lin
Reviewed-by: Rick Chen
---
arch/riscv/Kconfig
ine CONFIG_NR_CPUS to be 1 if CONFIG_NR_CPUS is not defined.
Tested on sifive unmatched.
Signed-off-by: Xiang W
Signed-off-by: Leo Yu-Chi Liang
---
Changes v2 -> v3:
- Fix the calculation of the GD_AVAILABLE_HARTS start address
- Fix compilation error for defconfigs that do not define CONFIG_N
Signed-off-by: Leo Yu-Chi Liang
---
configs/ae350_rv32_spl_defconfig | 6 +++---
configs/ae350_rv32_spl_xip_defconfig | 6 +++---
configs/ae350_rv64_spl_defconfig | 6 +++---
configs/ae350_rv64_spl_xip_defconfig | 6 +++---
4 files changed, 12 insertions(+), 12 deletions(-)
diff --git a
The current ae350-related defconfigs could also
support newer Andes CPU IP, so modify the names of CPU
from ax25 to andesv5, and board name from ax25-ae350 to ae350.
Signed-off-by: Leo Yu-Chi Liang
---
arch/riscv/Kconfig | 8
arch/riscv/cpu/{ax25
to be returned. Fix this.
Fixes: 2e8d2f88439d ("riscv: Remove OF_PRIOR_STAGE from RISC-V boards")
Signed-off-by: Rick Chen
Signed-off-by: Leo Yu-Chi Liang
---
arch/riscv/cpu/start.S | 3 ++-
board/AndesTech/ax25-ae350/ax25-ae350.c | 17 +++--
2 files changed, 13
l off confusing #ifdef __mem_pci block")
Signed-off-by: Leo Yu-Chi Liang
Reviewed-by: Bin Meng
---
arch/riscv/include/asm/io.h | 117 +---
1 file changed, 1 insertion(+), 116 deletions(-)
diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/i
of the file.
Signed-off-by: Leo Yu-Chi Liang
---
arch/riscv/include/asm/io.h | 117 +---
1 file changed, 1 insertion(+), 116 deletions(-)
diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
index fc39bb2c70..49bffac03c 100644
--- a/arch/riscv
$cmd
}
The address where the kernel is loaded can be altered by
changing the value of KERNEL_IMAGE_ADDR.
Signed-off-by: Leo Yu-Chi Liang
---
include/configs/ax25-ae350.h | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/include/configs/ax25-ae350.h b/include/configs/a
According to ./include/linux/kconfig.h,
CONFIG_IS_ENABLED(OF_BOARD) expands to 0
when CONFIG_SPL_BUILD is defined because
there is no CONFIG_SPL_OF_BOARD.
Use #if defined instead.
Fixes: 2e8d2f88439d ("riscv: Remove OF_PRIOR_STAGE from RISC-V boards")
Signed-off-by: Leo Yu-Chi Liang
This statement has an unmatched parentheses, fix it.
Signed-off-by: Leo Yu-Chi Liang
---
common/image-board.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/image-board.c b/common/image-board.c
index e7660352e9..ddf30c6730 100644
--- a/common/image-board.c
+++ b
According to ./include/linux/kconfig.h,
CONFIG_IS_ENABLED(OF_BOARD) expands to 0
when CONFIG_SPL_BUILD is defined because
there is no CONFIG_SPL_OF_BOARD.
Use #if defined instead.
Signed-off-by: Leo Yu-Chi Liang
---
board/AndesTech/ax25-ae350/ax25-ae350.c | 4 ++--
1 file changed, 2 insertions
If Coherence Manager were not set in the beginning,
u-boot-spl would sometimes fail to boot to u-boot proper.
Enable CM and I/D cache at the same time in harts_early_init
Signed-off-by: Leo Yu-Chi Liang
---
arch/riscv/cpu/ax25/cpu.c | 42 +++
1 file changed
Switch off SMP support when building u-boot-spl would cause linking error as
follow:
undefined reference to 'secondary hart relocate' and 'smp_call_function'.
Add macro to wrap up proper code region that needs SMP configuration on.
Signed-off by: Leo Liang
Cc: r...@andestech.com
---
arch/riscv/
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