On Tue, 2017-01-10 at 18:34 +, Mark Rutland wrote:
> Looking at the git log for arch/arm64/boot/dts/arm, most updates are
> simply adding new descriptions, so a DTB from a year ago should work
> just fine with mainline (modulo the Juno PCI window issue, which was a
> DTB bug). Upgrading kernel
On Mon, 2016-09-26 at 13:38 +0100, Sudeep Holla wrote:
>
> On 26/09/16 13:30, Jon Medhurst (Tixy) wrote:
> > On Fri, 2016-09-23 at 17:38 +0100, Sudeep Holla wrote:
> >> Commit f225d39d3093 ("vexpress: Check TC2 firmware support before
> >> defaulting
> &
On Fri, 2016-09-23 at 17:38 +0100, Sudeep Holla wrote:
> Commit f225d39d3093 ("vexpress: Check TC2 firmware support before defaulting
> to nonsec booting") added support to check if the firmware on TC2 is
> configured appropriately before booting in nonsec/hyp mode.
>
> However when booting in no
On Fri, 2016-09-23 at 17:38 +0100, Sudeep Holla wrote:
> Commit f225d39d3093 ("vexpress: Check TC2 firmware support before defaulting
> to nonsec booting") added support to check if the firmware on TC2 is
> configured appropriately before booting in nonsec/hyp mode.
>
> However when booting in no
On Fri, 2016-09-23 at 16:10 +0100, Sudeep Holla wrote:
> +#ifdef CONFIG_OF_BOARD_SETUP
> +int ft_board_setup(void *fdt, bd_t *bd)
> +{
> + int offset, tmp, len;
> + const struct fdt_property *prop;
> + const char *cci_compatible = "arm,cci-400-ctrl-if";
> +
> + if (!armv7_bo
On Sun, 2016-08-14 at 16:05 -0400, Tom Rini wrote:
> On Thu, Jun 23, 2016 at 01:37:32PM +0100, Jon Medhurst (Tixy) wrote:
>
> > The firmware on TC2 needs to be configured appropriately before booting
> > in nonsec mode will work as expected, so test for this and fall back
The firmware on TC2 needs to be configured appropriately before booting
in nonsec mode will work as expected, so test for this and fall back to
sec mode if required.
Signed-off-by: Jon Medhurst
---
This is an implementation of Andre's suggestion in
http://lists.denx.de/pipermail/u-boot/2016-June
On Wed, 2016-06-22 at 15:53 +0100, Andre Przywara wrote:
> Hi,
>
> On 22/06/16 15:34, Jon Medhurst (Tixy) wrote:
> > When CPU's come out of reset they are in secure state supervisor mode,
> > so this is the state Linux kernel entry point is called in when it
> >
When CPU's come out of reset they are in secure state supervisor mode,
so this is the state Linux kernel entry point is called in when it
brings up secondary CPU cores or the primary CPU restarts after power
management has sent it through an off/on transition.
As U-Boot starts the kernel in hyperv
On Wed, 2011-11-30 at 07:51 -0700, Tom Rini wrote:
> On Wed, Nov 30, 2011 at 1:32 AM, Jon Medhurst (Tixy)
> wrote:
> > On Tue, 2011-11-29 at 13:46 -0700, Tom Rini wrote:
> >> On Tue, Nov 29, 2011 at 6:46 AM, Jon Medhurst (Tixy)
> >> wrote:
> >> > Ext
On Tue, 2011-11-29 at 13:46 -0700, Tom Rini wrote:
> On Tue, Nov 29, 2011 at 6:46 AM, Jon Medhurst (Tixy)
> wrote:
> > Extend the default boot sequence on Versatile Express to load a boot
> > script from MMC.
> >
> > Signed-off-by: Jon Medhurst
>
> Is the
Extend the default boot sequence on Versatile Express to load a boot
script from MMC.
Signed-off-by: Jon Medhurst
---
include/configs/vexpress_common.h | 20 ++--
1 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/include/configs/vexpress_common.h
b/include/confi
The new IO FPGA implementation for Versatile Express contains an MMCI
(PL180) cell with the FIFO extended to 128 words. This causes the
read_bytes() function to go into an infinite loop; as it will wait for
for the half-full signal (SDI_STA_RXFIFOBR) if there are more than 8
words remaining (SDI_FI
On Wed, 2011-10-05 at 10:58 +0100, Pawel Moll wrote:
> > That's useful to know. The PL180 code is also used for U8500, I don't
> > know if that implements the peripheral ID register; though I guess any
> > probing could be limited to vexpress anyway.
>
> STE have the same "problems" with FIFO size
On Wed, 2011-10-05 at 10:30 +0100, Pawel Moll wrote:
> Hi Tixy,
>
> > One possible fix is to add some build time configuration to change
> > SDI_FIFO_BURST_SIZE for the new implementation.
>
> You can also detect the configuration in runtime, basing on PeriphID:
>
> http://infocenter.arm.com/he
From: Jon Medhurst
The new IO FPGA implementation for Versatile Express contains an MMCI
(PL180) cell with the FIFO extended to 128 words. This causes the
read_bytes() function to go into an infinite loop; as it will wait for
for the half-full signal (SDI_STA_RXFIFOBR) if there are more than 8
wo
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