Hi.
On 11.02.2017 16:08, Icenowy Zheng wrote:
[..]
> @@ -299,6 +190,13 @@ static void mctl_h3_zq_calibration_quirk(struct
> dram_para *para)
> {
> struct sunxi_mctl_ctl_reg * const mctl_ctl =
> (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
> + int zq_count;
>
Hi,
renaming is not quite enough, see the comments below.
On 11.02.2017 16:08, Icenowy Zheng wrote:
> The DesignWare DRAM controller used by H3 and newer SoCs use a bit to
> identify whether the DRAM is half-width.
>
> As H3 itself come with 32-bit DRAM, the two modes of the bit used to be
> nam
the respective register. Fix this.
>>>
>>> Reported-by: Jens Kuske
>>> Signed-off-by: Andre Przywara
>>> ---
>>> arch/arm/mach-sunxi/dram_sun8i_h3.c | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/arch/ar
On 30.09.2016 15:17, Jagan Teki wrote:
> On Fri, Sep 30, 2016 at 6:20 PM, Jens Kuske wrote:
>> On 30.09.2016 14:24, Jagan Teki wrote:
>>> On Wed, Sep 21, 2016 at 11:38 PM, Jens Kuske wrote:
>>>> H3 seems to have a silicon bug breaking the impedance calibration.
On 30.09.2016 14:24, Jagan Teki wrote:
> On Wed, Sep 21, 2016 at 11:38 PM, Jens Kuske wrote:
>> H3 seems to have a silicon bug breaking the impedance calibration.
>> This is currently worked around in software by multiple steps
>> combining the results to replace the wrong v
lack of
information and affected boards till now.
This commit adds a simplified version without correction factor,
which would be 1.00 for all known boards anyway.
Signed-off-by: Jens Kuske
---
Hi,
This has been tested by an Armbian user:
http://forum.armbian.com/index.php/topic/872-beelink-x2
.
Signed-off-by: Jens Kuske
---
Hi all,
this might fix some of the DRAM reliability problems seen on H3 boards,
but I could only test it on one board myself, where it only improves
results for dram clocks above 648 MHz. But my board didn't suffer
from reliability problems at 672 MHz, so may
Hi Chen-Yu,
On 06/01/16 08:13, Chen-Yu Tsai wrote:
> Hi everyone,
>
> This series enables PSCI support for the H3. Like other Allwinner SoCs,
> the implementation only supports PSCI 0.1, specifically only secondary
> CPU boot/hotplug.
Thanks, the patches look good to me. I've also tested them on
The read delays were set incorrectly, leading to reliability
issues at higher DRAM clock speeds. This commit adjusts this
to match the vendor boot0 behaviour.
Signed-off-by: Jens Kuske
Tested-by: Siarhei Siamashka
---
arch/arm/cpu/armv7/sunxi/dram_sun8i_h3.c | 12 ++--
1 file changed
On 16/11/15 07:26, Chen-Yu Tsai wrote:
> Hi everyone,
>
> I got my Orange Pi PC booting U-boot now, using Hans' sunxi-wip branch that
> includes Jens' patches.
>
> For PSCI and SMP, it seems the H3 follows the structure of previous sun8i
> SoCs.
> The CPUCFG registers line up. The manual doesn't
Add initial sun8i H3 support, only uart + mmc are supported for now.
Signed-off-by: Jens Kuske
---
arch/arm/cpu/armv7/sunxi/board.c | 4
arch/arm/cpu/armv7/sunxi/cpu_info.c| 2 ++
arch/arm/include/asm/arch-sunxi/gpio.h | 1 +
board/sunxi/Kconfig| 7
Based on existing A23/A33 code and the original H3 boot0.
Signed-off-by: Jens Kuske
---
arch/arm/cpu/armv7/sunxi/Makefile | 1 +
arch/arm/cpu/armv7/sunxi/dram_sun8i_h3.c| 469
arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 3 +
arch/arm
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