On Thu, Aug 20, 2020 at 1:25 PM Heinrich Schuchardt wrote:
>
> No need to check tmp is non-zero twice.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> lib/rsa/rsa-sign.c | 4
> 1 file changed, 4 deletions(-)
>
> diff --git a/lib/rsa/rsa-sign.c b/lib/rsa/rsa-sign.c
> index 40ca1e1f57..18b68e1
ame hint. These two string
> identifiers are not necessarily equal.
>
> Signed-off-by: Jan Luebbe
> Signed-off-by: Bastian Krause
Looks good to me.
Reviewed-by: George McCollister
> ---
> Note: we could also check if keydir starts with "pkcs11:" and append
> &q
I don't have time to test the generic coreboot support on this board
right now but sounds fine to me.
Thanks,
George McCollister
On Fri, Aug 10, 2018 at 4:39 AM, Bin Meng wrote:
> Now that we have generic coreboot payload support, remove the
> dedicated support for Advante
With Python 3.5.2 encode will throw an exception if val is a byte array.
Decode it to a string first. This assumes it's utf-8, if it's not valid
utf-8 it will throw an exception.
Signed-off-by: George McCollister
---
tools/dtoc/fdt_util.py | 2 ++
1 file changed, 2 insertions(+)
di
check data == "" would fail when data
was b'' and would cause an infinite memory leaking loop. joins would
also fail with an exception below but due to the infinite loop it never
made it that far.
Signed-off-by: George McCollister
---
tools/patman/cros_subprocess.py | 4 +++
for
these parts.
Signed-off-by: George McCollister
---
lib/rsa/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/lib/rsa/Kconfig b/lib/rsa/Kconfig
index 09ec358242..fde1ac108d 100644
--- a/lib/rsa/Kconfig
+++ b/lib/rsa/Kconfig
@@ -1,6 +1,6 @@
config RSA
rsa_engine_get_priv_key() to construct
correct key_id strings.
Signed-off-by: George McCollister
---
doc/uImage.FIT/signature.txt | 143 +
include/image.h | 5 +-
lib/rsa/rsa-sign.c | 244 +--
tools/fit_image.c| 3
| 4 +++-
> 6 files changed, 17 insertions(+), 5 deletions(-)
>
Reviewed-by: George McCollister
Tested-by: George McCollister
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On Sun, Nov 6, 2016 at 9:37 AM, Sven Ebenfeld wrote:
> Cc: sba...@denx.de
>
> Signed-off-by: Sven Ebenfeld
> ---
> doc/README.imx6 | 48
> 1 file changed, 48 insertions(+)
>
Reviewed-b
ff-by: Sven Ebenfeld
> ---
> Makefile | 9 -
> common/image.c| 6 ++
> include/image.h | 1 +
> tools/default_image.c | 10 --
> tools/mkimage.c | 32
> 5 files changed, 55 insertions(+),
fg| 10 +++
> arch/arm/include/asm/imx-common/hab.h | 2 +
> include/configs/mx6_common.h | 3 +
> 5 files changed, 110 insertions(+), 59 deletions(-)
>
Reviewed-by: George McCollister
Tested-by: George McCollister
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ad to linker failures. e.g. "armv5te-ld.bfd: cannot find
> arch/arm/imx-common/built-in.o: No such file or directory)"
>
> Signed-off-by: Sven Ebenfeld
> ---
> arch/arm/Makefile| 2 +-
> arch/arm/imx-common/Makefile | 2 ++
> 2 files changed, 3 inserti
On Mon, Oct 10, 2016 at 1:57 PM, George McCollister
wrote:
> Many SPI NOR flash devices support status register protection through
> one or two status register protection bits. Protection of the status
> register is essential in defending the device from rogue software which
> ma
The Atmel AT97SC3204 is also TIS compliant.
Modify the tpm_tis_lpc driver to check for the vid/did used by the
Atmel AT97SC3204 and report an appropriate description.
Signed-off-by: George McCollister
---
Changes in v2:
- Reorganized didvid check to make it more consistent with the original
The Atmel AT97SC3204 is also TIS compliant.
Modify the tpm_tis_lpc driver to check for the vid/did used by the
Atmel AT97SC3204 and report an appropriate description.
Signed-off-by: George McCollister
---
drivers/tpm/tpm_tis_lpc.c | 37 -
1 file changed, 28
Add an sf sub-command named sr-protect which allows the status register
protection method to be changed.
Valid settings are software, hardware, power and otp.
Signed-off-by: George McCollister
---
cmd/sf.c | 28
1 file changed, 28 insertions(+)
diff --git a/cmd
|
---
Not all devices support OTP.
Signed-off-by: George McCollister
---
drivers/mtd/spi/sf_internal.h | 1 +
drivers/mtd/spi/spi_flash.c | 57 +++
2 files changed, 58 insertions(+)
diff --git a/drivers/mtd/spi/sf_internal.h b
until
the next power-down.
One Time Program - Writes to the status register are permanently
blocked.
Signed-off-by: George McCollister
---
include/spi_flash.h | 17 +
1 file changed, 17 insertions(+)
diff --git a/include/spi_flash.h b
STMICRO parts such as M25PX64 and SST parts such as SST26VF032B support
a single status register protect bit. When set this bit cause writes to
the status register to be blocked when the write protect signal is low.
Implement sr_protect for these devices.
Signed-off-by: George McCollister
the data stored in flash. This patch series adds
status register protect support for STMICRO, SST, Winbond and Spansion
devices and also implements an sf sub-command to set the used
protection method.
George McCollister (5):
sf: Add status register protection mechanism
sf: Add status register
Spansion parts such as S25FL128S and Winbond parts such as W25Q64FV
support the block protection mechanism implemented as
stm_lock() and stm_unlock(). Use stm_lock() and stm_unlock() for
Spansion and Winbond devices.
Signed-off-by: George McCollister
---
drivers/mtd/spi/spi_flash.c | 11
On Thu, Oct 6, 2016 at 11:55 AM, Jagan Teki wrote:
> On Thu, Oct 6, 2016 at 9:21 PM, George McCollister
> wrote:
>> On Thu, Oct 6, 2016 at 10:27 AM, Jagan Teki wrote:
>>> On Thu, Oct 6, 2016 at 8:32 PM, George McCollister
>>> wrote:
>>>> I'm loo
On Thu, Oct 6, 2016 at 10:27 AM, Jagan Teki wrote:
> On Thu, Oct 6, 2016 at 8:32 PM, George McCollister
> wrote:
>> I'm looking into adding a sub-command to sf to protect status
>> registers on Winbond SPI flash parts via the status register protect
>> bits SRP0, SR
iver model?
Is anyone aware of any vendors other than Winbond that use this SRP
mechanism or should only SPI_FLASH_CFI_MFR_WINBOND parts use it?
For details see "7.1.7 Status Register Protect Bit (SRP1, SRP0)" on
page 15 of http://www.winbond.com/resource-files/w25q64cv_r
t ought to have been checking for
>>> -ENOLINK prior to bac17b78dace ("image-fit: switch ENOLINK to ENOENT")
>>> anyway, which would make it right after this patch, but this would be
>>> good to get verified by someone who knows this x86 code or is able to
>
On Tue, Jun 28, 2016 at 8:44 AM, Stefan Roese wrote:
> This patch adds support for the SMBus block read/write functionality.
> Other protocols like the SMBus quick command need to get added
> if this is needed.
>
> This patch also removed the SMBus related defines from the Ivybridge
> pch.h header
development board all lead to the SERIRQ function being
disabled (address 0xfed0c560 with value of 0x2003cc80).
Signed-off-by: George McCollister
Reviewed-by: Bin Meng
---
Changes in v2:
- Reword commit message
arch/x86/dts/baytrail_som-db5800-som-6867.dts | 6 ++
1 file changed, 6 insertions
On Thu, Jul 28, 2016 at 1:36 AM, Bin Meng wrote:
> On Thu, Jul 28, 2016 at 6:01 AM, George McCollister
> wrote:
>> Pad configuration for SERIRQ is not set to enable the SERIRQ function
>> on soft reset though strangely, it is on initial boot.
>>
>
> What does &q
Pad configuration for SERIRQ is not set to enable the SERIRQ function
on soft reset though strangely, it is on initial boot.
Signed-off-by: George McCollister
---
arch/x86/dts/baytrail_som-db5800-som-6867.dts | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/x86/dts/baytrail_som
:
- Winbond Super I/O (Must be disabled with jumpers on SOM-DB8500)
- USB 3.0 (XHCI)
- TPM
Signed-off-by: George McCollister
Reviewed-by: Simon Glass
---
Changes in v2:
- Disable sdio, sdcard, emmc45-ddr50 in FSP DT
- Remove defines CONFIG_MMC, CONFIG_SDHCI, CONFIG_GENERIC_MMC
CONFIG_MMC_SDMA
On Thu, Jun 16, 2016 at 10:10 PM, Bin Meng wrote:
> Hi George,
>
> On Wed, Jun 15, 2016 at 10:51 PM, George McCollister
> wrote:
>> Add support for Advantech SOM-DB5800 with the SOM-6867 installed.
>> This is very similar to conga-qeval20-qa3-e3845 in that there is a
&g
On Fri, Jun 17, 2016 at 12:05 AM, Bin Meng wrote:
> Hi George,
>
> On Wed, Jun 15, 2016 at 1:12 AM, George McCollister
> wrote:
>> On Mon, Jun 13, 2016 at 9:09 PM, Bin Meng wrote:
>>> Hi George,
>>>
>>> On Mon, Jun 13, 2016 at 9:09 PM, George McColli
:
- Winbond Super I/O (Must be disabled with jumpers on SOM-DB8500)
- USB 3.0 (XHCI)
- TPM
Signed-off-by: George McCollister
---
arch/x86/Kconfig | 4 +
arch/x86/dts/Makefile | 3 +-
arch/x86/dts/baytrail_som-db5800-som-6867.dts
On Wed, Jun 15, 2016 at 9:09 AM, Bin Meng wrote:
> Hi George,
>
> On Wed, Jun 15, 2016 at 9:57 PM, George McCollister
> wrote:
>> On Wed, Jun 15, 2016 at 3:33 AM, Bin Meng wrote:
>>> If global NVS says internal UART is not enabled, hide it in the ASL
>&
t; 1 file changed, 8 insertions(+), 11 deletions(-)
Reviewed-by: George McCollister
Tested-by: George McCollister
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changed, 31 insertions(+), 2 deletions(-)
Reviewed-by: George McCollister
Tested-by: George McCollister
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e mode 100644 arch/x86/include/asm/arch-baytrail/global_nvs.h
Reviewed-by: George McCollister
Tested-by: George McCollister
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On Mon, Jun 13, 2016 at 8:55 PM, Bin Meng wrote:
> Hi George,
>
> On Sun, Jun 12, 2016 at 5:26 PM, Bin Meng wrote:
>> On Sun, Jun 12, 2016 at 4:43 PM, Bin Meng wrote:
>>> Hi,
>>>
>>> My testing shows that only pin_usb_host_en1 is needed to turn on the
>>> power on the USB3 port. The USB2 port po
On Mon, Jun 13, 2016 at 9:09 PM, Bin Meng wrote:
> Hi George,
>
> On Mon, Jun 13, 2016 at 9:09 PM, George McCollister
> wrote:
>> On Fri, Jun 10, 2016 at 7:17 PM, Bin Meng wrote:
>>> Hi George,
>>>
>>> On Fri, Jun 10, 2016 at 4:57 AM, George McCollis
On Mon, Jun 13, 2016 at 8:45 PM, Bin Meng wrote:
> Hi George,
>
> On Tue, Jun 14, 2016 at 12:12 AM, George McCollister
> wrote:
>> On Fri, Jun 10, 2016 at 7:25 PM, Bin Meng wrote:
>>> Hi George,
>>>
>>> +Simon, Stefan
>>>
>>>
On Fri, Jun 10, 2016 at 7:25 PM, Bin Meng wrote:
> Hi George,
>
> +Simon, Stefan
>
> On Fri, Jun 10, 2016 at 1:17 AM, George McCollister
> wrote:
>> Does anyone have any ideas on how we might go about disabling
>> functions defined in arch/x86/include/asm/arch-
On Fri, Jun 10, 2016 at 7:17 PM, Bin Meng wrote:
> Hi George,
>
> On Fri, Jun 10, 2016 at 4:57 AM, George McCollister
> wrote:
>> I'm looking for feedback on this mock-up of fsp,azalia-config DT
>> before I proceed to writing code. I included everything in fsp for
gt; Move the call to syscon_get_by_driver_data() from ich6_gpio driver
> to cpu_init_r().
>
> Signed-off-by: Bin Meng
Reviewed-by: George McCollister
Tested-by: George McCollister
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On Fri, Jun 10, 2016 at 8:29 AM, vinoth eswaran wrote:
> On Fri, Jun 10, 2016 at 2:53 PM, George McCollister
> wrote:
>> On Thu, Jun 9, 2016 at 11:01 PM, Bin Meng wrote:
>>> Hi,
>>>
>>> +Simon, ML and Stefan.
>>>
>>> On Wed, Jun 8, 201
On Thu, Jun 9, 2016 at 11:01 PM, Bin Meng wrote:
> Hi,
>
> +Simon, ML and Stefan.
>
> On Wed, Jun 8, 2016 at 11:58 PM, vinoth eswaran wrote:
>> Hello Bin,
>>
>> Sorry that I don't know how not to reply without top-posting. I
>> don't know which settings to change, google didn't help me in this
fsp,dimm-trpt-rcd = <0xb>;
fsp,dimm-twr = <0xc>;
fsp,dimm-twtr = <6>;
fsp,dimm-trrd = <6>;
fsp,dimm-trtp = <6>;
fsp,dimm-tfaw = <0x14>;
};
};
Thanks,
George McCollister
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board .dts if the board uses them. I need to
disable the internal UART definition for the baytrail board I'm adding
since if it's included the off chip UART gets killed when Linux does
it's acpi_bus_scan.
Regards,
George McCollister
___
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An accumulated length was incorrectly added to current each pass
through the loop. On system with more than 2 cores this caused a
corrupt MADT to be generated.
Signed-off-by: George McCollister
---
arch/x86/lib/acpi_table.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions
I was having this problem on the Minnowboard Max with the defconfig
and this fixes it.
Tested-by: George McCollister
Thanks,
George
On Wed, Jun 1, 2016 at 8:11 AM, Ed Swarthout wrote:
> Fixes:
>
> => ext2ls scsi 0:1
> ** Bad device scsi 0:1 **
>
> for boards which use t
when it drops CAR."
Is it safe to move Azalia verb tables into DT for Baytrail FSP?
Regards,
George McCollister
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is isn't a concern at the moment. USB doesn't work since the
xHCI driver appears to be broken.
Signed-off-by: George McCollister
Reviewed-by: Bin Meng
Reviewed-by: Tom Rini
Acked-by: Simon Glass
---
Changes for V2:
Changed pci's compatible string to "pci-x86"
Changed
is isn't a concern at the moment. USB doesn't work since the
xHCI driver appears to be broken.
Signed-off-by: George McCollister
Reviewed-by: Bin Meng
Acked-by: Simon Glass
---
Changes for V2:
Changed pci's compatible string to "pci-x86"
Changed I/O from base of 0x1000 t
is isn't a concern at the moment. USB doesn't work since the
xHCI driver appears to be broken.
Signed-off-by: George McCollister
---
Changes for V2:
Changed pci's compatible string to "pci-x86"
Changed I/O from base of 0x1000 to base of 0x1900
Changed spi-flash memory-ma
On Mon, Oct 19, 2015 at 9:02 PM, Bin Meng wrote:
> Hi George,
>
> On Tue, Oct 20, 2015 at 1:46 AM, George McCollister
> wrote:
>> Advantech SOM-6896 is a Broadwell U based COM Express Compact Module
>> Type 6. This patch adds support for it as a coreboot payload.
>>
is isn't a concern at the moment. USB doesn't work since the
xHCI driver appears to be broken.
Signed-off-by: George McCollister
---
Changes for V2:
Changed pci's compatible string to "pci-x86"
Changed I/O from base of 0x1000 to base of 0x1900
Changed spi-flash memory-ma
Simon,
On Thu, Oct 15, 2015 at 8:25 AM, Simon Glass wrote:
> Hi Bin,
>
> On Monday, 12 October 2015, Bin Meng wrote:
>>
>> Hi George,
>>
>> On Tue, Oct 13, 2015 at 10:52 AM, George McCollister
>> wrote:
>> > On Mon, Oct 12, 2015 at 7:48 PM, Bin
On Mon, Oct 12, 2015 at 7:48 PM, Bin Meng wrote:
> Hi George,
>
> On Tue, Oct 13, 2015 at 2:30 AM, George McCollister
> wrote:
>> On Mon, Oct 12, 2015 at 8:34 AM, George McCollister
>> wrote:
>>> On Fri, Oct 9, 2015 at 10:31 PM, Bin Meng wrote:
>>>>
is isn't a concern at the moment. USB doesn't work since the
xHCI driver appears to be broken.
Signed-off-by: George McCollister
---
Changes for V2:
Changed pci's compatible string to "pci-x86"
Changed I/O from base of 0x1000 to base of 0x1900
Changed spi-flash memory-ma
Add the Wildcat Point ID so Broadwell U based boards can use SPI.
Signed-off-by: George McCollister
Reviewed-by: Bin Meng
---
Changes for V2:
Add Reviewed-by: Bin Meng
drivers/spi/ich.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/ich.c b/drivers/spi
Add Wildcat Point AHCI and LPC PCI IDs which are present on Broadwell U
based (and possibly other) boards.
Signed-off-by: George McCollister
Reviewed-by: Bin Meng
---
Changes for V2:
Add simple sentence as the commit message
Add Reviewed-by: Bin Meng
include/pci_ids.h | 2 ++
1 file changed
On Mon, Oct 12, 2015 at 8:34 AM, George McCollister
wrote:
> On Fri, Oct 9, 2015 at 10:31 PM, Bin Meng wrote:
>> Hi George,
>>
>> On Sat, Oct 10, 2015 at 5:54 AM, George McCollister
>> wrote:
>>> Advantech SOM-6896 is a Broadwell U based COM Express Compac
On Fri, Oct 9, 2015 at 10:31 PM, Bin Meng wrote:
> Hi George,
>
> On Sat, Oct 10, 2015 at 5:54 AM, George McCollister
> wrote:
>> Advantech SOM-6896 is a Broadwell U based COM Express Compact Module
>> Type 6. This patch adds support for it as a coreboot payload.
>>
Add the Wildcat Point ID so Broadwell U based boards can use SPI.
Signed-off-by: George McCollister
---
drivers/spi/ich.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index 2e388e7..be4c0a3 100644
--- a/drivers/spi/ich.c
+++ b
is isn't a concern at the moment. USB doesn't work since the
xHCI driver appears to be broken.
Signed-off-by: George McCollister
---
arch/x86/dts/Makefile | 3 ++-
arch/x86/dts/som-6896.dts | 43 +++
include/con
Signed-off-by: George McCollister
---
include/pci_ids.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/pci_ids.h b/include/pci_ids.h
index 49f7d7d..17a01a0 100644
--- a/include/pci_ids.h
+++ b/include/pci_ids.h
@@ -3022,6 +3022,8 @@
#define PCI_DEVICE_ID_INTEL_IXP28000x9004
On Thu, Oct 8, 2015 at 12:43 PM, Simon Glass wrote:
> Hi George,
>
> On 7 October 2015 at 16:29, George McCollister
> wrote:
>> Instead of having x86-pinctrl work separately from ich6-gpio have it
>> work underneath ich6-gpio. This removes redundant configuration and wi
Instead of having x86-pinctrl work separately from ich6-gpio have it
work underneath ich6-gpio. This removes redundant configuration and will
allow the addition of shared bank settings in future commits.
Signed-off-by: George McCollister
---
arch/x86/dts/minnowmax.dts
Max was unusable
since USB_HOST_EN0 was set high then immediately set low when
USB_HOST_EN1 was written.
Signed-off-by: George McCollister
---
arch/x86/dts/minnowmax.dts| 6 ++
doc/device-tree-bindings/gpio/intel,ich6-gpio.txt | 5 +
drivers/gpio
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