Re: [PATCH] spi: dw: Fix broken dw_spi_mem_ops()

opcode) + op->addr.nbytes + op->dummy.nbytes; > + u8 op_len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes; > u8 op_buf[op_len]; > u32 cr0; > Tested-by: Damien Le Moal -- Damien Le Moal Western Digital Research

Re: [PATCH 1/4] clk: k210: Fix checking if ulongs are less than 0

long rate_in) I would assume that these functions are called if the rate_in argument is correct, so I do not really understand why the argument type needs to be changed... > { > u64 r, f, od; > u32 reg = readl(priv->base + k210_plls[id].off); > -- Damien Le Moal Western Digital Research

Re: [PATCH v3 00/11] clk: k210: Rewrite K210 clock without CCF

ryte/pll.c | 585 -- >>> drivers/clk/rockchip/clk_rk3308.c |2 +- >>> drivers/core/device.c |2 +- >>> drivers/net/gmac_rockchip.c |2 +- >>> include/clk.h | 30 +- >>> include/dt-bindings/clock/k210-sysctl.h | 94 +- >>> include/kendryte/bypass.h | 31 - >>> include/kendryte/clk.h | 35 - >>> include/kendryte/pll.h | 34 - >>> 24 files changed, 1437 insertions(+), 1711 deletions(-) >>> create mode 100644 drivers/clk/clk_kendryte.c >>> delete mode 100644 drivers/clk/kendryte/Kconfig >>> delete mode 100644 drivers/clk/kendryte/Makefile >>> delete mode 100644 drivers/clk/kendryte/bypass.c >>> delete mode 100644 drivers/clk/kendryte/clk.c >>> delete mode 100644 drivers/clk/kendryte/pll.c >>> delete mode 100644 include/kendryte/bypass.h >>> delete mode 100644 include/kendryte/clk.h >>> >> >> >> >> Best regards, >> >> Lukasz Majewski >> >> -- >> >> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk >> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany >> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de >> > > -- Damien Le Moal Western Digital Research

Re: [PATCH v2 00/11] clk: k210: Rewrite K210 clock without CCF

t_flat: allow not offsetting data start"). Not sure what is going on yet. 5.13-rc4 kernel works perfectly. > create mode 100644 drivers/clk/clk_kendryte.c > delete mode 100644 drivers/clk/kendryte/Kconfig > delete mode 100644 drivers/clk/kendryte/Makefile > delete mode 100644 drivers/clk/kendryte/bypass.c > delete mode 100644 drivers/clk/kendryte/clk.c > delete mode 100644 drivers/clk/kendryte/pll.c > delete mode 100644 include/kendryte/bypass.h > delete mode 100644 include/kendryte/clk.h > -- Damien Le Moal Western Digital Research

Re: [PATCH v3 05/11] clk: k210: Move the clint clock to under aclk

On 2021/04/09 11:58, Sean Anderson wrote: > > On 4/8/21 10:54 PM, Damien Le Moal wrote: >> On 2021/04/09 11:13, Sean Anderson wrote: >>> No other (real) clocks have the cpu clock as their parent; instead they are >>> children of aclk. Move the clint clock under aclk

Re: [PATCH v3 05/11] clk: k210: Move the clint clock to under aclk

On 2021/04/09 11:54, Damien Le Moal wrote: > On 2021/04/09 11:13, Sean Anderson wrote: >> No other (real) clocks have the cpu clock as their parent; instead they are >> children of aclk. Move the clint clock under aclk to match them. >> >> Signed-off-by: Sean Anderso

Re: [PATCH v3 05/11] clk: k210: Move the clint clock to under aclk

scv_timebase which is set from the timebase-frequency DT property. Not sure how u-boot handles that though. Since your code allows changing the PLLs frequency, the timebase-frequency property may end up being buggy if it is not changed too. -- Damien Le Moal Western Digital Research

Re: [PATCH v3 02/11] clk: k210: Fix PLLs not being enabled

int k210_pll_disable(struct clk *clk) > writel(reg, pll->reg); > > reg &= ~K210_PLL_PWRD; > + reg &= ~K210_PLL_EN; > writel(reg, pll->reg); > return 0; > } > Looks good. That matches what the linux driver is doing. Reviewed-by: Damien Le Moal -- Damien Le Moal Western Digital Research

Re: [PATCH v2 06/10] spi: dw: Rewrite poll_transfer logic

mut_op->data.nbytes = poll_transfer(priv, op->data.buf.out, > + NULL, op->data.nbytes); > > - dw_write(priv, DW_SPI_SER, 1 << spi_chip_select(slave->dev)); > - while (priv->rx != priv->rx_end) > - dw_reader(priv); > - } else { > - u32 val; > - > - priv->tx = op->data.buf.out; > - priv->tx_end = priv->tx + op->data.nbytes; > - > - /* Fill up the write fifo before starting the transfer */ > - dw_writer(priv); > - dw_write(priv, DW_SPI_SER, 1 << spi_chip_select(slave->dev)); > - while (priv->tx != priv->tx_end) > - dw_writer(priv); > - > - if (readl_poll_timeout(priv->regs + DW_SPI_SR, val, > -(val & SR_TF_EMPT) && !(val & SR_BUSY), > -RX_TIMEOUT * 1000)) { > - dev_dbg(bus, "timed out; sr=%x\n", > - dw_read(priv, DW_SPI_SR)); > - ret = -ETIMEDOUT; > - } > + /* > + * Ensure the data (or the instruction for zero-data instructions) has > + * been transmitted from the fifo/shift register before disabling the > + * device. > + */ > + if (readl_poll_timeout(priv->regs + DW_SPI_SR, val, > +(val & SR_TF_EMPT) && !(val & SR_BUSY), > +RX_TIMEOUT * 1000)) { > + dev_dbg(bus, "timed out; sr=%x\n", dw_read(priv, DW_SPI_SR)); > + ret = -ETIMEDOUT; > } > - > dw_write(priv, DW_SPI_SER, 0); > external_cs_manage(slave->dev, true); > > -- Damien Le Moal Western Digital Research