-Original Message-
From: Marek Vasut
Sent: Tuesday, March 26, 2024 1:08 PM
To:u-boot@lists.denx.de
Cc: Marek Vasut; Christophe ROULLIER; Joe
Hershberger; Patrice CHOTARD - foss; Patrick
DELAUNAY - foss; Ramon
Fried;u-b...@dh-electronics.com;uboot-st...@st-md-mailman.stormreply.com
-Original Message-
From: Marek Vasut
Sent: Tuesday, March 26, 2024 1:08 PM
To:u-boot@lists.denx.de
Cc: Christophe ROULLIER; Patrice CHOTARD -
foss; Marek Vasut; Joe
Hershberger; Patrick DELAUNAY - foss; Ramon
Fried;u-b...@dh-electronics.com;uboot-st...@st-md-mailman.stormreply.com
-Original Message-
From: Marek Vasut
Sent: Tuesday, March 26, 2024 1:08 PM
To:u-boot@lists.denx.de
Cc: Christophe ROULLIER; Marek Vasut; Joe
Hershberger; Patrice CHOTARD - foss; Patrick
DELAUNAY - foss; Ramon
Fried;u-b...@dh-electronics.com;uboot-st...@st-md-mailman.stormreply.com
-Original Message-
From: Marek Vasut
Sent: Tuesday, March 26, 2024 1:07 PM
To: u-boot@lists.denx.de
Cc: Marek Vasut ; Patrice CHOTARD - foss ; Christophe
ROULLIER ; Joe Hershberger ; Patrick DELAUNAY -
foss ; Ramon Fried ; u-b...@dh-electronics.com;
uboot-st...@st-md
-Original Message-
From: Marek Vasut
Sent: Tuesday, March 26, 2024 1:07 PM
To:u-boot@lists.denx.de
Cc: Marek Vasut; Patrice CHOTARD - foss; Christophe
ROULLIER; Joe Hershberger; Patrick DELAUNAY -
foss; Ramon
Fried;u-b...@dh-electronics.com;uboot-st...@st-md-mailman.stormreply.com
-Original Message-
From: Marek Vasut
Sent: Tuesday, March 26, 2024 1:07 PM
To:u-boot@lists.denx.de
Cc: Marek Vasut; Patrice CHOTARD - foss; Christophe
ROULLIER; Joe Hershberger; Patrick DELAUNAY -
foss; Ramon
Fried;u-b...@dh-electronics.com;uboot-st...@st-md-mailman.stormreply.com
On 3/9/24 03:11, Marek Vasut wrote:
From: Christophe Roullier
Add compatible "st,stm32mp13-dwmac" to manage STM32MP13 boards.
Signed-off-by: Christophe Roullier
Signed-off-by: Marek Vasut # Rebase, reshuffle, squash
code
---
Cc: Christophe Roullier
Cc: Joe Hershberger
Cc: Patri
On 3/9/24 03:11, Marek Vasut wrote:
From: Christophe Roullier
Manage 2 ethernet instances, select which instance to configure with
mask If mask is not present in DT, it is stm32mp15 platform.
Signed-off-by: Christophe Roullier
Signed-off-by: Marek Vasut # Rework the code
---
Cc: Christophe
On 3/9/24 03:11, Marek Vasut wrote:
From: Patrick Delaunay
Request the clk-ck earlier in probe in preparation for obtaining the
clock rate from these clk-ck in eqos_probe_syscfg_stm32() in the
follow up patch.
Signed-off-by: Patrick Delaunay
---
Cc: Christophe Roullier
Cc: Joe Hershberger
On 3/9/24 03:11, Marek Vasut wrote:
Use const bool for the values parsed out of DT. Drop the duplicate
assignment of false into those bool variables, assign them directly
with the content parsed out of DT. Abbreviate the variable name too.
Signed-off-by: Marek Vasut
---
Cc: Christophe Roullier
On 3/9/24 03:11, Marek Vasut wrote:
Use dev_*() only to print all the logs from this glue code, instead of
mixing dev_*(), log_*(), pr_*() all in one code.
Signed-off-by: Marek Vasut
---
Cc: Christophe Roullier
Cc: Joe Hershberger
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: Ramon Fried
On 3/9/24 03:11, Marek Vasut wrote:
Move the log_debug() calls on top of the bit manipulation code.
No functional change.
Signed-off-by: Marek Vasut
---
Cc: Christophe Roullier
Cc: Joe Hershberger
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: Ramon Fried
Cc: u-b...@dh-electronics.com
Cc
On 3/9/24 03:11, Marek Vasut wrote:
Use FIELD_PREP to configure content of ETH_SEL bitfield in
SYSCFG_PMCSETR register. No functional change.
Signed-off-by: Marek Vasut
---
Cc: Christophe Roullier
Cc: Joe Hershberger
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: Ramon Fried
Cc: u-b...@dh
s disabled.
Signed-off-by: Marek Vasut
---
Cc: Christophe Roullier
Cc: Joe Hershberger
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: Ramon Fried
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
drivers/net/dwc_eth_qos_stm32.c | 25 -
1 fi
this
function, move it into generic driver code instead. Drop the now unused
duplicates from board files.
Signed-off-by: Marek Vasut
---
Cc: Christophe Roullier
Cc: Joe Hershberger
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: Ramon Fried
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md
this
function, move it into generic driver code instead. Drop the now unused
duplicates from board files.
Signed-off-by: Marek Vasut
---
Cc: Christophe Roullier
Cc: Joe Hershberger
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: Ramon Fried
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md
: Marek Vasut
---
Cc: Christophe Roullier
Cc: Joe Hershberger
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: Ramon Fried
Cc:u-b...@dh-electronics.com
Cc:uboot-st...@st-md-mailman.stormreply.com
---
drivers/net/dwc_eth_qos.c | 2 +-
drivers/net/dwc_eth_qos.h | 2 +-
drivers/net
On 1/14/20 3:36 PM, Marek Vasut wrote:
> On 1/14/20 8:20 AM, Christophe ROULLIER wrote:
>> On 1/13/20 6:30 PM, Marek Vasut wrote:
>>> On 1/13/20 5:14 PM, Christophe ROULLIER wrote:
>>> [...]
>>>>>> Christophe you can complete my answer if it is no
On 1/13/20 6:30 PM, Marek Vasut wrote:
> On 1/13/20 5:14 PM, Christophe ROULLIER wrote:
> [...]
>>>> Christophe you can complete my answer if it is not enough clear.
>>> I would expect that you should describe _all_ the clock which are routed
>>> into the eth
On 1/13/20 2:33 PM, Marek Vasut wrote:
> On 1/13/20 2:26 PM, Patrick DELAUNAY wrote:
>> Hi Marek,
> Hi,
>
>> + Christophe (Maintainer in kernel)
>>
>>> From: Marek Vasut
>>> Sent: vendredi 10 janvier 2020 01:29
>>>
>>> Add missing 'eth-ck' clock to the ethernet node. These clock are used to
>>>
Hi Ramon,
No need to write specific phy driver, uboot phy generic driver is working
fine.
The goal of board_interface_eth_init function is only to configure syscfg
register with good value in function of interface type (MII, RMII, GMII
...). And this syscfg value is specific for each platform. Af
This allows to enable Ethernet and use driver for
Synopsys Ethernet QoS device
Signed-off-by: Christophe Roullier
---
Changes in v2:
-remark from Joe Hershberger to replace "int interface" with "phy_interface_t
interface"
and manage return values "-1", "
Add default SERVERIP address
Enable noncached memory region required by ethernet driver
Add PXE support
Signed-off-by: Christophe Roullier
---
Changes in v2: None
include/configs/stm32mp1.h | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/include/configs
alues "-1", "0" with PHY_INTERFACE_MODE_NONE and
PHY_INTERFACE_MODE_MII
Christophe Roullier (5):
board: stm32mp1: Add board_interface_eth_init
net: dwc_eth_qos: add Ethernet stm32mp1 support
ARM: dts: stm32: Add Ethernet support on stm32mp1
stm32mp1: Add Ethernet support for stm
This patch add Ethernet support on stm32mp157 eval board
Signed-off-by: Christophe Roullier
---
Changes in v2: None
arch/arm/dts/stm32mp157-pinctrl.dtsi | 9 +++--
arch/arm/dts/stm32mp157c-ev1.dts | 2 +-
arch/arm/dts/stm32mp157c.dtsi| 16 ++--
3 files changed
Called to configure Ethernet PHY interface selection and
configure clock selection in RCC Ethernet clock tree.
Signed-off-by: Christophe Roullier
---
Changes in v2: None
board/st/stm32mp1/stm32mp1.c | 68 ++--
1 file changed, 65 insertions(+), 3 deletions
Synopsys GMAC 4.20 is used. And Phy mode for eval and disco is RMII
with PHY Realtek RTL8211 (RGMII)
We also support some other PHY config on stm32mp157c
PHY_MODE(MII,GMII, RMII, RGMII) and in normal,
PHY wo crystal (25Mhz and 50Mhz), No 125Mhz from PHY config
Signed-off-by: Christophe
From: Patrick Delaunay
ETHCK_K is the identifier the kernel clock for ETH in kernel
binding, selected by ETHKSELR / gated by ETHCKEN = BIT(7).
U-Boot driver need to use the same identifier, so change ETHCK
to ETHCK_K.
Signed-off-by: Patrick Delaunay
Signed-off-by: Christophe Roullier
Hi Joe,
On 09/05/2019 23:07, Joe Hershberger wrote:
> On Fri, Apr 26, 2019 at 6:16 AM Christophe Roullier
> wrote:
>> Synopsys GMAC 4.20 is used. And Phy mode for eval and disco is RMII
>> with PHY Realtek RTL8211 (RGMII)
>> We also support some other PHY config on
Add default SERVERIP address
Enable noncached memory region required by ethernet driver
Add PXE support
Signed-off-by: Christophe Roullier
---
include/configs/stm32mp1.h | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/include/configs/stm32mp1.h b/include/configs
Called to configure Ethernet PHY interface selection and
configure clock selection in RCC Ethernet clock tree.
Signed-off-by: Christophe Roullier
---
board/st/stm32mp1/stm32mp1.c | 77
1 file changed, 77 insertions(+)
diff --git a/board/st/stm32mp1
This allows to enable Ethernet and use driver for
Synopsys Ethernet QoS device
Signed-off-by: Christophe Roullier
---
configs/stm32mp15_basic_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configs/stm32mp15_basic_defconfig
b/configs/stm32mp15_basic_defconfig
index d20b2ab3508
Support all PHY config:
PHY_MODE (MII,GMII, RMII, RGMII)
Phy wo crystal (25Mhz and 50 Mhz), No 125Mhz from PHY config
Christophe Roullier (5):
board: stm32mp1: Add board_interface_eth_init
net: dwc_eth_qos: add Ethernet stm32mp1 support
ARM: dts: stm32: Add Ethernet support on
This patch add Ethernet support on stm32mp157 eval board
Signed-off-by: Christophe Roullier
---
arch/arm/dts/stm32mp157-pinctrl.dtsi | 31
arch/arm/dts/stm32mp157c-ev1.dts | 21 +
arch/arm/dts/stm32mp157c.dtsi| 35
Synopsys GMAC 4.20 is used. And Phy mode for eval and disco is RMII
with PHY Realtek RTL8211 (RGMII)
We also support some other PHY config on stm32mp157c
PHY_MODE(MII,GMII, RMII, RGMII) and in normal,
PHY wo crystal (25Mhz and 50Mhz), No 125Mhz from PHY config
Signed-off-by: Christophe
This patch add Ethernet support on stm32mp157 eval board
Signed-off-by: Christophe Roullier
---
arch/arm/dts/stm32mp157-pinctrl.dtsi | 31 +++
arch/arm/dts/stm32mp157c-ev1.dts | 21 +
arch/arm/dts/stm32mp157c.dtsi| 35
Add default SERVERIP address
Enable noncached memory region required by ethernet driver
Add PXE support
Signed-off-by: Christophe Roullier
---
include/configs/stm32mp1.h | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/include/configs/stm32mp1.h b/include/configs
From: Patrick Delaunay
ETHCK_K is the identifier the kernel clock for ETH in kernel
binding, selected by ETHKSELR / gated by ETHCKEN = BIT(7).
U-Boot driver need to use the same identifier, so change ETHCK
to ETHCK_K.
Signed-off-by: Patrick Delaunay
Signed-off-by: Christophe Roullier
Synopsys GMAC 4.20 is used. And Phy mode for eval and disco is RMII
with PHY Realtek RTL8211 (RGMII)
We also support some other PHY config on stm32mp157c
PHY_MODE(MII,GMII, RMII, RGMII) and in normal,
PHY wo crystal (25Mhz and 50Mhz), No 125Mhz from PHY config
Signed-off-by: Christophe
This allows to enable Ethernet and use driver for
Synopsys Ethernet QoS device
Signed-off-by: Christophe Roullier
---
configs/stm32mp15_basic_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configs/stm32mp15_basic_defconfig
b/configs/stm32mp15_basic_defconfig
index d20b2ab
Called to configure Ethernet PHY interface selection and
configure clock selection in RCC Ethernet clock tree.
Signed-off-by: Christophe Roullier
---
board/st/stm32mp1/stm32mp1.c | 77
1 file changed, 77 insertions(+)
diff --git a/board/st/stm32mp1
Support all PHY config:
PHY_MODE (MII,GMII, RMII, RGMII)
Phy wo crystal (25Mhz and 50 Mhz), No 125Mhz from PHY config
Christophe Roullier (5):
board: stm32mp1: Add board_interface_eth_init
net: dwc_eth_qos: add Ethernet stm32mp1 support
ARM: dts: stm32: Add Ethernet support on
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