> From: Tom Rini
> Sent: Saturday, October 12, 2024 1:34 AM
> To: ChiaWei Wang
>
> On Fri, Sep 27, 2024 at 11:07:22AM +0800, Chia-Wei Wang wrote:
>
> > Aspeed AST2700 SoCs integrates the Caliptra secure IP, where an
> > ECDSA384 signature verification HW interf
Hi Simon
> -Original Message-
> From: Simon Glass
> Sent: Saturday, September 21, 2024 12:02 AM
>
> On Mon, 2 Sept 2024 at 07:33, Chia-Wei Wang
> wrote:
> >
> > Both the signature and the public key are stored as DTS nodes in the
> > FIT image and SPL/U-Boot DTBs.
> >
> > Like the RSA s
Hi Simon,
> -Original Message-
> From: Simon Glass
> Sent: Saturday, September 21, 2024 12:02 AM
>
> On Mon, 2 Sept 2024 at 07:33, Chia-Wei Wang
> wrote:
> >
> > Aspeed AST27xx SoCs integrate the CPTRA 1.0 secure IP, which export an
> > ECDSA384_SIGNATURE_VERIFY mailbox command service
Hi Simon,
> -Original Message-
> From: Simon Glass
> Sent: Saturday, September 21, 2024 12:02 AM>
>
> Hi,
>
> On Mon, 2 Sept 2024 at 07:33, Chia-Wei Wang
> wrote:
> >
> > The padding algorithm is not mandatory for all signing algorithm.
> >
> > For example, ECDSA does not require a pad
> From: Leo Liang
> Sent: Monday, September 9, 2024 8:17 PM
> To: ChiaWei Wang
>
> On Mon, Aug 19, 2024 at 06:17:00PM +0800, Chia-Wei Wang wrote:
> > AST2700 SoCs integrates a Ibex 32-bits RISC-V core as the boot MCU for
> > the first stage bootloader execution, nam
r
> ; Maxim Sloyko ; Tom
> Rini ; ChiaWei Wang
> Subject: [PATCH v9 36/37] [TESTING] configs: set CONFIG_NET=y for
> FTGMAC100
>
> FTGMAC100 is not compatible with NET_LWIP which was enabled as the
> default stack in a previous commit. So enable NET in the defconfig.
>
> Si
> From: Tom Rini
> Sent: Tuesday, April 30, 2024 9:36 PM
>
> Remove from all mach-aspeed files and when needed add
> missing include files directly.
>
> Signed-off-by: Tom Rini
Reviewed-by: Chia-Wei Wang
Thanks,
Chiawei
> From: SSunk
> Sent: Saturday, August 12, 2023 11:08 AM
>
> Add XMC
> XM25QH128C/XM25QH256C/XM25QU256C/XM25QH512C/XM25QU512C
> site: https://www.xmcwh.com/site/product
>
> Signed-off-by: Kankan Sun
Reviewed-by: Chia-Wei Wang
Reviewed-by: Chia-Wei Wang
Thanks.
> From: Ryan Chen
> Sent: Friday, February 10, 2023 3:42 PM
>
> Enable defconfigs relevant for storing env on SPI flash.
>
> Signed-off-by: Ryan Chen
> ---
> configs/evb-ast2600_defconfig | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/config
Reviewed-by: Chia-Wei Wang
Thanks.
> From: Simon Glass
> Sent: Monday, January 30, 2023 10:42 PM
>
> This converts 2 usages of this option to the non-SPL form, since there is no
> SPL_HW_WATCHDOG defined in Kconfig
>
> Signed-off-by: Simon Glass
> ---
>
> drivers/crypto/aspeed/aspeed_hace.
Acked-by: Chia-Wei Wang
> From: Dhananjay Phadke
> Sent: Wednesday, August 3, 2022 4:55 AM
>
> Ported as is, makes it easier to add readable GPIO definitions in DTS files.
>
> Signed-off-by: Dhananjay Phadke
> ---
> include/dt-bindings/gpio/aspeed-gpio.h | 49 ++
> 1
Hi Sean,
> From: Sean Anderson
> Sent: Tuesday, June 28, 2022 12:57 PM
>
> Hi Chai,
>
> On 6/28/22 12:23 AM, Joel Stanley wrote:
> > Hi Chai Wei,
> >
> > On Wed, 1 Jun 2022 at 08:21, Chia-Wei Wang
> wrote:
> >>
> >> The commit b583348ca8c8 ("image: fit: Align hash output buffers")
> >> places
Hi Joel,
> From: Joel Stanley
> Sent: Tuesday, June 28, 2022 12:24 PM
>
> Hi Chai Wei,
>
> On Wed, 1 Jun 2022 at 08:21, Chia-Wei Wang
> wrote:
> >
> > The commit b583348ca8c8 ("image: fit: Align hash output buffers")
> > places the hash output buffer at the .bss section. However, AST2600 by
>
Reviewed-by: Chia-Wei Wang
> From: joel.s...@gmail.com On Behalf Of Joel Stanley
> Sent: Monday, June 27, 2022 3:58 PM
>
> The AST2600 has a Qemu model that allows testing. Create a SPI NOR image
> containing the combined SPL and u-boot FIT image.
>
> Signed-off-by: Joel Stanley
> ---
> .azu
> From: joel.s...@gmail.com On Behalf Of Joel Stanley
> Sent: Monday, June 27, 2022 3:58 PM
>
> For the u-boot-with-spl.bin target to be useful for the AST2600, set the
> maximum SPL size which also sets the padding length.
>
> The normal way of loading u-boot is as a FIT, so configure u-boot.im
Reviewed-by: Chia-Wei Wang
> From: joel.s...@gmail.com On Behalf Of Joel Stanley
> Sent: Monday, June 27, 2022 3:58 PM
>
> Useful for testing images with the default hash type.
>
> Signed-off-by: Joel Stanley
> ---
> configs/evb-ast2600_defconfig | 1 +
> 1 file changed, 1 insertion(+)
>
>
Reviewed-by: Chia-Wei Wang
The QEMU emulation issue is under investigation by Steven.
The CRC32 and MD5 SW support will be added before we re-enabling HW crypto
drivers.
Chiawei
> From: joel.s...@gmail.com On Behalf Of Joel Stanley
> Sent: Monday, June 27, 2022 3:58 PM
>
> The HACE driver la
Reviewed-by: Chia-Wei Wang
> From: joel.s...@gmail.com On Behalf Of Joel Stanley
> Sent: Monday, June 27, 2022 3:58 PM
>
> Allows loading one u-boot from another. Useful for testing on hardware.
>
> Signed-off-by: Joel Stanley
> ---
> configs/evb-ast2600_defconfig | 1 +
> 1 file changed, 1
Reply again to leave record on mailing list.
> From: joel.s...@gmail.com On Behalf Of Joel Stanley
> Sent: Friday, June 24, 2022 10:50 AM
>
> For the u-boot-with-spl.bin target to be useful for the AST2600, set the
> maximum SPL size which also sets the padding length.
>
> The normal way of loa
Reply again to leave record on mailing list.
> From: joel.s...@gmail.com On Behalf Of Joel Stanley
> Sent: Friday, June 24, 2022 10:50 AM
>
> The Qemu model or the u-boot driver is unable to correctly compute the
> SHA256 hash used in a FIT. Disable it by default while that issue is worked
> ou
Tested-by: Chia-Wei Wang
Thanks for the fix.
Driven by the same issue, We also sent another patch moving .BSS section into
DRAM.
You may also check it out and any feedback is appreciated.
https://patchwork.ozlabs.org/project/uboot/patch/20220601082115.10799-1-chiawei_w...@aspeedtech.com/
Chiaw
Reviewed-by: Chia-Wei Wang
> -Original Message-
> From: joel.s...@gmail.com On Behalf Of Joel Stanley
> Sent: Thursday, May 19, 2022 8:37 AM
> To: u-boot@lists.denx.de; Ryan Chen ; ChiaWei
> Wang
> Subject: [PATCH] MAINTAINERS: aspeed: Add more files and myself as a
&
> From: Billy Tsai
> Sent: Friday, April 29, 2022 11:51 AM
>
> To work correctly, this driver depends on SYSCON to get the base address from
> the parent dts node.
>
> Signed-off-by: Billy Tsai
> ---
> drivers/pwm/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/pwm/Kc
> From: Simon Glass
> Sent: Saturday, March 12, 2022 10:44 AM
>
> On Mon, 7 Mar 2022 at 20:02, Billy Tsai wrote:
> >
> > Add the PWM node and enable it for AST2600 EVB
> >
> > Signed-off-by: Billy Tsai
> > ---
> > arch/arm/dts/ast2600-evb.dts | 20
> > arch/arm/dts/ast2600
> From: Simon Glass
> Sent: Saturday, March 12, 2022 10:44 AM
>
> On Mon, 7 Mar 2022 at 20:02, Billy Tsai wrote:
> >
> > This patchs add the signal description array for PWM pinctrl settings.
> >
> > Signed-off-by: Billy Tsai
> > ---
> > arch/arm/dts/ast2600.dtsi| 80 +
> From: Simon Glass
> Sent: Saturday, March 12, 2022 10:44 AM
>
> On Mon, 7 Mar 2022 at 20:02, Billy Tsai wrote:
> >
> > This patch add the support of PWM controller which can be found at
> > aspeed
> > ast2600 soc. The pwm supoorts up to 16 channels and it's part function
> > of multi-function
> From: Neal Liu
> Sent: Tuesday, February 15, 2022 4:55 PM
>
> Check interrupt status to see if RSA engine is completed. After completion of
> the task, write-clear the status to finish operation.
> Add missing register base for completion.
>
> Signed-off-by: Neal Liu
Please add a line with "
Hi Andrew,
I am curious about the usage scenario.
Is the runtime control required for production release?
As this control acts like a backdoor to bypass the chain-of-trust.
If it is for debugging/development purposes, should we encourage the use of
unsigned images under RD environments?
Beyond th
Thank you all for the review comments and tags.
I will prepare the v8 patch with tag included and comments addressed.
In addition, as DM_HASH has been merged into the master branch.
The v8 patch will be rebased on the master branch.
Thanks,
Chiawei
> From: U-Boot On Behalf Of Chia-Wei Wang
> Se
> From: U-Boot On Behalf Of ChiaWei Wang
> Sent: Thursday, October 21, 2021 9:57 AM
>
> > From: Dhananjay Phadke
> > Sent: Thursday, October 21, 2021 9:33 AM
> >
> > On Wed, 20 Oct 2021, Chia-Wei Wang wrote:
> >
> > > +static const struct
> From: Joel Stanley
> Sent: Thursday, October 21, 2021 8:08 AM
>
> On Wed, 20 Oct 2021 at 02:50, Chia-Wei Wang
> wrote:
> >
> > Add RSACLK enable for ACRY, the HW RSA/ECC crypto engine of ASPEED
> > AST2600 SoCs.
> >
> > As ACRY and HACE share the same reset control bit, we do not perform
> > t
> From: Joel Stanley
> Sent: Thursday, October 21, 2021 8:08 AM
>
> On Wed, 20 Oct 2021 at 02:49, Chia-Wei Wang
> wrote:
> >
> > Fix inconsistent function parameter name of the hash algorithm.
> >
> > Signed-off-by: Chia-Wei Wang
> > Fixes: 92055e138f2 ("image: Drop if/elseif hash selection in
> From: Joel Stanley
> Sent: Thursday, October 21, 2021 8:08 AM
>
> On Wed, 20 Oct 2021 at 02:50, Chia-Wei Wang
> wrote:
> >
> > From: Johnny Huang
> >
> > Hash and Crypto Engine (HACE) is designed to accelerate the throughput
> > of hash data digest, and symmetric-key encryption.
> >
> > Signe
> From: Joel Stanley
> Sent: Thursday, October 21, 2021 8:25 AM
>
> On Wed, 20 Oct 2021 at 02:50, Chia-Wei Wang
> wrote:
> >
> > ACRY is deisnged to accerlerate ECC/RSA digital signature
>
> designed
> accelerate
Thanks for pointing out the typo. It will be fixed in the next revision
Regards,
> From: Joel Stanley
> Sent: Thursday, October 21, 2021 8:31 AM
>
> On Wed, 20 Oct 2021 at 02:50, Chia-Wei Wang
> wrote:
> >
> > Move CONFIG_EXTRA_ENV_SETTINGS to board-specific configuration
> > headers.
> >
> > Signed-off-by: Chia-Wei Wang
> > ---
> > include/configs/aspeed-common.h | 9
> From: Dhananjay Phadke
> Sent: Thursday, October 21, 2021 9:33 AM
>
> On Wed, 20 Oct 2021, Chia-Wei Wang wrote:
>
> > +static const struct hash_ops aspeed_hace_ops = {
> > + .hash_init = aspeed_hace_init,
> > + .hash_update = aspeed_hace_update,
> > + .hash_finish = aspeed_hace_finish,
>
> From: U-Boot On Behalf Of Chia-Wei Wang
> Sent: Friday, October 15, 2021 10:04 AM
>
> ACRY is deisnged to accerlerate ECC/RSA digital signature generation and
> verification.
>
> Signed-off-by: Chia-Wei Wang
> ---
> drivers/crypto/aspeed/Kconfig | 10 ++
> drivers/crypto/aspeed/Makefi
Hi Simon,
> From: Simon Glass
> Sent: Thursday, October 14, 2021 11:10 PM
>
> Hi Chia-Wei,
>
> On Sun, 3 Oct 2021 at 19:54, Chia-Wei Wang
> wrote:
> >
> > Fix inconsistent function parameter name of the hash algorithm.
> >
> > Signed-off-by: Chia-Wei Wang
> > Fixes: 92055e138f2 ("image: Drop
Hi Simon,
> From: Simon Glass
> Sent: Wednesday, October 6, 2021 10:10 PM
>
> Hi Chia-Wei,
>
> On Thu, 16 Sept 2021 at 00:39, Chia-Wei Wang
> wrote:
> >
> > Use DM_HASH to perform hashing operations if supported.
> > Thus either SW or HW-assisted hashing could be leveraged.
>
> This is missin
Hi Tom,
> From: Tom Rini
> Sent: Monday, October 4, 2021 2:41 AM
>
> On Thu, Sep 16, 2021 at 04:52:19PM +0800, Chia-Wei Wang wrote:
>
> > Enable SPL FIT image load and verification support.
> > The HW accelerated SHA is also available with the newly added support
> > of the HACE HW hash engine.
Hi Simon,
> From: Simon Glass
> Sent: Thursday, September 23, 2021 12:19 AM
>
> Hi,
>
> On Thu, 2 Sept 2021 at 07:28, Tom Rini wrote:
> >
> > On Fri, Jul 30, 2021 at 09:08:03AM +0800, Chia-Wei Wang wrote:
> >
> > > Add UCLASS_HASH for hash driver development. Thus the hash drivers
> > > (SW or
Hi Alex,
> From: Alex G.
> Sent: Friday, September 17, 2021 12:00 AM
>
> On 7/29/21 8:08 PM, Chia-Wei Wang wrote:
> > Calculate hash using DM driver if supported.
> > For backward compatibility, the call to legacy hash functions is
> > reserved.
> >
> > Signed-off-by: Chia-Wei Wang
> > ---
> >
ance between the hash algos support and the code size can be
managed.
>
> > diff --git a/drivers/crypto/hash/hash_sw.c
> > b/drivers/crypto/hash/hash_sw.c new file mode 100644 index
> > 00..fea9d12609
> > --- /dev/null
> > +++ b/drivers/crypto/hash/ha
the hash/ out of crypto/ if a more specific
place is created and preferred.
>
> [snip]
> > diff --git a/drivers/crypto/hash/hash-uclass.c
> > b/drivers/crypto/hash/hash-uclass.c
> > new file mode 100644
> > index 00..446eb9e56a
> > --- /dev/null
>
Hi All,
Do you have update on this patch series?
We look forward to continuing the SPL FIT booting patch for Aspeed SoCs based
on this one.
Any advice and suggestions are appreciated.
Chiawei
> From: U-Boot On Behalf Of Chia-Wei Wang
> Sent: Friday, July 30, 2021 9:08 AM
>
> This patch series
Hi Peng,
> -Original Message-
> From: Peng Fan (OSS)
> Sent: Tuesday, August 3, 2021 2:02 PM
>
>
> On 2021/8/3 5:30, Tom Rini wrote:
> > On Mon, Aug 02, 2021 at 06:44:57PM +0800, Chia-Wei Wang wrote:
> >> A U-Boot image could be loaded and executed at a different location
> >> than it w
Hi Tom,
> From: Tom Rini
> Sent: Tuesday, August 3, 2021 5:31 AM
> On Mon, Aug 02, 2021 at 06:44:57PM +0800, Chia-Wei Wang wrote:
> > A U-Boot image could be loaded and executed at a different location
> > than it was linked at.
> >
> > For example, Aspeed takes a stable release version of U-Boot
Hi Tom,
> From: Tom Rini
> Sent: Saturday, July 24, 2021 8:57 PM
>
> On Tue, Jul 20, 2021 at 02:38:31PM +0800, Chia-Wei Wang wrote:
>
> > From: Joel Stanley
> >
> > Currently the FIT verification calls directly into SW implemented
> > functions to get a CRC/SHA/MD5 hash.
> >
> > This patch rem
Hi Simon,
> -Original Message-
> From: Simon Glass
> Sent: Wednesday, July 21, 2021 2:33 AM
>
> Hi Chia-Wei,
>
> On Tue, 20 Jul 2021 at 00:38, Chia-Wei Wang
> wrote:
> >
> > From: Joel Stanley
> >
> > Hash and Crypto Engine (HACE) is designed to accelerate the throughput
> > of hash d
021 10:24 AM
> To: u-boot@lists.denx.de
> Cc: Ryan Chen ; ChiaWei Wang
> ; BMC-SW
> Subject: [PATCH 07/13] arm: aspeed: Disable ATAGs support
>
> This platform never had to support an ATAGs-based Linux kernel, so remove
> the support for it.
>
> Cc: Ryan Chen
> Cc:
Hi Tom,
The patches has been rebased onto the up-to-date U-Boot master.
A makefile error is also fixed in the revised version and verified with an
AST2500 EVB.
Thanks,
Chiawei
> -Original Message-
> From: ChiaWei Wang
> Sent: Thursday, October 15, 2020 10:25 AM
Hi Tom,
Thanks for the review.
> -Original Message-
> From: Tom Rini
> Sent: Thursday, October 8, 2020 11:52 PM
> To: ChiaWei Wang
> Cc: Ryan Chen ; max...@google.com;
> u-boot@lists.denx.de; BMC-SW
> Subject: Re: [PATCH 0/2] Refactor AST2500 reset control
>
&
patches are in fact refactoring to the existing Aspeed code structure in
U-Boot.
When the refactoring is done, we would like to send a patch series for the
support of Aspeed next generation SoC (AST2600).
Thanks.
Chiawei
> -Original Message-
> From: ChiaWei Wang
> Sent
> -Original Message-
> From: Ryan Chen
> Sent: Monday, August 31, 2020 2:03 PM
> To: Ryan Chen ; ChiaWei Wang
> ; Lukasz Majewski ;
> c...@kaod.org; Eddie James ; Simon Glass
> ; u-boot@lists.denx.de
> Subject: [PATCH v2 3/3] cosmetic: aspeed: Modify for SPDX-
> -Original Message-
> From: Ryan Chen
> Sent: Monday, August 31, 2020 2:03 PM
> To: Ryan Chen ; ChiaWei Wang
> ; Lukasz Majewski ;
> c...@kaod.org; Eddie James ; Simon Glass
> ; u-boot@lists.denx.de
> Subject: [PATCH v2 1/3] cosmetic: aspeed: ast2500: Rename cloc
> -Original Message-
> From: Ryan Chen
> Sent: Monday, August 31, 2020 2:03 PM
> To: Ryan Chen ; ChiaWei Wang
> ; Lukasz Majewski ;
> c...@kaod.org; Eddie James ; Simon Glass
> ; u-boot@lists.denx.de
> Subject: [PATCH v2 2/3] clock:aspeed: Sync with Linux kern
Hi Tom,
Thank you for the feedback.
> -Original Message-
> From: Tom Rini [mailto:tr...@konsulko.com]
> Sent: Tuesday, August 11, 2020 11:26 PM
> To: ChiaWei Wang
> Cc: u-boot@lists.denx.de
> Subject: Re: [U-Boot] requesting a custodian tree for Aspeed SoCs
> ma
Hi,
We are Aspeed SW team and would like to request the creation of a
u-boot-aspeed.git
custodian tree for the u-boot support related to Aspeed SoCs. Attached is the
SSH key
generated for this purpose.
By the way, the Aspeed SoCs are based on ARM architecture. However, we are not
sure
if the A
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