On 4/16/24 9:59 PM, E Shattow wrote:
On Tue, Apr 9, 2024 at 11:44 PM Bo Gan wrote:
On 4/9/24 6:55 PM, E Shattow wrote:
Original speed class SD cards fail with this change "unable to change mode".
The BUS_ROOT clock will have to be switched to PLL2 anyway in U-Boot proper o
On 4/9/24 6:55 PM, E Shattow wrote:
Original speed class SD cards fail with this change "unable to change mode".
On Tue, Mar 12, 2024 at 4:12 AM Hal Feng wrote:
On 06.03.24 11:00, Bo Gan wrote:
Previously PLL node was missing from SPL dts. This caused BUS_ROOT to stay on
OSC cl
Previously PLL node was missing from SPL dts. This caused BUS_ROOT
to stay on OSC clock (24Mhz). As a result, all peripherals have to
run at a much lower frequency, and loading from sdcard/emmc is slow.
Thus, enabling PLL node in dts to fix this.
Signed-off-by: Bo Gan
---
arch/riscv/dts/jh7110
On 6/14/23 10:15 AM, Ben Dooks wrote:
On 14/06/2023 07:25, Bo Gan wrote:
On 5/25/23 4:05 AM, Ben Dooks wrote:
On 15/05/2023 14:03, Ben Dooks wrote:
When debugging, it is useful to have a backtrace to find
out what is in the call stack as the previous function (RA)
may not have been the
On 5/25/23 4:05 AM, Ben Dooks wrote:
On 15/05/2023 14:03, Ben Dooks wrote:
When debugging, it is useful to have a backtrace to find
out what is in the call stack as the previous function (RA)
may not have been the culprit.
Since this adds size to the build, do not add it by default
and avoid pu
spl_clear_bss (start.S)
| hole |
++
| Image+DTB | <--- Assuming cleared/loaded by ROM
+----+ 0x800
Signed-off-by: Bo Gan
Cc: samin . guo
Cc: Yanhong Wang
Cc: Rick Chen
Cc: Leo
Cc: Sean Anderson
Cc: Lukas
stack |++
++| ..|
| ..|| malloc_base |
++++
| hart N-1 stack|| GD|
++++
||||
Signed-off-by: Bo Gan
Cc: Rick Chen
Cc: Leo
Cc: Sean An
Hi Yanhong and others,
I've made up my own version and addressed my concerns in this patch:
https://patchwork.ozlabs.org/project/uboot/patch/1684668616-358043-1-git-send-email-ganbo...@gmail.com/
Some descriptions would be similar, as they are from my previous response to
Heinrich:
https://lis
spl_clear_bss (start.S)
| hole |
++
| Image+DTB | <--- Assuming cleared/loaded by ROM
+----+ 0x800
Signed-off-by: Bo Gan
Cc: samin . guo
Cc: Yanhong Wang
Cc: Rick Chen
Cc: Leo
Cc: Sean Anderson
Cc: Lukas
On 5/17/23 11:41 PM, Yanhong Wang wrote:
SPL runs on the L2 LIM, which is 2M in size mapped at 0x800.This
region consists of 16 0x2 sized regions, each one can be used as
either L2 cache way or SRAM (not both).From top to bottom, you have way
0-15.The way 0 is always enabled, so SPL can o
On 5/17/23 11:41 PM, Yanhong Wang wrote:
The per-hart stack,malloc space and global variable 'gd' sits between
__bss_end and L2_LIM_MEM_END.Zeroing this region could overwrite the
hart's stack, and other harts' stacks.If it were to save and restore
`ra` register, then we would crash in function e
On 5/14/23 10:08 PM, Rick Chen wrote:
Hi Bo Gan,
It builds fail as below:
arch/riscv/cpu/start.S:97: Error: illegal operands `li
t0,CONFIG_SYS_INIT_SP_ADDR'
Thanks,
Rick
Hi Rick & Leo,
Please help take a look at v2 of the patch:
https://patchwork.ozlabs.org/project/uboot/patch/1
stack |++
++| ..|
| ..|| malloc_base |
++++
| hart N-1 stack|| GD|
++++
||||
Signed-off-by: Bo Gan
Cc: Rick Chen
Cc: Leo
Cc: Sean An
@Heinrich Some background information I discovered by experimenting with my vf2
board:
The only reasonable place to load SPL is the L2 LIM, which is 2M in size mapped
at
0x800. This region consists of 16 0x2 sized regions, each one can be
used as
either L2 cache way or SRAM (not both).
On 5/16/23 6:11 AM, Heinrich Schuchardt wrote:
The size of SPL including the 1 KiB header added by spl_tool may not exceed
128 KiB. Without the header this leaves 127 KiB for spl/u-boot-spl.bin.
We should check this value when building to avoid oversized binaries.
+CONFIG_SPL_SIZE_LIMIT=0x1fc00
On 4/27/23 7:25 PM, Yanhong Wang wrote:
+struct starfive_eeprom {
+ struct eeprom_header header;
+ struct starfive_eeprom_atom1 atom1;
+ struct starfive_eeprom_atom4 atom4;
+};
+
+static uchar eeprom_buf[STARFIVE_EEPROM_HATS_SIZE_MAX];
+
+struct starfive_eeprom *pbuf = (struct s
On 3/28/23 8:42 PM, Yanhong Wang wrote:
+void harts_early_init(void)
+{
+ ulong *ptr;
+ u8 *tmp;
+ ulong len, remain;
+ /*
+* Feature Disable CSR
+*
+* Clear feature disable CSR to '0' to turn on all features for
+* each core. This operation
stack |++
++| ..|
| ..|| malloc_base |
++++
| hart N-1 stack|| GD|
++++
||||
Signed-off-by: Bo Gan
Cc: Rick Chen
Cc: Leo
---
arch
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