>ddr_init_addr);
out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
So for me the timing_cfg_2 must be set at a deterministic value to avoid
stability issue when the CONFIG_SYS_FSL_ERRATUM_DDR_A003474 flag is set.
Many thanks
Benoit
On 08/12/2014 08:07 PM, York Sun wrote:
> On 07/
mple for you to follow.
>
> But again, we should fix the DMA function anyway.
>
> York
>
>
> On 07/23/2014 12:21 AM, Benoit Sansoni wrote:
>> Hi York,
>>
>> That what I saw in the code.
>>
>> Also to test it you need to have the hardware, but the
and 4GB.
If you need help, you are welcome.
Thanks for your help
Benoit
On 07/23/2014 12:53 AM, York Sun wrote:
> On 07/18/2014 06:11 AM, Benoit Sansoni wrote:
>> Hi ,
>>
>> I found out an issue when enabling ECC for P2041 platform with an amount
>> of memory o
Hi ,
I found out an issue when enabling ECC for P2041 platform with an amount
of memory of 8GB.
The routine "void dma_meminit(uint val, uint size)" is not adapted to
manage memory size greater or equal to 4GB due to the 'uint' type.
With this typing the dma_meminit sees 0 as size when memory is fo
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