Re: [BUG] network is broken on Orange Pi PC

> >>>> > > >>>>mii_cmd |= MDIO_CMD_MII_BUSY; > > >>>> > > >>>> @@ -242,7 +244,9 @@ static int sun8i_mdio_write(struct mii_dev > *bus, int > > >>>> addr, int devad, int reg, > > >>>> * The EMAC clock is either 200 or 300 MHz, so we need a > divider > > >>>> * of 128 to get the MDIO frequency below the required > 2.5 MHz. > > >>>> */ > > >>>> - mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 << > > >>>> MDIO_CMD_MII_CLK_CSR_SHIFT; > > >>>> + if (!priv->use_internal_phy) > > >>>> + mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 << > > >>>> + MDIO_CMD_MII_CLK_CSR_SHIFT; > > >>>> > > >>>>mii_cmd |= MDIO_CMD_MII_WRITE; > > >>>>mii_cmd |= MDIO_CMD_MII_BUSY; > I tried this with my v3s which has only an internal phy. u-boot wasn't able to establish a connection with any speed and duplex mode combination. All i get is `ethernet@1c3 Waiting for PHY auto negotiation to complete. TIMEOUT !` Do you work with the internal or external phy @Heinrich? Did you try the default u-boot with a different speed and duplex mode combination and have the same behavior? Greetings andreas > >>>> > > >>>> Best regards > > >>>> > > >>>> Heinrich > > >>>> > > >>>> I would assume the problem hits all H3 boards. > > >>> > > >>> And that's the confusing part: it does not. I tested this on my > > >>> OrangePi Zero (H2+ with internal PHY), both back then with the > original > > >>> MDIO frequency patch and also now after your report. It always worked > > >>> reliably for me. > > >>> Also: I am still puzzled how one influences the other: The error you > > >>> get is from the *MAC* soft reset: I would think this is an > independent > > >>> operation from any communication attempts with the PHY. > > >>> > > >>> There is this thread here about the same symptom on a V3s: > > >>> https://lists.denx.de/pipermail/u-boot/2021-May/450315.html > > >>> v2 of this original patch (in the same thread) proposes some other > > >>> solution, which I am also not very happy with. But just to get some > more > > >>> data points: can you check whether skipping the soft reset fixes this > > >>> for you? I will have a closer look tonight to check the order of soft > > >>> reset and PHY communication. Maybe we should only do the soft reset > > >>> *once* when the MAC probes, and not on every .start call? > > >>> > > >>> Thanks, > > >>> Andre > > >>> > > >> > > > > > > > -- Mit freundlichen Grüßen / kind regards Andreas Rehn | Master of Engineering (M.Eng)

Re: [PATCH 6/6] net: sun8i-emac: v3s: fix soft reset timeout

Am Do., 3. Juni 2021 um 16:43 Uhr schrieb Heinrich Schuchardt < xypron.g...@gmx.de>: > On 6/3/21 3:56 PM, Andre Przywara wrote: > > On Fri, 21 May 2021 22:14:00 +0200 > > Andreas Rehn wrote: > > > > Hi, > > > >> sorry for the late response. &g

[PATCH v2 6/6] net: sun8i-emac: v3s: fix soft reset timeout

kernel driver dwmac-sun8i work very nice and don't provide a soft reset. Skip soft reset on u-boot for V3s provide the expected behavior on all connection permutations. If cable is not plugged in, the timeout comes form the phy driver itself. Signed-off-by: Andreas Rehn --- Changes

[PATCH v2 4/6] net: sun8i-emac: add v3s variant

Add variant V3S_EMAC. Handle pinmux compile time error by skipping goio setup, because V3s uses internal phy and don't expose pins. Signed-off-by: Andreas Rehn --- Changes in v2: - skip pinmux and add proper description - Add V3S variant add it to compatible list -

[PATCH v2 3/6] clk: sunxi: v3s: fix tabs / spaces

align CLK_USB_PHY0 with tabs Signed-off-by: Andreas Rehn --- Changes in v2: - revert CLK_SPI0 extra tab drivers/clk/sunxi/clk_v3s.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c index 55fc597043..bc6b7b4870

Re: [PATCH 6/6] net: sun8i-emac: v3s: fix soft reset timeout

8 Uhr schrieb Andre Przywara < andre.przyw...@arm.com>: > On Thu, 20 May 2021 00:10:47 +0200 > Andreas Rehn wrote: > > > hey, > > > > sure. I give it a try tomorrow. > > with 250 ms, for example, I ran into timeouts after the first tftp > download. >

[PATCH v2 5/6] dts: sunxi: v3s: enable emac

Enable emac for licheepi-zero-dock as it provides a ethernet port Signed-off-by: Andreas Rehn --- arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts | 9 + 1 file changed, 9 insertions(+) diff --git a/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts b/arch/arm/dts/sun8i-v3s-licheepi-zero

[PATCH v2 4/6] net: sun8i-emac: add v3s variant

Add variant V3S_EMAC. Skip GPIO setup for V3s because it uses internal phy and don't expose pins. Signed-off-by: Andreas Rehn --- drivers/net/sun8i_emac.c | 17 + 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_e

[PATCH v2 3/6] clk: sunxi: v3s: fix tabs / spaces

align CLK_USB_PHY0 with tabs Signed-off-by: Andreas Rehn --- drivers/clk/sunxi/clk_v3s.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c index 55fc597043..bc6b7b4870 100644 --- a/drivers/clk/sunxi/clk_v3s.c +++ b

Re: [PATCH 6/6] net: sun8i-emac: v3s: fix soft reset timeout

com>: > On Wed, 19 May 2021 21:42:08 +0200 > Andreas Rehn wrote: > > Hi, > > > v3s emac soft reset tooks quit longer if autonegation is active > > on 100 Mbit full duplex pairs what can result in > > `sun8i_emac_eth_start: Timeout` error > > Mmmh,

Re: [PATCH 3/6] clk: sunxi: v3s: fix tabs / spaces

May 2021 21:42:05 +0200 > Andreas Rehn wrote: > > Hi, > > > align CLK_SPI0 and CLK_USB_PHY0 with tabs > > > > Signed-off-by: Andreas Rehn > > --- > > drivers/clk/sunxi/clk_v3s.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > &

Re: [PATCH 1/6] dts: sunxi: add licheepi-zero-dock

., 19. Mai 2021 um 23:42 Uhr schrieb Andre Przywara < andre.przyw...@arm.com>: > On Wed, 19 May 2021 21:42:03 +0200 > Andreas Rehn wrote: > > Hi Andreas, > > > licheepi-zero dock is the second gen licheepi-zero board > > and brings addtional periperals like &

[PATCH 6/6] net: sun8i-emac: v3s: fix soft reset timeout

(e.g. timeouts on tftp download). Signed-off-by: Andreas Rehn --- drivers/net/sun8i_emac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index 0e7ad3b0d4..23fd35f9e1 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net

[PATCH 5/6] dts: sunxi: v3s: enable emac support

h3 and v3s have internal phys and can share the same driver. Furthermore sun8i-v3s-emac is not available, use sun8i-h3-emac instead - add emac pins - enable emac for licheepi-zero-dock as it provides a ethernet port Signed-off-by: Andreas Rehn --- arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts

[PATCH 4/6] net: sun8i-emac: add v3s pinmux setting

Driver uses pinmux instead of emac type. Add v3s pinmux to support SoC. Signed-off-by: Andreas Rehn --- drivers/net/sun8i_emac.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index 5a1b38bf80..0e7ad3b0d4 100644 --- a/drivers/net

[PATCH 2/6] clk: sunxi: v3s: Implement EMAC clocks/resets

Add emac clock and reset register/bits. Signed-off-by: Andreas Rehn --- drivers/clk/sunxi/clk_v3s.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c index 29622199fd..55fc597043 100644 --- a/drivers/clk/sunxi/clk_v3s.c +++ b

[PATCH 3/6] clk: sunxi: v3s: fix tabs / spaces

align CLK_SPI0 and CLK_USB_PHY0 with tabs Signed-off-by: Andreas Rehn --- drivers/clk/sunxi/clk_v3s.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c index 55fc597043..9c2717bfab 100644 --- a/drivers/clk/sunxi

[PATCH 1/6] dts: sunxi: add licheepi-zero-dock

MAINTAINER item and provide a defconfig. Signed-off-by: Andreas Rehn --- arch/arm/dts/Makefile| 3 ++- board/sunxi/MAINTAINERS | 5 + configs/LicheePi_Zero_dock_defconfig | 7 +++ 3 files changed, 14 insertions(+), 1 deletion(-) create mode 100644 configs

[PATCH 0/6] arm: sunxi: v3s: add ethernet support

wasn't able to get a stable connection on 100 Mb full duplex switches with autonegation enabled. Maybe the internal phy has a different behavior on softreset then others which results in a delayed established link. Andreas Rehn (6): dts: sunxi: add licheepi-zero-dock clk: sunxi: v3s: Implement