[U-Boot] [PATCH 3/3] crypto/fsl: add support for multiple SEC engines initialization

From: Alex Porosanu For SoCs that contain multiple SEC engines, each of them needs to be initialized (by means of initializing among others the random number generator). Signed-off-by: Alex Porosanu --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 9 ++ drivers/crypto/fsl/jr.c | 271

[U-Boot] [PATCH 1/3] arch/arm: add SEC JR0 offset

From: Alex Porosanu Freescale PPC SoCs do not hard-code security engine's Job Ring 0 address, rather a define is used. This patch adds the same functionality to the ARM based SoCs (i.e. LS1/LS2 and i.MX parts) Signed-off-by: Alex Porosanu --- arch/arm/include/asm/arch-fsl-layer

[U-Boot] [PATCH 0/3] Multiple FSL Security Engine RNG instantation

This series of patches add the neccesary support for allowing multi-SEC SoCs, like the C292 & C293 to instantiate the respecting RNGs. Alex Porosanu (3): arch/arm: add SEC JR0 offset arch/arm, arch/powerpc: add # of SEC engines on the SOC crypto/fsl: add support for multiple SEC eng

[U-Boot] [PATCH 2/3] arch/arm, arch/powerpc: add # of SEC engines on the SOC

From: Alex Porosanu Some SOCs, specifically the ones in the C29x familiy can have multiple security engines. This patch adds a system configuration define which indicates the maximum number of SEC engines that can be found on a SoC. Signed-off-by: Alex Porosanu --- arch/arm/include/asm/arch

[U-Boot] [PATCH] armv8/fdt: add fixup_crypto_node

For Qoriq PPC&ARM v7 platforms, the crypto node is being fixup'ed in order to update the SEC internal version (aka SEC ERA). This patch adds the same functionality to the ARMv8 SoCs. Signed-off-by: Alex Porosanu --- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 19 ++

[U-Boot] [PATCH 2/3] crypto/fsl - change starting entropy delay value

starting value of the length of the entropy sample to 3200 system clocks. In addition to this change, the attempted entropy delay values are now printed on the console upon initialization of the RNG block. Signed-off-by: Alex Porosanu --- include/fsl_sec.h | 2 +- 1 file changed, 1 insertion

[U-Boot] [PATCH 0/3] CAAM RNG fixes

This set of patches fixes some issues identified with the usage of the RNG block of the CAAM in newer SoCs e.g. T2080. Alex Porosanu (3): crypto/fsl - disable RNG oscillator maximum frequency check crypto/fsl - change starting entropy delay value crypto/fsl - enable raw data instead of von

[U-Boot] [PATCH 1/3] crypto/fsl - disable RNG oscillator maximum frequency check

d as being out of bounds. This patch effectively disables the maximum frequency check, by setting a high enough maximum allowable frequency for the oscillator. The reasoning behind this is that usually a broken oscillator will run too slow (i.e. not run at all) rather than run too fast. Signed-off-by:

[U-Boot] [PATCH 3/3] crypto/fsl - enable raw data instead of von Neumann data

The sampling of the oscillator can be done in multiple modes for generating the entropy value. By default, this is set to von Neumann. This patch changes the sampling to raw data, since it has been discovered that the generated entropy has a better 'quality'. Signed-off-by: Ale