To enforce anti-rollback to any older version, dtb must be
always update manually. This should be described in the
documentation.
This commit also adds the recommendation that secure system should not
enable the fdt command because lowest-supported-version
property in device tree can be changed by
> -Original Message-
> From: Marek Vasut
> Sent: Wednesday, 21 June, 2023 7:16 PM
> To: Chong, Teik Heng ; u-boot@lists.denx.de
> Cc: Jagan Teki ; Vignesh R ;
> Simon ; Kris ;
> Chee, Tien Fong ; Hea, Kok Kiang
> ; Lokanathan, Raaj ;
> Maniyam, Dinesh ; Ng, Boon Khai
> ; Yuslaimi, Alif Za
> -Original Message-
> From: Marek Vasut
> Sent: Wednesday, 21 June, 2023 10:19 PM
> To: Lim, Jit Loon ; u-boot@lists.denx.de
> Cc: Jagan Teki ; Simon
> ; Chee, Tien Fong
> ; Hea, Kok Kiang ;
> Lokanathan, Raaj ; Maniyam, Dinesh
> ; Ng, Boon Khai ;
> Yuslaimi, Alif Zakuan ; Chong, Teik Hen
Hi Pali,
FYI. In reference to this patch:
https://lore.kernel.org/all/20230114164125.1298-1-p...@kernel.org/
Recently, I built a new Linux kernel 6.3.x for the Kirkwood boards and
discovered that the PCI_MVEBU driver was marked as BROKEN in Linux
mainline. That was a surprise for me, since I've b
On 6/20/23 16:37, Jagan Teki wrote:
Hi,
Has anyone tried to use dwc2 and echi port together with USB disk?
look like this is not working with this combination on any Rockchip
SoC's
Here are the issues that I've reproduced in RK3328 where the disk
connected in EHCI port is detecting but DWC2 is
On Wed, Jun 21, 2023 at 04:21:18PM +0200, Marek Vasut wrote:
> The following changes since commit 50842b217fef505a0ec6662cc2acdc55d0bb23c5:
>
> Merge tag 'u-boot-at91-fixes-2023.07-a' of
> https://source.denx.de/u-boot/custodians/u-boot-at91 (2023-06-19 09:18:40
> -0400)
>
> are available in
On 6/21/23 04:55, Andre Przywara wrote:
On Tue, 20 Jun 2023 16:11:48 -0600
Sam Edwards wrote:
Hi Sam,
pleasure to write with you ;-)
Hi Andre,
Likewise!
Well, so this is actually the fallback implementation which should
somewhat work on most SoCs: set a flag, reset, and catch the flag in
On Thu, Jun 08, 2023 at 09:55:59AM +0900, AKASHI Takahiro wrote:
> dm_test_restore() is called after dm unit test is run.
> But this function does not scan any nodes under /firmware since
> it calls dm_scan_fdt().
>
> This causes an issue. For instance, scmi_sandbox_agent device
> will disappear
On Tue, Jun 06, 2023 at 08:37:42PM +0900, Masahiro Yamada wrote:
> This function is not used by anyone.
>
> Signed-off-by: Masahiro Yamada
> Reviewed-by: Simon Glass
Applied to u-boot/next, thanks!
--
Tom
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Description: PGP signature
On Sat, Jun 03, 2023 at 06:06:14PM +0530, Vignesh Raghavendra wrote:
> Enable CONFIG_TI_SECURE_DEVICE to support booting High Secure(HS)
> variants of AM64x SoC.
>
> Signed-off-by: Vignesh Raghavendra
Applied to u-boot/next, thanks!
--
Tom
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On Thu, Jun 01, 2023 at 06:13:51PM +0900, Masahisa Kojima wrote:
> DM_FLAG_PRE_RELOC flag is added into some drivers
> by recent commits such as
> 1bd790bc4b ("firmware: psci: enable DM_FLAG_PRE_RELOC").
> Current SYS_MALLOC_F_LEN of SynQuacer Developerbox platform
> is too small, Developerbox wil
On Wed, May 31, 2023 at 03:03:58AM +0200, Marek Vasut wrote:
> Add test for command bdinfo .
>
> Signed-off-by: Marek Vasut
> Reviewed-by: Simon Glass
Applied to u-boot/next, thanks!
--
Tom
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On Tue, May 30, 2023 at 03:50:30PM -0400, Tom Rini wrote:
> Per GitHub Dependabot:
> - Use setuptools 65.5.1 to avoid some DoS issue
> - Use requests 2.31.0 to avoid leaking some proxy information
>
> Signed-off-by: Tom Rini
> Tested-by: Heinrich Schuchardt
Applied to u-boot/next, thanks!
--
On Mon, May 29, 2023 at 03:42:28PM +0200, Julien Panis wrote:
> At first SPI transfers, multiple chip selects can be
> enabled simultaneously. This is due to chip select
> polarity, which is not properly initialized for all
> channels. This patch fixes the issue.
>
> Signed-off-by: Julien Panis
On Sat, May 27, 2023 at 06:09:42PM -0600, Sam Edwards wrote:
> The functions `psci_get_context_id` and `psci_get_target_pc`
> are written in C, so the C compiler may clobber registers r0-r3.
> Do not use these registers to save data across calls.
>
> Signed-off-by: Sam Edwards
Applied to u-boot
On Thu, May 25, 2023 at 10:18:05AM +0200, Stefano Babic wrote:
> Use a variable (MKIMAGE_SIGN_PASSWORD) like already done for RSA to
> allow the signing process to run in batch.
>
> Signed-off-by: Stefano Babic
Applied to u-boot/next, thanks!
--
Tom
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On Mon, Jun 05, 2023 at 10:40:26AM +0900, Chan Kim wrote:
> I'm trying sending a patch for the first time.
> I found when running u-boot qemu_arm64_defconfig on qemu-6.2.0's arm64 virt
> machine, we need CONFIG_GICV3.
> And for the GICV3 related to be compiled, we need to add GICD_BASE,
> GICR_BAS
On Wed, Jun 21, 2023 at 03:51:18PM +0530, Nikhil M Jain wrote:
> To understand usage of DDR in A53 SPL stage, add a table showing region
> and space used by major components of SPL.
>
> Signed-off-by: Nikhil M Jain
Reviewed-by: Tom Rini
--
Tom
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On Wed, Jun 21, 2023 at 05:56:56PM +0200, Julien Panis wrote:
> This patch fixes a bad condition for USB device definition.
> This prevents from getting a "No USB device found" error.
>
> Fixes: 6815a66ad7430 ("am33xx: musb: Remove unused configuration logic")
> Signed-off-by: Julien Panis
> ---
ned(CONFIG_SPL_BUILD)
+ !defined(CONFIG_SPL_BUILD)
static struct musb_hdrc_config musb_config = {
.multipoint = 1,
---
base-commit: 19b77d3d23966a0d6dbb3c86187765f11100fb6f
change-id: 20230621-fix_usb_ether_init-4bf4f1135113
Best regards,
--
Julien Panis
ao-secure node can be used to get information about the board,
so, for example, using show_board_info() we can get following
information for board with Meson A1 SoC:
SoC: Amlogic Meson A1 (A113L) Revision 2c:a (1:a)
Signed-off-by: Alexey Romanov
---
arch/arm/dts/meson-a1.dtsi | 6 ++
1 file
Add support for hardware random number generator
of Amlogic Meson SoCs.
Signed-off-by: Alexey Romanov
---
arch/arm/dts/meson-a1.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/meson-a1.dtsi b/arch/arm/dts/meson-a1.dtsi
index f3560cbc3a4..1f57c137384 100644
--- a/arch/a
From: Quentin Schulz
Puma supports upstream TF-A and is configured to output serial on UART0
instead of the default UART2. Since U-Boot is properly configured to
output on UART0, let's pass the DT to TF-A so there is no need for a
custom TF-A to make the latter output to UART0 too.
Cc: Quentin S
From: Quentin Schulz
Long are gone the times TF-A couldn't handle the FDT passed by U-Boot.
Specifically, since commit e7b586987c0a ("rockchip: don't crash if we
get an FDT we can't parse") in TF-A, failure to parse the FDT will use
the fallback mechanism. This patch was merged in TF-A v2.4-rc0 f
Finally pass the FDT address to TF-A since it now gracefully fallbacks to
hardcoded defaults if it cannot parse it. This allows us to avoid modifying
hardcoded values in TF-A to enable the console.
This was tested with TF-A v2.9.0 on Puma Haikou RK3399.
We do this only for new RK3399 boards, wher
This RISC-V ACLINT specification [1] defines a set of memory mapped
devices which provide inter-processor interrupts (IPI) and timer
functionalities for each HART on a multi-HART RISC-V platform.
This seriesl updates U-Boot existing SiFive CLINT driver to handle
the ACLINT changes, and is now able
As the RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V
ALINT in the source tree to be future-proof.
Signed-off-by: Bin Meng
Reviewed-by: Rick Chen
---
(no changes since v1)
MAINTAINERS
This RISC-V ACLINT specification [1] defines a set of memory mapped
devices which provide inter-processor interrupts (IPI) and timer
functionalities for each HART on a multi-HART RISC-V platform.
The RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specificati
This RISC-V ACLINT specification [1] defines a set of memory mapped
devices which provide inter-processor interrupts (IPI) and timer
functionalities for each HART on a multi-HART RISC-V platform.
The RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specificati
In current linker script both .efi_runtime_rel and .rela.dyn sections
are of RELA type whose entry size is either 12 (RV32) or 24 (RV64).
These two are arranged as an continuous region on purpose so that the
prelink-riscv executable can fix up the PIE addresses in one loop.
However there is an 'AL
The following changes since commit 50842b217fef505a0ec6662cc2acdc55d0bb23c5:
Merge tag 'u-boot-at91-fixes-2023.07-a' of
https://source.denx.de/u-boot/custodians/u-boot-at91 (2023-06-19 09:18:40 -0400)
are available in the Git repository at:
git://source.denx.de/u-boot-usb.git master
for yo
On 6/21/23 16:15, Marc Zyngier wrote:
On Wed, 21 Jun 2023 15:06:51 +0100,
Jit Loon Lim wrote:
From: Kah Jing Lee
Dcache feature is not enabled in SPL and enable it will cause ISR
exception. Since the Dcache is not supported in SPL, new
CONFIG_SPL_SYS_DISABLE_DCACHE_OPS is added to Kconfig to
On 6/21/23 16:06, Jit Loon Lim wrote:
From: Kah Jing Lee
Dcache feature is not enabled in SPL and enable it will cause ISR
exception
Why would it cause an exception ?
On 6/21/23 16:11, Jit Loon Lim wrote:
From: Teik Heng Chong
The controller registers should not be accessed while the controller's
vcc_reset_n is asserted.
Signed-off-by: Teik Heng Chong
Is this patch ported from Linux or is this custom development ?
Is there a matching patch/fix in Linux
On Wed, 21 Jun 2023 15:06:51 +0100,
Jit Loon Lim wrote:
>
> From: Kah Jing Lee
>
> Dcache feature is not enabled in SPL and enable it will cause ISR
> exception. Since the Dcache is not supported in SPL, new
> CONFIG_SPL_SYS_DISABLE_DCACHE_OPS is added to Kconfig to disable Dcache
> in SPL.
>
From: Teik Heng Chong
The controller registers should not be accessed while the controller's
vcc_reset_n is asserted.
Signed-off-by: Teik Heng Chong
---
drivers/usb/host/xhci-dwc3.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers
From: Kah Jing Lee
Dcache feature is not enabled in SPL and enable it will cause ISR
exception. Since the Dcache is not supported in SPL, new
CONFIG_SPL_SYS_DISABLE_DCACHE_OPS is added to Kconfig to disable Dcache
in SPL.
Signed-off-by: Kah Jing Lee
---
arch/arm/cpu/armv8/cache_v8.c | 20 +
From: Sin Hui Kho
Add MMU mapping region for FPGA including 512 MB LW HPS2FPGA and
1GB HPS2FPGA.
Signed-off-by: Sin Hui Kho
---
arch/arm/mach-socfpga/mmu-arm64_s10.c | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c
b/arch/arm/mach-socfpga/mmu-a
This commit adds driver for iMX93 ADC.
The driver is implemented using driver model and provides
ADC uclass's methods for ADC single channel operations:
- adc_start_channel()
- adc_channel_data()
- adc_stop()
ADC features:
- channels: 4
- resolution: 12-bit
Signed-off-by: Luc
iMX93 ADC features:
- 4 channels
- 12 bit resolution
Signed-off-by: Luca Ellero
---
configs/imx93_11x11_evk_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/imx93_11x11_evk_defconfig
b/configs/imx93_11x11_evk_defconfig
index 89edebc4c6..30ef460c80 100644
--- a/confi
Add ADC support for NXP iMX93
Changes for v2:
- add "static" to functions
- enable ADC in iMX93 EVK
Changes for v3:
- split in 3 commits
- keep dts file in sync with Linux devicetree
- add comments to commits
Changes for v4:
- add imx93_adc_power_down() in imx93_adc_stop()
Changes for v5:
- sim
From: Dinesh Maniyam
Enable APB Timer driver model.
Signed-off-by: Dinesh Maniyam
---
arch/arm/dts/socfpga_agilex5_socdk.dts | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/dts/socfpga_agilex5_socdk.dts
b/arch/arm/dts/socfpga_agilex5_socdk.dts
index 1a39426561..
For some Amlogic SOC's, the mechanism for obtain a random number
has been changed. For example, S4 now uses a status bit wait algo.
Signed-off-by: Alexey Romanov
---
drivers/rng/meson-rng.c | 73 +
1 file changed, 67 insertions(+), 6 deletions(-)
diff --g
From: xiefei
Due to the need to read the register value before
switching to hs mode, the standard protocol does
not explicitly specify that the setting before
switching to hs mode is in legacy mode. Therefore,
the code at this point may cause communication
abnormalities between the host and card
Hello Heinrich,
thank you for you extensive review. I will incorporate
your reviews in a future version of the patch series.
Best Regards
Malte
Am 16.06.2023 um 20:18 schrieb Heinrich Schuchardt:
On 6/16/23 13:34, Stefan Herbrechtsmeier wrote:
From: Malte Schmidt
Thanks for considering whi
On 6/21/23 09:13, Xavier Drudis Ferran wrote:
Commands causing reset in some configs:
When bootflow scan is run, this will cause a UCLASS_BOOTDEV device to
be added as sibling of those UCLASS_BLK devices found in the search
chain defined in environment variable "boot_targets", until boot
su
On 6/21/23 05:13, teik.heng.ch...@intel.com wrote:
From: Teik Heng Chong
Fix the write to the HPRT register which treat W1C fields
as if they were mere RW. This leads to unintended clearing of such fields
This bug was found during the testing on Simics model. Referring to
specification DesignW
During compilation splash_source puts out below warning for type
conversion in splash_load_fit for bmp_load_addr and fit_header.
Change their type to uintptr_t to fix the warnings.
common/splash_source.c: In function ‘splash_load_fit’:
common/splash_source.c:366:22: warning: cast to pointer from i
At the time of compilation evm.c gives below warning for implicit
declaration of enable_caches, to mitigate this include cpu_func.h.
board/ti/am62x/evm.c: In function ‘spl_board_init’:
board/ti/am62x/evm.c:90:9: warning: implicit declaration of function
‘enable_caches’ [-Wimplicit-function-declar
This patch series aims at fixing warnings which occur during
compilation, by including required header files and using appropriate
types for variables which are typecasted.
Changes in V2:
- Type cast bmp_load_addr to uintptr_t at places necessary rather than
changing argument type.
Nikhil M Jai
On Tue, 20 Jun 2023 16:11:48 -0600
Sam Edwards wrote:
Hi Sam,
pleasure to write with you ;-)
> On 6/20/23 06:42, Andre Przywara wrote:
> > So yeah, the request of a "Enter FEL" command came up multiple times, but
> > so far no one could be bothered to implement this properly. The idea would
> >
Set bloblist address to 0x80D0.
Signed-off-by: Nikhil M Jain
Reviewed-by: Devarsh Thakkar
---
V5:
- No change.
V4:
- Remove the link to SPL DDR memory layout and add a new patch.
V3:
- Add link to updated memory map.
V2:
- Add Reviewed-by tag.
configs/am62x_evm_a53_defconfig | 1 +
1 fi
To understand usage of DDR in A53 SPL stage, add a table showing region
and space used by major components of SPL.
Signed-off-by: Nikhil M Jain
---
V5:
- Change the layout of A53 SPL DDR into tabular format.
V4(patch introduced):
- Document A53 SPL DDR memory layout.
doc/board/ti/am62x_sk.rst
This is required since user may want to either call the remove method
of video driver and reset the display or not call the remove method
to continue displaying until next stage.
Signed-off-by: Nikhil M Jain
Reviewed-by: Devarsh Thakkar
Reviewed-by: Tom Rini
---
V5:
- No change.
V4:
- Add Revi
Use config SPL_VIDEO_REMOVE to remove video driver at SPL stage before
jumping to next stage, in place of CONFIG_SPL_VIDEO, to allow user to
remove video if required.
Signed-off-by: Nikhil M Jain
Reviewed-by: Devarsh Thakkar
---
V5:
- No change.
V4:
- No change.
V3:
- Replace #if defined(CONFI
U-boot proper can use frame buffer address passed from SPL to reserve
the memory area used by framebuffer set in SPL so that splash image
set in SPL continues to get displayed while u-boot proper is running.
Put the framebuffer address and size in a bloblist to make them
available at u-boot proper
Add method to reserve video framebuffer information using blob,
received from previous stage.
Signed-off-by: Nikhil M Jain
Reviewed-by: Simon Glass
---
V5:
- No change.
V4:
- No change.
V3:
- Add Reviewed-by tag.
V2:
- Remove #if CONFIG_IS_ENABLED(VIDEO) in video_reserve_from_blob.
drivers/
Use spl_dcache_enable, in place of setup_dram, arch_reserve_mmu to set
up pagetable, initialise DRAM and enable Dcache to avoid multiple
function calls.
Check for CONFIG_SPL_VIDEO in place of CONFIG_SPL_VIDEO_TIDSS to prevent
any build failure in case video config is not defined and video related
In spl_dcache_enable after setting up page table, set gd->relocaddr
pointer to tlb_addr, to get next location to reserve memory. Align
tlb_addr with 64KB address.
Signed-off-by: Nikhil M Jain
Reviewed-by: Devarsh Thakkar
---
V5:
- No change.
V4:
- Add Reviewed-by tag.
V3:
- No change.
V2:
- P
At SPL stage when stack is relocated, the stack pointer needs to be
updated, the stack pointer may point to stack in on chip memory even
though stack is relocated.
Signed-off-by: Nikhil M Jain
Reviewed-by: Tom Rini
---
V5:
- No change.
V4:
- No change.
V3:
- Add Reviewed-by tag.
V2:
- No chan
This patch series aims at updating SPL splashscreen framework for AM62x.
This patch series depends on
https://lore.kernel.org/u-boot/20230504225829.2537050-1-...@chromium.org/
This series:
- Fixes compilation issues in case splash related configs are not
defined in SPL.
- Does page table setup,
Hi,
> -Original Message-
> From: Michal Simek
> Sent: Tuesday, June 20, 2023 3:20 PM
> To: Jassi Brar ; Ilias Apalodimas
>
> Cc: Jose Marinho ; u-boot@lists.denx.de;
> etienne.carri...@linaro.org; tr...@konsulko.com; s...@chromium.org;
> sughosh.g...@linaro.org; xypron.g...@gmx.de; takah
Add the NIC device ID and adjust the PCI bar regions.
Signed-off-by: Minda Chen
---
drivers/net/rtl8169.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
index 34e4cff1e9..963702777c 100644
--- a/drivers/net/rtl8169.c
+++ b/
Add PCIe device rtl8169 net adapter driver support.
Signed-off-by: Minda Chen
---
configs/starfive_visionfive2_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/starfive_visionfive2_defconfig
b/configs/starfive_visionfive2_defconfig
index ffbc4b9476..360160200f 100644
--- a/
Fix rtl8169 descriptor less the DMA min aligned compile warning
for RISC-V SoC platform.
Signed-off-by: Minda Chen
---
drivers/net/rtl8169.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
index dcba51590d..34e4cff1e9 100644
--
StarFive JH7110 uboot support PCIe and using rtl8169 network adapter
PCIe device. But compile warning in rtl8169 driver cause CI test fail.
So commit this patch set to fix it, Also a new device ID to adjust the
PCI bar regions in rtl8169.
The StarFive JH7110 PCIe driver link:
https://patchwork.ozl
Fix make pointer from integer without a cast compile warning.
Signed-off-by: Minda Chen
---
drivers/net/rtl8169.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
index 2276a465e7..dcba51590d 100644
--- a/drivers/net/r
Commands causing reset in some configs:
When bootflow scan is run, this will cause a UCLASS_BOOTDEV device to
be added as sibling of those UCLASS_BLK devices found in the search
chain defined in environment variable "boot_targets", until boot
succeeds from some device. This can happen automat
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