On 5/17/23 11:41 PM, Yanhong Wang wrote:
SPL runs on the L2 LIM, which is 2M in size mapped at 0x800.This
region consists of 16 0x2 sized regions, each one can be used as
either L2 cache way or SRAM (not both).From top to bottom, you have way
0-15.The way 0 is always enabled, so SPL can o
On 5/17/23 11:41 PM, Yanhong Wang wrote:
The per-hart stack,malloc space and global variable 'gd' sits between
__bss_end and L2_LIM_MEM_END.Zeroing this region could overwrite the
hart's stack, and other harts' stacks.If it were to save and restore
`ra` register, then we would crash in function e
On 5/14/23 10:08 PM, Rick Chen wrote:
Hi Bo Gan,
It builds fail as below:
arch/riscv/cpu/start.S:97: Error: illegal operands `li
t0,CONFIG_SYS_INIT_SP_ADDR'
Thanks,
Rick
Hi Rick & Leo,
Please help take a look at v2 of the patch:
https://patchwork.ozlabs.org/project/uboot/patch/1684650044-31
Harts need to use per-hart stack before any function call, even if that
function is a simple one. When the callee uses stack for register save/
restore, especially RA, if nested call, concurrent access by multiple
harts on the same stack will cause data-race.
This patch sets up SP before `board_in
Am 20. Mai 2023 22:55:37 MESZ schrieb Sam Edwards :
>
>Here is a series of patches aimed at improving support for the LLVM
>toolchain (clang, lld, and to a lesser extent, llvm-objcopy) when
>targeting ARM. This toolchain is a cross-compiler "by default" -- a user
>generally should not need to in
On Fri, May 19, 2023 at 03:41:34PM +0300, Roger Quadros wrote:
> Hi Colin,
>
> On 19/05/2023 02:19, Colin Foster wrote:
> > Hi Roger,
> >
> >> Can you please share your spl/u-boot.cfg?
> >
> > Attached
>
> Couple of questions there
>
> 1) CONFIG_MTDPARTS_DEFAULT
> "mtdparts=nandflash:0x2(
Hi,
I'm trying to use ums to access EMMC on our SAMA5D2 board without success.
My board_init(), without adding usba_udc_probe() ums will cause data abort
error:
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_USB_GADGE
The OrangePi R1 Plus LTS is a minor variant of OrangePi R1 Plus with
the on-board NIC chip changed from rtl8211e to yt8531c, and RAM type
changed from DDR4 to LPDDR3.
The device tree is taken from kernel v6.4-rc1.
Signed-off-by: Tianling Shen
---
Changes in v2:
* Rebased upon the latest git HEA
Orange Pi R1 Plus is a Rockchip RK3328 based SBC by Xunlong.
This device is similar to the NanoPi R2S, and has a 16MB
SPI NOR (mx25l12805d). The reset button is changed to
directly reset the power supply, another detail is that
both network ports have independent MAC addresses.
The device tree an
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