On Sat, 4 Mar 2023 at 10:51, Pali Rohár wrote:
> Improve code for checking strapping pins which specifies boot mode source.
>
> Martin, could you test if Clearfog can be still configured into UART
> booting mode via HW switches and if it still works correctly? First
> patch is reverting UART rela
On Sat, 4 Mar 2023 at 10:51, Pali Rohár wrote:
> This allows to merge BOOT_FROM_MMC and BOOT_FROM_MMC_ALT constants to one
> macro. And also allows to extend other BOOT_FROM_* macros for other
> variants.
>
> Signed-off-by: Pali Rohár
> ---
> arch/arm/mach-mvebu/cpu.c | 16
On Sat, 4 Mar 2023 at 10:40, Pali Rohár wrote:
> Boot configuration stored in EXT_CSC register is completely ignored by
> BootROM:
>
> https://lore.kernel.org/u-boot/CAOAjy5SYPPzWKok-BSGYwZwcKOQt_aZPgh6FTbrFd3F=8dm...@mail.gmail.com/
>
> Reflect this eMMC booting in documentation and in the code.
On Sunday 05 March 2023 00:06:05 Martin Rowe wrote:
> On Sat, 4 Mar 2023 at 11:20, Pali Rohár wrote:
>
> > On Saturday 04 March 2023 11:50:34 Pali Rohár wrote:
> > > Disassembling A385 BootROM binary reveal how BootROM interprets strapping
> > > pins for Boot Device Mode. All possible options are
On Sat, 4 Mar 2023 at 11:20, Pali Rohár wrote:
> On Saturday 04 March 2023 11:50:34 Pali Rohár wrote:
> > Disassembling A385 BootROM binary reveal how BootROM interprets strapping
> > pins for Boot Device Mode. All possible options are:
> >
> > 0x00..0x07 -> Parallel NOR
> > 0x08..0x15 -> Paralle
On 3/4/23 15:46, Michal Suchánek wrote:
On Sat, Mar 04, 2023 at 01:58:17PM -0600, Samuel Holland wrote:
On 2/20/23 04:39, Michal Suchánek wrote:
On Sun, Feb 19, 2023 at 11:59:36PM -0600, Samuel Holland wrote:
Do not return both NULL and error pointers. The function is only
documented as return
On Sat, Mar 04, 2023 at 01:58:17PM -0600, Samuel Holland wrote:
> On 2/20/23 04:39, Michal Suchánek wrote:
> > On Sun, Feb 19, 2023 at 11:59:36PM -0600, Samuel Holland wrote:
> >> Do not return both NULL and error pointers. The function is only
> >> documented as returning error pointers.
> >>
> >>
On Sat, Mar 04, 2023 at 01:54:12PM -0600, Samuel Holland wrote:
> On 2/20/23 13:42, Michal Suchánek wrote:
> > On Mon, Feb 20, 2023 at 10:57:17AM -0500, Sean Anderson wrote:
> >>
> >> On 2/20/23 05:46, Michal Suchánek wrote:
> >>> On Sun, Feb 19, 2023 at 11:59:34PM -0600, Samuel Holland wrote:
> >>
On 2/20/23 10:11, Sean Anderson wrote:
> On 2/20/23 00:59, Samuel Holland wrote:
>> clk_get_rate() can return an error value. Recompute the rate if the
>> cached value is an error value.
>>
>> Fixes: 4aa78300a025 ("dm: clk: Define clk_get_parent_rate() for clk
>> operations")
>> Signed-off-by: Samu
On 2/20/23 04:39, Michal Suchánek wrote:
> On Sun, Feb 19, 2023 at 11:59:36PM -0600, Samuel Holland wrote:
>> Do not return both NULL and error pointers. The function is only
>> documented as returning error pointers.
>>
>> Fixes: 8a1661f20e6c ("drivers: clk: Handle gracefully NULL pointers")
>> Si
On 2/20/23 13:42, Michal Suchánek wrote:
> On Mon, Feb 20, 2023 at 10:57:17AM -0500, Sean Anderson wrote:
>>
>> On 2/20/23 05:46, Michal Suchánek wrote:
>>> On Sun, Feb 19, 2023 at 11:59:34PM -0600, Samuel Holland wrote:
Some clk uclass functions, such as devm_clk_get() and clk_get_parent(),
>
On Fri, Mar 03, 2023 at 11:31:22PM +0100, Heinrich Schuchardt wrote:
> Kconfig settings that are related to the API for standalone applications
> should be in the API sub-menu and not on the top level.
>
> CONFIG_STANDALONE_LOAD_ADDR is only relevant if standalone example
> applications are built
On Wed, Feb 22, 2023 at 09:33:41AM -0700, Simon Glass wrote:
> This series was split out of the old 'split config' splc series. It
> contains clean-up patches which do not depend on split config.
>
> This is available at u-boot-dm/spld-working
>
> The size changes look pretty good: https://paste
DDR code does not use seq_exec.h, so remove it.
Signed-off-by: Pali Rohár
---
drivers/ddr/marvell/a38x/ddr3_init.h | 1 -
drivers/ddr/marvell/a38x/seq_exec.h | 64
2 files changed, 65 deletions(-)
delete mode 100644 drivers/ddr/marvell/a38x/seq_exec.h
diff --git
On Saturday 04 March 2023 11:50:34 Pali Rohár wrote:
> Disassembling A385 BootROM binary reveal how BootROM interprets strapping
> pins for Boot Device Mode. All possible options are:
>
> 0x00..0x07 -> Parallel NOR
> 0x08..0x15 -> Parallel NAND
> 0x16..0x17 -> Parallel NOR
> 0x18..0x25 -> Parallel
Definitions are according to the MV78460 Hardware Specifications.
Signed-off-by: Pali Rohár
---
arch/arm/mach-mvebu/include/mach/soc.h | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h
b/arch/arm/mach-mvebu/include/mach/soc.h
index 75fe785932c2..49b4
Disassembling A385 BootROM binary reveal how BootROM interprets strapping
pins for Boot Device Mode. All possible options are:
0x00..0x07 -> Parallel NOR
0x08..0x15 -> Parallel NAND
0x16..0x17 -> Parallel NOR
0x18..0x25 -> Parallel NAND
0x26..0x27 -> SPI NAND
0x28..0x29 -> UART xmodem
0x2a..0x2b -
A385 BootROM fills into bits [31:28] of register 0x182d0 tracing value,
which represents in which state BootROM currently is. BootROM fills one
of the possible values: 0x2 (CPU initialization), 0x3 (UART detection),
0x6 (UART booting), 0x8 (PCI Express booting), 0x9 (parallel or SPI NOR
booting), 0
This allows to merge BOOT_FROM_MMC and BOOT_FROM_MMC_ALT constants to one
macro. And also allows to extend other BOOT_FROM_* macros for other
variants.
Signed-off-by: Pali Rohár
---
arch/arm/mach-mvebu/cpu.c | 16 +---
arch/arm/mach-mvebu/include/mach/soc.h | 25
A385 BootROM treats strapping configuration 0x22 as SPI-NAND. So remove
incorrect definition 0x22 as SATA. SATA on A385 has configuration 0x2A.
Signed-off-by: Pali Rohár
---
arch/arm/mach-mvebu/cpu.c | 1 -
arch/arm/mach-mvebu/include/mach/soc.h | 3 +--
2 files changed, 1 insertion
Improve code for checking strapping pins which specifies boot mode source.
Martin, could you test if Clearfog can be still configured into UART
booting mode via HW switches and if it still works correctly? First
patch is reverting UART related commit for Clearfog which I think it not
needed anymor
A385 BootROM treats strapping configuration 0x3f as invalid. When booting
fails (e.g. because of invalid configuration) then BootROM fallbacks to
UART booting.
Detecting BootROM fallback to UART booting is implemented in U-Boot since
commit 2fd4284051e3 ("ARM: mach-mvebu: handle fall-back to UART
Show correct information in debug() output and use correct names for variables.
No functional change.
Signed-off-by: Pali Rohár
---
arch/arm/mach-mvebu/cpu.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
i
Boot configuration stored in EXT_CSC register is completely ignored by
BootROM. So we should skip it too in SPL, to load proper U-Boot from the
same location as from which was loaded SPL by BootROM.
BootROM tries to boot from partitions in this order: Boot 0, Boot 1, User
Data Partition.
In case
Boot configuration stored in EXT_CSC register is completely ignored by BootROM:
https://lore.kernel.org/u-boot/CAOAjy5SYPPzWKok-BSGYwZwcKOQt_aZPgh6FTbrFd3F=8dm...@mail.gmail.com/
Reflect this eMMC booting in documentation and in the code.
Martin, can you test this patch series if SPL and main U-B
Boot configuration stored in EXT_CSC register is completely ignored by BootROM.
Fixes: fa03279e198d ("tools: kwboot: Add image type documentation")
Signed-off-by: Pali Rohár
---
tools/kwboot.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/tools/kwboot.c b/tools/kwboot
Ping again? Or silence means no care from CZ.NIC side?
On Tuesday 31 January 2023 19:53:23 Pali Rohár wrote:
> Gentle ping? Does CZ.NIC care about Turris routers and u-boot support?
>
> On Monday 07 November 2022 21:28:31 Pali Rohár wrote:
> > Hello! Just beware of these two commits which renamed
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