On 5/5/22 7:33 PM, Andre Przywara wrote:
> The introduction of the DM pinctrl driver made its probe function enable
> all clocks enumerated in the DT. This includes the "CLK_BUS_PIO" (and
> variations) gate clock, but also CLK_PLL_PERIPH0. So far we didn't
I believe the use of CLK_PLL_PERIPH0 is f
On 5/6/22 15:03, Tom Rini wrote:
On Fri, May 06, 2022 at 11:23:12AM -0700, William Zhang wrote:
This is the initial support for Broadcom's ARM-based 47622 SOC.
In this change, our first SOC is an armv7 platform called 47622. The
initial support includes a bare-bone implementation and dts with
On Fri, May 06, 2022 at 11:23:12AM -0700, William Zhang wrote:
> This is the initial support for Broadcom's ARM-based 47622 SOC.
>
> In this change, our first SOC is an armv7 platform called 47622. The
> initial support includes a bare-bone implementation and dts with ARM
> PL011 uart.
>
> The S
Currently, the adin driver fails to compile.
The original patch introducing the adin driver used the function
phy_get_interface_by_name to support the adi,phy-mode-override
property. Unfortunately, a few days before the adin patch
was accepted, another patch removed support for phy_get_interface_b
This is the initial support for Broadcom's ARM-based 47622 SOC.
In this change, our first SOC is an armv7 platform called 47622. The
initial support includes a bare-bone implementation and dts with ARM
PL011 uart.
The SOC-specific code resides in arch/arm/mach-bcmbca/ and board
related code is in
This change introduces Broadcom's ARCH_BCMBCA architecture for armv7
and armv8 based Broadband SoCs. We expect to send additional patches
for each SoC in the near future.
Changes in v2:
- Updated dts and dtsi files which are accpeted in linux-next upstream
- Changed CONFIG_SYS_TEXT_BASE to 0x01000
Am 6. Mai 2022 20:10:58 MESZ schrieb Mark Kettenis :
>> Date: Fri, 6 May 2022 19:30:51 +0200
>> From: Heinrich Schuchardt
>>
>> On 4/30/22 14:49, Heinrich Schuchardt wrote:
>> > On 4/29/22 12:56, Heinrich Schuchardt wrote:
>> >> On 4/28/22 18:33, Heinrich Schuchardt wrote:
>> >>> On 4/28/22 10
> Date: Fri, 6 May 2022 19:30:51 +0200
> From: Heinrich Schuchardt
>
> On 4/30/22 14:49, Heinrich Schuchardt wrote:
> > On 4/29/22 12:56, Heinrich Schuchardt wrote:
> >> On 4/28/22 18:33, Heinrich Schuchardt wrote:
> >>> On 4/28/22 10:09, Masahisa Kojima wrote:
> This commit supports the men
Methode eDPU is an Armada 3720 power board based on the Methode uDPU.
They feature the same CPU, RAM, and storage as well as the form factor.
However, eDPU only has one SFP slot plus a copper G.hn port which does not
work under U-boot.
In order to reduce duplication, split the uDPU DTS into a co
Currently, pinctrl drivers only get probed if pinconf is actually being
used, however on SoC-s like Armada 3720 pinctrl driver is a also the GPIO
driver.
So, if the pinctrl driver doesn't get probed GPIO-s won't get registered
and thus they cannot be used.
This is a problem on the Methode eDPU as
On 4/30/22 14:49, Heinrich Schuchardt wrote:
On 4/29/22 12:56, Heinrich Schuchardt wrote:
On 4/28/22 18:33, Heinrich Schuchardt wrote:
On 4/28/22 10:09, Masahisa Kojima wrote:
This commit supports the menu-driven UEFI boot option addition.
User can select the block device volume having
efi_sim
On 5/6/22 16:50, Jan Kiszka wrote:
From: Jan Kiszka
Before clearing the screen, ensure that no previous output of firmware
or UEFI programs will be overwritten on serial devices or other
streaming consoles. This helps generating complete boot logs.
Tested regarding multi-output against qemu-x8
On 5/6/22 14:36, Ilias Apalodimas wrote:
Currently we don't support sha384/512 for the X.509 certificate
in dbx. Moreover if we come across such a hash we skip the check
and approve the image, although the image might needs to be rejected.
Rework the code a bit and fix it by adding an array of
On 5/6/22 12:18 PM, Tom Rini wrote:
> On Thu, May 05, 2022 at 04:16:54PM -0400, Sean Anderson wrote:
>> This converts the spi load method to use spl_load. As a consequence, it
>
>> also adds support for LOAD_FIT_FULL.
>>
>> Signed-off-by: Sean Anderson
>> Reviewed-by: Stefan Roese
>
> I had
On Thu, May 05, 2022 at 04:16:51PM -0400, Sean Anderson wrote:
> This converts the net load method to use spl_load. As a result, it also
> adds support for LOAD_FIT_FULL and IMX images.
>
> Signed-off-by: Sean Anderson
> Reviewed-by: Stefan Roese
Given my previous hardware problems testing SPI
On Thu, May 05, 2022 at 04:16:50PM -0400, Sean Anderson wrote:
> This converts the mmc loader to spl_load. Legacy images are handled by
> spl_load (via spl_parse_image_header), so mmc_load_legacy can be
> omitted.
>
> Signed-off-by: Sean Anderson
> Reviewed-by: Stefan Roese
On mx6cuboxi, pine_
On Thu, May 05, 2022 at 04:16:54PM -0400, Sean Anderson wrote:
> This converts the spi load method to use spl_load. As a consequence, it
> also adds support for LOAD_FIT_FULL.
>
> Signed-off-by: Sean Anderson
> Reviewed-by: Stefan Roese
I had hoped to test this, but I can't convince the platfo
On Thu, May 05, 2022 at 04:16:49PM -0400, Sean Anderson wrote:
> This converts the fat loader to use spl_load.
>
> Signed-off-by: Sean Anderson
> Reviewed-by: Stefan Roese
On omap2plus and rpi:
Tested-by: Tom Rini
--
Tom
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On Fri, May 06, 2022 at 01:42:48PM +0200, Marek Vasut wrote:
> The following changes since commit 03b873b4f41010e4f85a72dd59016bb0b123dde1:
>
> Merge branch '2022-05-05-assorted-cleanups-and-fixes' (2022-05-05 19:37:22
> -0400)
>
> are available in the Git repository at:
>
> git://source.de
On Fri, May 06, 2022 at 12:55:19PM +0200, Stefan Roese wrote:
> Hi Tom,
>
> please pull the following watchdog related patch:
>
Applied to u-boot/master, thanks!
--
Tom
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Hello Peng,
just a gentle ping -- did you already had a chance to check the mentioned
parameter of event 0x82?
Thanks in advance.
Best regards,
Fedor
On Thu, Apr 14, 2022 at 8:00 PM Fedor Ross wrote:
>
> Hello Peng,
>
> can you please check the parameter of event 0x82 internally? The AN12853
>
On Fri, 6 May 2022 13:28:52 +0200
Heinrich Schuchardt wrote:
Hi,
> Building with OpenSSL 3.0 produces warnings like:
>
> ../tools/sunxi_toc0.c:846:17: warning: ‘RSA_get0_d’ is deprecated:
> Since OpenSSL 3.0 [-Wdeprecated-declarations]
> 846 | if (root_key && RSA_get0_d(root_
From: Jan Kiszka
Before clearing the screen, ensure that no previous output of firmware
or UEFI programs will be overwritten on serial devices or other
streaming consoles. This helps generating complete boot logs.
Tested regarding multi-output against qemu-x86_defconfig.
Signed-off-by: Jan Kisz
Hi
Thank you. What is the reply from bootrom team?
Michael
On Fri, May 6, 2022 at 4:41 PM Han Xu wrote:
>
> On 22/04/27 07:50AM, Michael Trimarchi wrote:
> > The specific implementation was having bug. Those bugs are since
> > the beginning of the implementation. Some manufactures can receive
>
On 22/04/27 07:50AM, Michael Trimarchi wrote:
> If the fitImage has some bad block in fit image area, the
> offset must be recalulcated. This should be done always.
> After implementing it in mxs now is possible to call the function
> even for that platform.
>
> Cc: Fabio Estevam
> Signed-off-by:
On 22/04/27 07:50AM, Michael Trimarchi wrote:
> The badblock should be skipped properly in reading and writing.
> Fix the logic. The bcb struct is written, skipping the bad block,
> so we need to read using the same logic. This was tested create
> bad block in the area and then flash it and read it
On 22/04/27 07:50AM, Michael Trimarchi wrote:
> The specific implementation was having bug. Those bugs are since
> the beginning of the implementation. Some manufactures can receive
> this bug in their SPL code. This bug start to be more visible on
> architecture that has complicated boot process l
On 22/04/27 07:50AM, Michael Trimarchi wrote:
> Move the hook after nand_scan_tail is called. The hook must be replaced
> to the mxs specific one but those must to be assignment later in the
> probe function.
>
> With this fix markbad is working again. Before this change:
>
> nand markbad 0xDEC00
Hi Patrick
On 5/5/22 14:21, Patrick Delaunay wrote:
> Long TFTP transfers lead to a wall of # characters on UART, which in
> the end may slow down the transfer itself. Use CONFIG_TFTP_TSIZE to
> print progress in fewer # characters.
>
> Signed-off-by: Patrick Delaunay
> ---
>
> configs/stm32mp
Hi Patrick
On 4/26/22 15:38, Patrick Delaunay wrote:
> Device tree alignment with Linux kernel v5.18-rc2:
> - ARM: dts: stm32: Add support for the emtrion emSBC-Argon
> (only the pincontrol part)
> - ARM: dts: stm32: Drop duplicate status okay from DHCOM gpioc node
> - ARM: dts: stm32: add st,st
Hi Patrick
On 4/26/22 14:37, Patrick Delaunay wrote:
> Handle the input clock of RCC USB_PHY_48, provided by USBPHYC
> and named "ck_usbo_48m".
>
> Signed-off-by: Patrick Delaunay
> ---
>
> drivers/clk/clk_stm32mp1.c | 35 ---
> 1 file changed, 20 insertions(+),
Hi Patrick
On 4/26/22 14:37, Patrick Delaunay wrote:
> ck_usbo_48m is generated by usbphyc PLL and used by OTG controller
> for Full-Speed use cases with dedicated Full-Speed transceiver.
>
> ck_usbo_48m is available as soon as the PLL is enabled.
>
> Signed-off-by: Patrick Delaunay
> ---
>
>
Hi Patrick
On 4/26/22 14:37, Patrick Delaunay wrote:
> Add the counter of the PLL user n_pll_cons managed by the 2 functions
> stm32_usbphyc_pll_enable / stm32_usbphyc_pll_disable.
>
> This counter allow to remove the function stm32_usbphyc_is_init
> and it is a preliminary step for ck_usbo_48m i
Add in U-Boot documentation the quick instruction for
setup the STMicroelectronics STM32MP13x boards.
Signed-off-by: Patrick Delaunay
---
doc/board/st/stm32mp1.rst | 181 ++
1 file changed, 125 insertions(+), 56 deletions(-)
diff --git a/doc/board/st/stm32mp
Add a initial config for STM32M13x SOC family, using the stm32mp135f-dk
device tree.
Signed-off-by: Patrick Delaunay
---
board/st/stm32mp1/MAINTAINERS | 1 +
configs/stm32mp13_defconfig | 54 +++
2 files changed, 55 insertions(+)
create mode 100644 configs/st
Compile the device tree of STM32MP13x boards and add the needed
U-Boot add-on.
Signed-off-by: Patrick Delaunay
---
arch/arm/dts/Makefile | 3 +
arch/arm/dts/stm32mp13-u-boot.dtsi | 91 +
arch/arm/dts/stm32mp135f-dk-u-boot.dtsi | 30
3 fil
Add support for new compatible "st,stm32mp13-ddr" to manage the
DDR sub system (Controller and PHY) in STM32MP13x SOC:
- only one AXI port
- support of 16 port output (MEMC_DRAM_DATA_WIDTH = 2)
The STM32MP15x SOC have 2 AXI ports and 32 bits support.
Signed-off-by: Patrick Delaunay
---
.../mem
Although not recommended, the reset property could be made optional.
This way the driver will probe even if no reset property is provided
in an sdmmc node in DT. This reset is already optional in Linux.
Signed-off-by: Yann Gautier
Signed-off-by: Patrick Delaunay
---
drivers/mmc/stm32_sdmmc2.c
Add stm32mp15x prefix to all STM32MP15x board specific function,
this patch is a preliminary step for STM32MP13x support.
This patch also add the RCC probe to avoid circular access with
usbphyc probe as clk provider.
Signed-off-by: Patrick Delaunay
---
board/st/stm32mp1/stm32mp1.c | 27 +++
Add support for "st,stm32mp135-pinctrl" for STM32MP13x
Signed-off-by: Patrick Delaunay
---
drivers/pinctrl/pinctrl_stm32.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c
index 5729799b12..b100e56044 100644
--- a/drivers/pinc
Introduce the code in mach-stm32mp and the configuration file
stm32mp13_defconfig for the new STM32MP family.
Signed-off-by: Patrick Delaunay
---
arch/arm/mach-stm32mp/Kconfig | 21 +++-
arch/arm/mach-stm32mp/Kconfig.13x | 57 +
arch/arm/mach-stm32mp/Makefi
Add support of several MAC address in OTP (3 32bits OTP word for
2 MAC address) for SOCs in STM32MP13x family: STM32MP133 and STM32MP135.
Signed-off-by: Patrick Delaunay
---
arch/arm/mach-stm32mp/cpu.c | 41 ---
.../arm/mach-stm32mp/include/mach/sys_proto.h |
Add config CONFIG_STM32MP15_PWR to handle the
access on regulators managed by the PWR driver defined in
pwr_regulator.c
This driver is only used in U-Boot by STM32MP15x family.
Signed-off-by: Patrick Delaunay
---
arch/arm/mach-stm32mp/Kconfig.15x | 16
arch/arm/mach-stm32mp/Ma
Add sub Kconfig for each SOC in the STM32 CPU family.
It is a preliminary step to introduce a new SOC in the STM32MP family.
Signed-off-by: Patrick Delaunay
---
arch/arm/mach-stm32mp/Kconfig | 119 +---
arch/arm/mach-stm32mp/Kconfig.15x | 119 +++
Add mandatory choice for SOC support in ARCH_STM32MP.
This patch is a preliminary step for new SOC introduction
in STM32MP family.
Signed-off-by: Patrick Delaunay
---
arch/arm/mach-stm32mp/Kconfig | 23 +--
configs/stm32mp15_basic_defconfig | 4 ++--
configs/stm32m
Move code and defines only needed for CONFIG_STM32MP15x in stm32mp15x.c
when low level init without TFABOOT is supported.
Signed-off-by: Patrick Delaunay
---
arch/arm/mach-stm32mp/Makefile| 2 +
arch/arm/mach-stm32mp/cpu.c | 331 +
arch/arm/ma
As the get_otp() helper function in bsec are common for all STM32MP family,
move this function in bsec driver
Signed-off-by: Patrick Delaunay
---
arch/arm/mach-stm32mp/bsec.c | 17 +
arch/arm/mach-stm32mp/cpu.c| 17 -
arch/ar
Add the minimal support of the new STM32MP13x in mach-stm32mp
to allow boot from SD Card.
STM32MP13x is a single Cortex-A7 MPU aimed at various applications.
The discovery board is supported with stm32mp13_defconfig and the
device tree stm32mp135f-dk.dts.
The supported boot sequence is:
- TF-A
The SPL is only supported by STM32MP15x not by all the
SOC with STM32MP arch.
Only TFABOOT is supported in next products.
Signed-off-by: Patrick Delaunay
Signed-off-by: Patrick Delaunay
---
arch/arm/Kconfig | 1 -
arch/arm/mach-stm32mp/Kconfig | 1 +
2 files changed, 1 insertion(+
Add initial support of STM32MP13 family based on v5.18-rc2
Signed-off-by: Patrick Delaunay
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 123 ++
arch/arm/dts/stm32mp131.dtsi| 358
arch/arm/dts/stm32mp133.dtsi| 37 +++
arch/arm/dts/stm32mp135.dts
Initial commit of Librem5 u-boot and SPL
Signed-off-by: Angus Ainslie
Co-developed-by: Sebastian Krzyszkowiak
Signed-off-by: Sebastian Krzyszkowiak
---
All of the pre-requisite patches for this board are now upstream or in review.
Changes since v4:
Include imx8mq-u-boot.dtsi instead of addin
uDPU relies on using fixed-phy for the SFP support, and since the
fixed-phy parsing was moved to the generic driver instead of mvneta
networking stopped working on uDPU with:
uDPU>> dhcp
dm_eth_phy_connect failed
This is due to the conversion commit not enabling fixed-phy support
in defconfig like
On Friday 06 May 2022 14:35:55 Stefan Roese wrote:
> On 06.05.22 14:16, Stefan Roese wrote:
> > On 06.05.22 14:09, Pali Rohár wrote:
> > > On Friday 06 May 2022 14:04:53 Stefan Roese wrote:
> > > > On 06.05.22 11:05, Pali Rohár wrote:
> > > > > Moving of internal registers from INTREG_BASE_ADDR_REG
Currently we don't support sha384/512 for the X.509 certificate
in dbx. Moreover if we come across such a hash we skip the check
and approve the image, although the image might needs to be rejected.
Rework the code a bit and fix it by adding an array of structs with the
supported GUIDs, len and
The previous patch adds support for rejecting images when the sha384/512
of an x.509 certificate is present in dbx. Update the sandbox selftests
Signed-off-by: Ilias Apalodimas
---
changes since v3:
- move sha384/512 testing to a different fucntion
changes since v2:
- None
changes since RFC:
- n
On 06.05.22 14:16, Stefan Roese wrote:
On 06.05.22 14:09, Pali Rohár wrote:
On Friday 06 May 2022 14:04:53 Stefan Roese wrote:
On 06.05.22 11:05, Pali Rohár wrote:
Moving of internal registers from INTREG_BASE_ADDR_REG to
SOC_REGS_PHY_BASE
needs to be done very early, prior calling any functi
On Friday 06 May 2022 14:21:02 Stefan Roese wrote:
> On 06.05.22 11:05, Pali Rohár wrote:
> > Internal registers in SPL are at address 0xd000 and in proper U-Boot at
> > address 0xf100. UART base address is located in internal registers.
> >
> > Fix DEBUG_UART_BASE option to correct value
On 06.05.22 13:54, Robert Marko wrote:
uDPU relies on using fixed-phy for the SFP support, and since the
fixed-phy parsing was moved to the generic driver instead of mvneta
networking stopped working on uDPU with:
uDPU>> dhcp
dm_eth_phy_connect failed
This is due to the conversion commit not ena
On 06.05.22 11:05, Pali Rohár wrote:
Internal registers in SPL are at address 0xd000 and in proper U-Boot at
address 0xf100. UART base address is located in internal registers.
Fix DEBUG_UART_BASE option to correct value for both SPL and proper U-Boot.
This change fixes hangup of proper
On 06.05.22 14:09, Pali Rohár wrote:
On Friday 06 May 2022 14:04:53 Stefan Roese wrote:
On 06.05.22 11:05, Pali Rohár wrote:
Moving of internal registers from INTREG_BASE_ADDR_REG to SOC_REGS_PHY_BASE
needs to be done very early, prior calling any function which may touch
internal registers, li
On Friday 06 May 2022 14:04:53 Stefan Roese wrote:
> On 06.05.22 11:05, Pali Rohár wrote:
> > Moving of internal registers from INTREG_BASE_ADDR_REG to SOC_REGS_PHY_BASE
> > needs to be done very early, prior calling any function which may touch
> > internal registers, like debug_uart_init().
> >
On 06.05.22 11:05, Pali Rohár wrote:
Moving of internal registers from INTREG_BASE_ADDR_REG to SOC_REGS_PHY_BASE
needs to be done very early, prior calling any function which may touch
internal registers, like debug_uart_init().
So do it earlier in arch_very_early_init() instead of arch_cpu_init
Hello Rafał,
On 05.05.22 07:46, Rafał Miłecki wrote:
> On 4.05.2022 11:23, Ahmad Fatoum wrote:
>> Hello Rafał,
>>
>> On 03.05.22 18:56, Rafał Miłecki wrote:
>>> From: Rafał Miłecki
>>>
>>> U-Boot stores its setup as environment variables. It's a list of
>>> key-value pairs stored on flash device
uDPU relies on using fixed-phy for the SFP support, and since the
fixed-phy parsing was moved to the generic driver instead of mvneta
networking stopped working on uDPU with:
uDPU>> dhcp
dm_eth_phy_connect failed
This is due to the conversion commit not enabling fixed-phy support
in defconfig like
The following changes since commit 03b873b4f41010e4f85a72dd59016bb0b123dde1:
Merge branch '2022-05-05-assorted-cleanups-and-fixes' (2022-05-05
19:37:22 -0400)
are available in the Git repository at:
git://source.denx.de/u-boot-usb.git master
for you to fetch changes up to 6aa8bde8786d7bd
Building with OpenSSL 3.0 produces warnings like:
../tools/sunxi_toc0.c:846:17: warning: ‘RSA_get0_d’ is deprecated:
Since OpenSSL 3.0 [-Wdeprecated-declarations]
846 | if (root_key && RSA_get0_d(root_key)) {
| ^~
As OpenSSL 3.0 is not available in elder Li
On 02.05.22 18:41, Pali Rohár wrote:
MAX6370 watchdog is available e.g. on Freescale P1/P2 RDB-PC boards.
Signed-off-by: Pali Rohár
Applied to u-boot-watchdog/master
Thanks,
Stefan
---
drivers/watchdog/Kconfig | 7 ++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/max
Schema file in YAML must be provided in board/ti/common for validating
input config files and packaging system firmware. The schema includes
entries for rm-cfg, board-cfg, pm-cfg and sec-cfg.
Board config file must be provided in board/ti/ in YAML.
These can then be consumed for generation of bina
Hi Tom,
please pull the following watchdog related patch:
- Add MAX6370 watchdog timer driver (Pali)
Here the Azure build, without any issues:
https://dev.azure.com
On Friday 06 May 2022 18:32:18 Jaehoon Chung wrote:
> On 4/30/22 03:27, Pali Rohár wrote:
> > Only newer eSDHC controllers set PRSSTAT_SDSTB flag. So do not wait until
> > flag PRSSTAT_SDSTB is set on old pre-2.2 controllers. Instead sleep for
> > fixed amount of time like it was before commit 6f88
On 4/30/22 03:27, Pali Rohár wrote:
> Only newer eSDHC controllers set PRSSTAT_SDSTB flag. So do not wait until
> flag PRSSTAT_SDSTB is set on old pre-2.2 controllers. Instead sleep for
> fixed amount of time like it was before commit 6f883e501b65 ("mmc:
> fsl_esdhc: Add emmc hs200 support").
>
>
On 4/27/22 17:27, Michal Simek wrote:
> From: T Karthik Reddy
>
> zynqmp_pm_is_function_supported() which checks feature support on som,
> which is implemented in firmware_zynqmp.c driver. As mini configuration
> does not use firmware driver, so create a weak function to avoid
> compilation error
Moving of internal registers from INTREG_BASE_ADDR_REG to SOC_REGS_PHY_BASE
needs to be done very early, prior calling any function which may touch
internal registers, like debug_uart_init().
So do it earlier in arch_very_early_init() instead of arch_cpu_init().
Movement is done in proper U-Boot,
Use CONFIG_VAL(DEBUG_UART_BASE) instead of CONFIG_DEBUG_UART_BASE, so
proper config value (CONFIG_DEBUG_UART_BASE or CONFIG_SPL_DEBUG_UART_BASE)
is used based on building target.
Signed-off-by: Pali Rohár
---
drivers/serial/ns16550.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
dif
SPL_DEBUG_UART_BASE is same as DEBUG_UART_BASE, but applies only for SPL.
In some cases base address of UART is different in SPL and proper U-Boot.
Signed-off-by: Pali Rohár
---
drivers/serial/Kconfig | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/serial/Kconfig b/drivers/se
Internal registers in SPL are at address 0xd000 and in proper U-Boot at
address 0xf100. UART base address is located in internal registers.
Fix DEBUG_UART_BASE option to correct value for both SPL and proper U-Boot.
This change fixes hangup of proper U-Boot when it is trying to print
some
When this option is set then ARM _main() function would call
arch_very_early_init() function at the beginning. It would be before
calling any other functions like debug_uart_init() and also before
initializing C runtime environment.
Signed-off-by: Pali Rohár
---
arch/arm/Kconfig| 6 ++
a
If proper U-Boot on Turris Omnia tries to print something on debug UART
then CPU hangs. Reason is that debug UART in proper U-Boot for Turris
Omnia has incorrect configuration of base register. Base register is
different in SPL and also in different stages of proper U-Boot.
Fix all these issues. I
Hi,
On 4/22/22 09:39, Patrice Chotard wrote:
Always consider USB cable is connected when USB boot device is detected.
Signed-off-by: Patrice Chotard
---
board/st/stm32mp1/stm32mp1.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/
Hi
On 4/22/22 09:39, Patrice Chotard wrote:
Add support of phy-tuning properties for sm32-usbphyc's phy tuning
aligned with v5.15 kernel bindings.
Signed-off-by: Patrice Chotard
---
drivers/phy/phy-stm32-usbphyc.c | 167
1 file changed, 167 insertions(+)
Hi,
On 4/27/22 13:54, Patrice Chotard wrote:
Add documentation for STM32 MCUs (F4, F7 and H7 series).
Signed-off-by: Patrice Chotard
---
Changes in v2:
- fix documentation file stm32_MCU.rst
board/st/stm32f429-discovery/MAINTAINERS | 1 +
board/st/stm32f429-evaluation/MAINTAINERS
Hi,
On 5/6/22 08:22, Patrice Chotard wrote:
Since commit 16cc5ad0b439 ("power: regulator: add dummy helper")
regulator dummy helper are always available even if DM_REGULATOR
is not set.
DM_REGULATOR flag is no more needed to protect no DM core,
remove it.
Signed-off-by: Patrice Chotard
---
Ch
Hi,
On 5/6/22 08:22, Patrice Chotard wrote:
Make usage of clock and reset bulk API in order to simplify the code
Signed-off-by: Patrice Chotard
---
Changes in v2:
- add the error code in all dev_err() output.
drivers/usb/host/ehci-generic.c | 103 ++--
1 fil
Hi,
On 5/4/22 14:50, Marek Vasut wrote:
The Buck3 on DHCOR is used to supply IO voltage. It can output either 3V3
in the default DHCOR configuration, or 2V9 in case of AV96 DHCOR variant
which has extra Empirion DCDC converter in front of the 1V8 IO supply, or
outright 1V8 in case of 1V8 IO DHCO
Hi,
On 4/22/22 09:38, Patrice Chotard wrote:
On some STM32 SoC's package, GPIO bank may have hole in their GPIO bank
Example:
If GPIO bank have 16 GPIO pins [0-15].
In particular SoC's package case, some GPIO bank can have less GPIO pins:
- [0-10] => 11 pins;
- [2-7] => 6 pins.
Hi,
On 4/22/22 09:38, Patrice Chotard wrote:
GPIOF_UNKNOWN becomes a valid pin muxing information to indicate
that a pin is not mapped.
Signed-off-by: Patrice Chotard
---
drivers/pinctrl/pinctrl_stm32.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/pinctrl/pinctrl_stm32.c b/
Hi,
On 4/22/22 09:38, Patrice Chotard wrote:
pinmux_mode[] is linked to gpio_function[] defined in gpio-uclass.c
So reuse the same gpio_func_t enum value
Signed-off-by: Patrice Chotard
---
drivers/pinctrl/pinctrl_stm32.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
Hi Han
Any update?
Michael
On Tue, May 3, 2022 at 7:14 AM Michael Nazzareno Trimarchi
wrote:
>
> Hi Han
>
> On Mon, May 2, 2022 at 11:32 PM Han Xu wrote:
> >
> > On 22/05/01 08:36AM, Michael Nazzareno Trimarchi wrote:
> > > Dear Han and Fabio
> > >
> > > On Thu, Apr 28, 2022 at 7:01 AM Michael
On Thu, 5 May 2022 23:53:45 -0600, Ashok Reddy Soma wrote:
> Add support to switch to EL1 and load an EL1 app from U-Boot which is
> executing at EL2 or EL3 in aarch64 mode.
>
>
Applied, thanks!
[1/1] arm64: versal: Add support to load an app at EL1
https://source.denx.de/u-boot/custodia
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