On Fri, Jun 25, 2021 at 11:51:51PM +0200, Pali Rohár wrote:
> On Friday 25 June 2021 17:37:44 Tom Rini wrote:
> > One thing I want to say here as I think it maybe wasn't clear in Marek's
> > suggestion. Why not have X-Loader boot SPL which loads U-Boot from extN
> > on the eMMC?
>
> Hello Tom! I
On Friday 25 June 2021 17:37:44 Tom Rini wrote:
> One thing I want to say here as I think it maybe wasn't clear in Marek's
> suggestion. Why not have X-Loader boot SPL which loads U-Boot from extN
> on the eMMC?
Hello Tom! I have already answered this in my previous email.
On Sat, Jun 26, 2021 at 12:31:49AM +0300, Ivaylo Dimitrov wrote:
[snip]
> In regards to SPL - there is no way to sign SPL with the keys used by Nokia
> to sign NOLO(the proprietary second stage loader), we simply don't have
> them. Without that, we can't replace NOLO.
One thing I want to say here
On 25.06.21 г. 19:04 ч., Simon Glass wrote:
Hi Pali,
On Fri, 25 Jun 2021 at 07:07, Pali Rohár wrote:
On Friday 25 June 2021 08:38:47 Tom Rini wrote:
On Sun, Jun 20, 2021 at 09:43:43PM +0200, Marek Vasut wrote:
On 6/20/21 5:54 PM, Tom Rini wrote:
[...]
As far as I understand, the RX51 ha
try_unlock_memory() is only used in one file, so make it static
in that file,remove it from the sys_proto header file, and relocate
it into the #ifdef section that call it. This will make it only built
under the conditions when it is called, and it may help with some
further optimization in the fut
secure_unlock_mem() is only used in one file, so make it static
in that file.
Signed-off-by: Adam Ford
---
V2: Move secure_unlock_mem into area encompassed by ifdef to only
define it when potentially used to avoid errors.
diff --git a/arch/arm/mach-omap2/omap3/board.c
b/arch/arm/mach-omap
secureworld_exit() is only used in one file, so make it static
to that file and remove it from sys_proto.h. This
may help with some further optimization in the future.
Signed-off-by: Adam Ford
---
V2: Move secureworld_exit into area encompassed by ifdef to only
define when potentially used
Several functions in omap3/board.c are only used in that file, and
two of them are only called when certain conditions are true in an
ifdef. Rearange these functions to also be inside the ifdef and
make them static.
Before:
text data bss dec hex filename
4999810571888
Since this flash doesn't have a Profile 1.0 table, the Octal DTR
capabilities are enabled in the post SFDP fixup, along with the 8D-8D-8D
fast read settings.
Enable Octal DTR mode with 20 dummy cycles to allow running at the
maximum supported frequency of 200Mhz.
Signed-off-by: Pratyush Yadav
--
The Cypress Semper flash is an xSPI compliant octal DTR flash. Add
support for using it in octal DTR mode.
The flash by default boots in a hybrid sector mode. Switch to uniform
sector mode on boot. Use the default 20 dummy cycles for a read fast
command.
The SFDP programming on some older version
On devices with non-uniform sector sizes like Spansion S25 or S28 family
of flashes the sector under erase does not necessarily have to be
mtd->erasesize bytes long. For example, on S28 flashes the first 128 KiB
region is composed of 32 4 KiB sectors, then a 128 KiB sector, and then
256 KiB sectors
From: Takahiro Kuwano
Some of Spansion/Cypress chips have overlaid 4KB sectors at top and/or
bottom, depending on the device configuration, while U-Boot supports
uniform sector layout only.
The spansion_erase_non_uniform() erases overlaid 4KB sectors,
non-overlaid portion of normal sector, and
When the flash is handed to us in a stateful mode like 8D-8D-8D, it is
difficult to detect the mode the flash is in. One option is to read SFDP
in all modes and see which one gives the correct "SFDP" signature, but
not all flashes support SFDP in 8D-8D-8D mode.
Further, even if you detect the mod
On probe, the SPI NOR core will put a flash in 8D-8D-8D mode if it
supports it. But Linux as of now expects to get the flash in 1S-1S-1S
mode. Handing the flash to Linux in Octal DTR mode means the kernel will
fail to detect the flash.
So, we need to reset to Power-on-Reset (POR) state before hand
A Soft Reset sequence will return the flash to Power-on-Reset (POR)
state. It consists of two commands: Soft Reset Enable and Soft Reset.
Find out if the sequence is supported from BFPT DWORD 16.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 6 ++
include/linux/mtd/spi-n
The Micron MT35XU512ABA flash does not support the quad enable bit. But
instead of programming the Quad Enable Require field to 000b ("Device
does not have a QE bit"), it is programmed to 111b ("Reserved").
While this is technically incorrect, it is not reason enough to abort
BFPT parsing. Instead
Allow flashes to specify a hook to enable octal DTR mode. Use this hook
whenever possible to get optimal transfer speeds.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 31 +++
include/linux/mtd/spi-nor.h| 2 ++
2 files changed, 33 insertions(
The xSPI Profile 1.0 table specifies how many dummy cycles and address
bytes are needed for the Read Status Register command in Octal DTR mode.
Use that information to send the correct Read SR command.
Some controllers might have trouble reading just 1 byte in DTR mode. So,
when we are in DTR mode
This table is indication that the flash is xSPI compliant and hence
supports octal DTR mode. Extract information like the fast read opcode,
the number of dummy cycles needed for a Read Status Register command,
and the number of address bytes needed for a Read Status Register
command.
The default d
Even when spi_nor_write_reg() has no data to write, like when executing
a write enable operation, it sets the data direction to
SPI_MEM_DATA_OUT. This trips up spi_mem_check_buswidth() because it
expects a data phase when there is none. Make sure the data direction is
set to SPI_MEM_NO_DATA when th
Sometimes the information in a flash's SFDP tables is wrong. Sometimes
some information just can't be expressed in the SFDP table. So,
introduce the fixup hooks to allow tailoring settings for a specific
flash.
Three hooks are added: default_init, post_sfdp, and post_bfpt. These
allow tweaking the
JESD216 rev D makes BFPT 20 DWORDs. Update the BFPT size define to
reflect that.
The check for rev A or later compared the BFPT header length with the
maximum BFPT length, BFPT_DWORD_MAX. Since BFPT_DWORD_MAX was 16, and so
was the BFPT length for both rev A and B, this check worked fine. But
now,
Some devices in DTR mode expect an extra command byte called the
extension. The extension can either be same as the opcode, bitwise
inverse of the opcode, or another additional byte forming a 16-byte
opcode. Get the extension type from the BFPT. For now, only flashes with
"repeat" and "inverse" ext
Double Transfer Rate (DTR) is SPI protocol in which data is transferred
on each clock edge as opposed to on each clock cycle. Make
framework-level changes to allow supporting flashes in DTR mode.
Right now, mixed DTR modes are not supported. So, for example a mode
like 4S-4D-4D will not work. All
The spi-mem layer provides a spi_mem_supports_op() function to check
whether a specific operation is supported by the controller or not.
This is much more accurate than the hwcaps selection logic based on
SPI_{RX,TX}_ flags.
Rework the hwcaps selection logic to use spi_mem_supports_op().
To make
nor->setup() can be used by flashes to configure settings in case they
have any peculiarities that can't be easily expressed by the generic
spi-nor framework. This includes things like different opcodes, dummy
cycles, page size, uniform/non-uniform sector sizes, etc.
Move related declarations to a
These structures will be used in a later commit inside another structure
definition. Also take the declarations out of the ifdef since they won't
affect the final binary anyway and will be used in a later commit.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 224
Set up opcode extension and enable/disable DTR mode based on whether the
command is DTR or not.
xSPI flashes can have a 4-byte dummy address associated with some
commands like the Read Status Register command in octal DTR mode. Since
the flash does not support sending the dummy address, we can not
If a flash chip has more than 16MB capacity but its BFPT reports
BFPT_DWORD1_ADDRESS_BYTES_3_OR_4, the spi-nor framework defaults to 3.
The check in spi_nor_scan() doesn't catch it because addr_width did get
set. This fixes that check.
Ported from Kernel commit 324f78dfb442b82365548b657ec4e6974c6
Once the start bit is toggled it takes a small amount of time before it
is internally synchronized. This means we can't start writing during
that part. So add a small delay to allow the bit to be synchronized.
Signed-off-by: Pratyush Yadav
---
drivers/spi/cadence_qspi.c | 4
drivers/spi
If the device tree provides a read delay value, use that directly and do
not perform the calibration procedure.
This allows the device tree to over-ride the read delay value in cases
where the read delay value obtained via calibration is incorrect. One
such example is the Cypress Semper flash. It
spi_mem_default_supports_op() rejects DTR ops by default to ensure that
the controller drivers that haven't been updated with DTR support
continue to reject them. It also makes sure that controllers that don't
support DTR mode at all (which is most of them at the moment) also
reject them.
This mea
In xSPI mode, flashes expect 2-byte opcodes. The second byte is called
the "command extension". There can be 3 types of extensions in xSPI:
repeat, invert, and hex. When the extension type is "repeat", the same
opcode is sent twice. When it is "invert", the second byte is the
inverse of the opcode.
Controllers can use this function to perform basic sanity checking on
the spi-mem op.
Reviewed-by: Sean Anderson
Signed-off-by: Pratyush Yadav
---
include/spi-mem.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/spi-mem.h b/include/spi-mem.h
index fe249f77ba..de3c11c8e2 100644
-
Each phase is given a separate 'dtr' field so mixed protocols like
4S-4D-4D can be supported.
Signed-off-by: Pratyush Yadav
---
drivers/spi/spi-mem.c | 3 +++
include/spi-mem.h | 8
2 files changed, 11 insertions(+)
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index c
Hi,
This series adds support for octal DTR flashes in the SPI NOR framework,
and then adds hooks for the Cypress S28HS512T and Micron MT35XU512ABA
flashes.
The Cadence QSPI controller driver is also updated to run in Octal DTR
mode.
Tested on TI J721E for MT35XU512ABA and J7200 for S28HS512T. Al
The AM3517 uses SYS_MALLOC_F_LEN of size 0x3000, but the rest of
the OMAP3 boards from LogicPD / BeaconEmbedded use 0x4000, but
they don't boot SPL.
Reduce the malloc size to restore booting.
Signed-off-by: Adam Ford
diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig
i
On Friday 25 June 2021 10:43:11 Simon Glass wrote:
> Hi Pali,
>
> On Fri, 25 Jun 2021 at 10:16, Pali Rohár wrote:
> >
> > On Friday 25 June 2021 10:04:14 Simon Glass wrote:
> > > But I do wonder about the
> > > 100KB growth you saw with DT/DM. That seems absolutely enormous to me!
> > > Can you p
Switch to fit_image_get_data_and_size() for consistency with all other
data loaded from FIT.
Signed-off-by: John Keeping
---
common/image-fit.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/common/image-fit.c b/common/image-fit.c
index 94501b1071..4c5a24806d 100644
--- a/
Hi Pali,
On Fri, 25 Jun 2021 at 10:16, Pali Rohár wrote:
>
> On Friday 25 June 2021 10:04:14 Simon Glass wrote:
> > Hi Pali,
> >
> > On Fri, 25 Jun 2021 at 07:07, Pali Rohár wrote:
> > >
> > > On Friday 25 June 2021 08:38:47 Tom Rini wrote:
> > > > On Sun, Jun 20, 2021 at 09:43:43PM +0200, Marek
On Friday 25 June 2021 10:04:14 Simon Glass wrote:
> Hi Pali,
>
> On Fri, 25 Jun 2021 at 07:07, Pali Rohár wrote:
> >
> > On Friday 25 June 2021 08:38:47 Tom Rini wrote:
> > > On Sun, Jun 20, 2021 at 09:43:43PM +0200, Marek Vasut wrote:
> > > > On 6/20/21 5:54 PM, Tom Rini wrote:
> > > >
> > > >
Hi Pali,
On Fri, 25 Jun 2021 at 07:07, Pali Rohár wrote:
>
> On Friday 25 June 2021 08:38:47 Tom Rini wrote:
> > On Sun, Jun 20, 2021 at 09:43:43PM +0200, Marek Vasut wrote:
> > > On 6/20/21 5:54 PM, Tom Rini wrote:
> > >
> > > [...]
> > >
> > > > > As far as I understand, the RX51 has gigabytes
Hi Andrey
+Philippe and Yannick who are the experts, please interacts directly with them.
Here is Philippe's answer:
The CONFIG_VIDEO_MIPI_DSI flag is not necessary as the panel is DPI, and so
maybe this DSI configuration annoys the rest of the display chain...
Moreover, we are not using follo
On Thu, Jun 24, 2021 at 4:43 PM Pratyush Yadav wrote:
>
> On 23/06/21 05:32PM, Jagan Teki wrote:
> > On Wed, May 5, 2021 at 3:11 PM Pratyush Yadav wrote:
> > >
> > > Hi,
> > >
> > > This series adds support for octal DTR flashes in the SPI NOR framework,
> > > and then adds hooks for the Cypress
On Fri, Jun 25, 2021 at 3:01 PM Jagan Teki wrote:
>
> On Wed, Jun 23, 2021 at 2:46 PM Zhengxun wrote:
> >
> > Add a driver for Macronix SPI controller IP.
> >
> > This patch referred from linux spi-mxic.c. The difference from the
> > linux version is described here.
> >
> > 1. To adapt uboot spi
Hi Sean,
On Fri, Jun 25, 2021 at 09:47:11AM -0400, Sean Anderson wrote:
> On 6/25/21 9:05 AM, Maxime Ripard wrote:
> > This reverts commit 27c9141b1114fd5721437abbb1c694e45e765f19.
>
> Why does this need to be reverted?
As I stated in the cover letter, I don't really know enough about USB to
kno
On 25.06.21 16:10, Stefano Babic wrote:
Hi Tom,
please pull from u-boot-imx, thanks !
this just contains fixes for warning in last PR + a couple of other
fixes (patches I missed last time).
It is of course u-boot-imx-20210625
Best regards,
Stefano
.denx.de/u-boot/custodians/u-boot-net (2021-06-18 11:18:56
-0400)
are available in the Git repository at:
https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git
tags/u-boot-imx-20210625
for you to fetch changes up to 52ce6a61c1fc74b62be7f57ba83c1b43181b1f91:
imx8mm: configs: enable dist
On Fri, 25 Jun 2021 15:05:44 +0200
Maxime Ripard wrote:
> Both mtdparts_init() and find_dev_and_part() will return 0 on success
> but 1 on failure.
>
> Since the calling functions of fb_nand_lookup expects a negative error
> code on failure, we can't just return the returned value of these
> fun
On 6/25/21 9:05 AM, Maxime Ripard wrote:
This reverts commit 27c9141b1114fd5721437abbb1c694e45e765f19.
Why does this need to be reverted?
--Sean
---
drivers/usb/gadget/f_fastboot.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/gadget/f_fastboot.c b/driver
On Fri, 25 Jun 2021 15:05:41 +0200
Maxime Ripard wrote:
> Most of the error messages in the NAND fastboot support are missing a \n
> at the end, add it where relevant.
>
> Signed-off-by: Maxime Ripard
Reviewed-by: Andre Przywara
Thanks!
Andre
> ---
> drivers/fastboot/fb_nand.c | 10 +--
On Fri, 25 Jun 2021 15:05:42 +0200
Maxime Ripard wrote:
> The CHIP Pro doesn't have a video output, so it doesn't make sense to
> have the video support enabled.
>
> A side effect is that it prevents the messages from the HDMI controller
> about a missing DDC controller to retrieve the EDID, whi
On Fri, 25 Jun 2021 15:05:43 +0200
Maxime Ripard wrote:
> The NextThingCo GR8 is a derivative of the sun5i family, and thus should
> be considered similar to the A10s and A13 as far as clocks go.
>
> The compatible was missing from the clock driver so far, leading to all
> the drivers depending
In the Linux DT the file rk3xxx.dtsi is shared between
rk3066 and rk3188. Both rk3xxx.dtsi and rk3188.dtsi have recently
had some updates.
For a future rk3066 support in U-boot this file must also update.
Move U-boot specific things in a rk3188-u-boot.dtsi file.
Signed-off-by: Johan Jonker
---
a
In the Linux DT the file rk3xxx.dtsi is shared between
rk3066 and rk3188. Both rk3xxx.dtsi and rk3188.dtsi have recently
had some updates.
For a future rk3066 support in U-boot this file must also update.
Move U-boot specific things in a rk3188-radxarock-u-boot.dtsi file.
Signed-off-by: Johan Jonk
In order to update the DT for rk3188
sync the power domain dt-binding header.
This is the state as of v5.12 in Linux.
Signed-off-by: Johan Jonker
---
include/dt-bindings/power/rk3188-power.h | 24
1 file changed, 24 insertions(+)
create mode 100644 include/dt-bindings/p
In the Linux DT the file rk3xxx.dtsi is shared between
rk3066 and rk3188. This file has recently had some updates.
For a future rk3066 support in U-boot this file must also update.
Move U-boot specific things in a rk3xxx-u-boot.dtsi file.
Signed-off-by: Johan Jonker
---
Changed V2:
add vpu nod
In order to update the DT for rk3066 and rk3188
sync the clock dt-binding header.
This is the state as of v5.12 in Linux.
Signed-off-by: Johan Jonker
Reviewed-by: Heiko Stuebner
---
include/dt-bindings/clock/rk3188-cru-common.h | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
On Friday 25 June 2021 08:38:47 Tom Rini wrote:
> On Sun, Jun 20, 2021 at 09:43:43PM +0200, Marek Vasut wrote:
> > On 6/20/21 5:54 PM, Tom Rini wrote:
> >
> > [...]
> >
> > > > As far as I understand, the RX51 has gigabytes of eMMC storage, so it
> > > > can
> > > > use SPL just like any other O
The controller name in Linux isn't sunxi_nand.0 but
1c03000.nand-controller, preventing us from passing the mtdparts
variable directly on the kernel command line.
Let's adjust our value to match what Linux expects.
Signed-off-by: Maxime Ripard
---
configs/CHIP_pro_defconfig | 4 ++--
1 file cha
The CHIP Pro MTD partition table sets the U-Boot offset at
512kB (0x8), and its backup at 2.5MB (0x28).
However, the default value for both of these on sunxi is 8MB (0x80),
which doesn't work in our case.
Fix this.
Signed-off-by: Maxime Ripard
---
configs/CHIP_pro_defconfig | 2 ++
Both mtdparts_init() and find_dev_and_part() will return 0 on success
but 1 on failure.
Since the calling functions of fb_nand_lookup expects a negative error
code on failure, we can't just return the returned value of these
functions.
This fixes an issue with the logic that detects whether we su
The CHIP Pro doesn't have any block storage device, so enabling UMS
makes little sense.
Signed-off-by: Maxime Ripard
---
configs/CHIP_pro_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/configs/CHIP_pro_defconfig b/configs/CHIP_pro_defconfig
index d2eddc7e9ff0..c8e2e2ae2ca3 100644
-
The NextThingCo GR8 is a derivative of the sun5i family, and thus should
be considered similar to the A10s and A13 as far as clocks go.
The compatible was missing from the clock driver so far, leading to all
the drivers depending on it being non-functional.
Signed-off-by: Maxime Ripard
---
driv
The CHIP Pro doesn't have a video output, so it doesn't make sense to
have the video support enabled.
A side effect is that it prevents the messages from the HDMI controller
about a missing DDC controller to retrieve the EDID, which doesn't make
much sense since the GR8 doesn't have an HDMI contro
Most of the error messages in the NAND fastboot support are missing a \n
at the end, add it where relevant.
Signed-off-by: Maxime Ripard
---
drivers/fastboot/fb_nand.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/fastboot/fb_nand.c b/drivers/fastboot/fb_
20 characters is fairly short for a partition table, let's increase it a
bit.
Signed-off-by: Maxime Ripard
---
drivers/mtd/mtd_uboot.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/mtd_uboot.c b/drivers/mtd/mtd_uboot.c
index c53ec657a34d..3b54d0ba6e95 100644
---
The SPL_PANIC_ON_RAW_IMAGE can be fairly useful to avoid the SPL getting
stuck without a message when the image retrieved isn't a valid image.
Let's convert it to Kconfig.
Signed-off-by: Maxime Ripard
---
README | 10 --
common/spl/Kconfig | 14 ++
This reverts commit 27c9141b1114fd5721437abbb1c694e45e765f19.
---
drivers/usb/gadget/f_fastboot.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c
index 8ba55aab9f8f..1fcffaf9dd26 100644
--- a/drivers/usb/gadget/f
This reverts commit 136e32593335e031558a573158b6180fc80b551f.
---
board/sunxi/board.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 21651a1bfca4..80c222114f9a 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -395,6 +395,11 @@
This reverts commit 6ddbb1e936c78cdef1e7395039fa7020c5c75326.
---
drivers/mtd/nand/raw/sunxi_nand_spl.c | 141 --
1 file changed, 85 insertions(+), 56 deletions(-)
diff --git a/drivers/mtd/nand/raw/sunxi_nand_spl.c
b/drivers/mtd/nand/raw/sunxi_nand_spl.c
index 85d8013b1a6
Hi,
These patches fix the NextThingCo CHIP Pro support in upstream U-Boot.
The three reverts are not supposed to be merged at this point: the first two
will break the NAND support on newer Allwinner SoCs, and it's not clear what
the fastboot one does exactly, so I'm a bit concerned about the side
On Wed, Jun 23, 2021 at 08:08:50AM +0200, Wolfgang Denk wrote:
> Dear Simon,
>
> In message
> you
> wrote:
> >
> > > > 0m123 ? ('m' for deciMal).
> > >
> > > Perhaps 0d123? Though I would prefer to remove many of the implicit
> > > assumptions of hex input.
> >
> > Right, we can't use 'd' beca
On Fri, Jun 25, 2021 at 03:13:07AM +0200, Marek Vasut wrote:
> Beacon board fix, for this release.
>
> The following changes since commit fcf3981161140d265b873a5b609b8867328dc9dc:
>
> Merge https://source.denx.de/u-boot/custodians/u-boot-x86 (2021-06-23
> 08:46:26 -0400)
>
> are available in
On Fri, Jun 25, 2021 at 03:12:16AM +0200, Marek Vasut wrote:
> A few easy MX7 EHCI USB fixes, for this release.
>
> The following changes since commit fcf3981161140d265b873a5b609b8867328dc9dc:
>
> Merge https://source.denx.de/u-boot/custodians/u-boot-x86 (2021-06-23
> 08:46:26 -0400)
>
> are
On Sun, Jun 20, 2021 at 09:43:43PM +0200, Marek Vasut wrote:
> On 6/20/21 5:54 PM, Tom Rini wrote:
>
> [...]
>
> > > As far as I understand, the RX51 has gigabytes of eMMC storage, so it can
> > > use SPL just like any other OMAP3 board.
> >
> > U-Boot is being called by the old vendor X-Loader
On Thu, 24 Jun 2021 09:02:45 +0800
nicholas_zh...@outlook.com wrote:
Hi,
this is some revised version, isn't it? Can you please start putting
patch version numbers into the subject: "[PATCH v4] arm: ..."? It's hard
to see what's outdated and find the latest version otherwise.
> From: weichangzhe
Hi Folks,
I am trying to display a splash image from u-boot on the Phytec's
phyBOARD Sargas STM32MP157 evaluation board.
https://www.phytec.de/en/produkte/single-board-computer/phyboard-sargas-stm32mp1/
https://www.phytec.de/en/cdocuments/?doc=d4PmEQ
I feel like I tried everything possible includ
On Thursday 27 May 2021 10:17:33 Pali Rohár wrote:
> On Thursday 27 May 2021 08:17:41 Stefan Roese wrote:
> > On 25.05.21 19:42, Marek Behún wrote:
> > > From: Pali Rohár
> > >
> > > Unfortunately the UART driver in current Linux for Armada 3700 expects
> > > UART's parent clock to be XTAL and ca
This adds serial parameters that include stop bit mode, parity mode,
and character length. Mark parity and space parity modes are not
supported.
At the moment, the only path to call setconfig directly is DM testing,
however, this affects the size of SPL for DM testing, so it doesn't
apply to SPL.
On Wed, Jun 23, 2021 at 2:46 PM Zhengxun wrote:
>
> Add a driver for Macronix SPI controller IP.
>
> This patch referred from linux spi-mxic.c. The difference from the
> linux version is described here.
>
> 1. To adapt uboot spi framework, modify some functions naming.
>
> 2. Remove the incompatib
It boots fine with current Fedora IoT 34 nightlies, but kernel crashes are
very regular (sometimes recoverable, sometimes not), which looks to me like
the same problem that Armbian builds have, logs seem to point to an issue
with the dmc frequency.
I've compiled an excerpt of interesting looking l
Hi Alban,
> -Original Message-
> From: Bedel, Alban
> Sent: Wednesday, June 23, 2021 6:38 PM
> To: Priyanka Jain ; Varun Sethi ;
> Wasim Khan (OSS)
> Cc: u-boot@lists.denx.de; Wasim Khan
> Subject: Re: [PATCH] armv8: fsl : fix bootcmd and mcinitcmd default value
>
> On Wed, 2021-06-16
Hi Simon,
> -Original Message-
> From: Simon Glass
> Sent: Tuesday, 22 June, 2021 9:32 PM
> To: Chee, Tien Fong
> Cc: Ley Foon Tan ; Lim, Elly Siew Chin
> ; ZY - u-boot ; Marek
> Vasut ; Tan, Ley Foon ; See, Chin
> Liang ; Simon Goldschmidt
> ; Westergreen, Dalon
> ; Gan, Yau Wai
> Subj
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