Also rename a "length" to "size" for consistency with the rest of qfw.
Signed-off-by: Asherah Connor
---
(no changes since v1)
drivers/misc/qfw.c | 6 ++--
include/qfw.h | 86 +++---
2 files changed, 84 insertions(+), 8 deletions(-)
diff --git a/d
Updates the QFW driver to use the driver model, splitting the driver
into qfw_pio and qfw_mmio (for non-x86) in their own uclass.
Signed-off-by: Asherah Connor
---
Changes in v4:
- PIO definitions are now #defines
- qfw_*_plat structs are no longer in header files
- Remove yield/pause in DMA wai
We minimally exercise the sandbox driver.
Signed-off-by: Asherah Connor
---
(no changes since v1)
arch/sandbox/dts/sandbox.dtsi | 4 ++
arch/sandbox/dts/test.dts | 4 ++
drivers/misc/Makefile | 1 +
drivers/misc/qfw_sandbox.c| 129 ++
test/
Signed-off-by: Asherah Connor
---
(no changes since v1)
test/py/tests/test_qfw.py | 21 +
1 file changed, 21 insertions(+)
create mode 100644 test/py/tests/test_qfw.py
diff --git a/test/py/tests/test_qfw.py b/test/py/tests/test_qfw.py
new file mode 100644
index 00.
There's a mixture of "qemu_fwcfg_"-prefixed functions and
"qfw_"-prefixed ones. Now that the qfw name is applied in multiple
places (i.e. the uclass itself, and each of its drivers), let's
consistently use the prefix "qfw_" for anything relating to the
drivers.
Signed-off-by: Asherah Connor
---
This series moves the QFW driver into a uclass, UCLASS_QFW, and splits
the driver into qfw_pio and qfw_mmio. A sandbox driver is also added,
and a DM unit test against that driver.
On x86 a U_BOOT_DRVINFO is used to configure the qfw_pio (with compiled-
in constants used for PIO ports), otherwise
Hi Tom,
> -Original Message-
> From: Tom Rini
> Sent: Wednesday, February 24, 2021 12:29 AM
> To: Lim, Elly Siew Chin
> Cc: u-boot@lists.denx.de; Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ; Simon
> Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan, Yau
> Wa
On Tue, Feb 23, 2021 at 04:31:16PM +0100, Michal Simek wrote:
> Hi Tom,
>
> please pull these changes to your tree. The major part were clock issues
> we found for ZynqMP and Versal in some PM cases where u-boot didn't ask
> for enabling clocks. And that's why drivers are shared we also had to
>
From: Dalon Westergreen
Add target to Makefile to generate "u-boot-spl-dtb.hex" for Intel SOCFPGA
SOC64 devices (Stratix 10 and Agilex). "u-boot-spl-dtb.hex" is hex formatted
spl with and offset of CONFIG_SPL_TEXT_BASE. It combines the spl image and dtb.
"u-boot-spl-dtb.hex" is needed to generate
On Tue, Feb 23, 2021 at 10:10:11AM -0500, Simon Glass wrote:
> Hi Marty,
>
> On Thu, 13 Aug 2020 at 13:35, Alper Nebi Yasak
> wrote:
> >
> > Hi Simon, Marty,
> >
> > I'm interested in getting U-Boot to work with Kevin as well, but don't
> > have a Servo (or the willingness to open up the case ye
CONFIG_CMD_BOOTD provides 'boot' command which is required in more scripts.
Signed-off-by: Pali Rohár
---
This patch applies cleanly on top of the patch "Nokia RX-51: Enable
usbtty serial console by default" [1] and CI testing passed without
any issues [2] [3]. Please include it into U-Boot 2021.
On 21/02/23 01:02:p, Heinrich Schuchardt wrote:
> On 23.02.21 12:43, Asherah Connor wrote:
> For which architectures does the fw_cfg device exist?
>
> It it is only ARM and X86, than I am missing such a dependency on
> CONFIG_CMD_QFW.
Right now we have:
arch/arm/Kconfig:
...
conf
On 21/02/23 06:02:p, Tom Rini wrote:
> Ah well, so my experiment would likely have not worked back then anyhow
> (but I don't recall seeing an error at the time). Anyhow, for now in
> U-Boot as there's not a generic QEMU symbol, this side of things should
> depend on ARM||X86 for now and let futur
On Tue, Feb 23, 2021 at 11:54:01PM +, Asherah Connor wrote:
> On 21/02/23 11:02:p, Tom Rini wrote:
> > On Tue, Feb 23, 2021 at 05:15:49PM +0100, Heinrich Schuchardt wrote:
> > > On 2/23/21 5:03 PM, Tom Rini wrote:
> > > > On Tue, Feb 23, 2021 at 04:54:45PM +0100, Heinrich Schuchardt wrote:
> >
On 21/02/23 11:02:p, Tom Rini wrote:
> On Tue, Feb 23, 2021 at 05:15:49PM +0100, Heinrich Schuchardt wrote:
> > On 2/23/21 5:03 PM, Tom Rini wrote:
> > > On Tue, Feb 23, 2021 at 04:54:45PM +0100, Heinrich Schuchardt wrote:
> > > > qemu-system-riscv64 does not allow me to specify a file for the qfw
On 2/23/21 3:18 PM, Simon Glass wrote:
Hi Alex,
On Tue, 23 Feb 2021 at 14:48, Alex G. wrote:
On 2/23/21 1:07 PM, Mark Kettenis wrote:
Hi Simon,
Commit c5819701a3de61e2ba2ef7ad0b616565b32305e5 broke the build on
OpenBSD and probably other non-Linux systems. ENODATA, which is now
used in fit
On Tue, Feb 23, 2021 at 04:19:35PM -0500, Simon Glass wrote:
> +Tom Rini
>
> Hi Mark,
>
> On Tue, 23 Feb 2021 at 14:07, Mark Kettenis wrote:
> >
> > Hi Simon,
> >
> > Commit c5819701a3de61e2ba2ef7ad0b616565b32305e5 broke the build on
> > OpenBSD and probably other non-Linux systems. ENODATA, wh
+Tom Rini
Hi Mark,
On Tue, 23 Feb 2021 at 14:07, Mark Kettenis wrote:
>
> Hi Simon,
>
> Commit c5819701a3de61e2ba2ef7ad0b616565b32305e5 broke the build on
> OpenBSD and probably other non-Linux systems. ENODATA, which is now
> used in fit_check_format(), isn't defined. It isn't part of POSIX[1
Hi Alex,
On Tue, 23 Feb 2021 at 14:48, Alex G. wrote:
>
> On 2/23/21 1:07 PM, Mark Kettenis wrote:
> > Hi Simon,
> >
> > Commit c5819701a3de61e2ba2ef7ad0b616565b32305e5 broke the build on
> > OpenBSD and probably other non-Linux systems. ENODATA, which is now
> > used in fit_check_format(), isn'
Now that proper DM clock and reset driver exists for Display Engine 2
and 3, remove all clock and reset related code and use appropriate
framework instead.
Signed-off-by: Jernej Skrabec
---
arch/arm/mach-sunxi/Kconfig | 1 +
drivers/video/sunxi/sunxi_de2.c | 67 +++--
Video driver currently manages clocks and resets by directly writing to
registers. This is already a bit messy because each SoC has some
specifics. It's much better to implement proper clock and reset driver
which takes information from device tree file.
Note that this driver is not perfect yet. I
Now that bit meanings are somewhat known, rework PHY initialization.
This is modelled after Linux driver.
Signed-off-by: Jernej Skrabec
---
drivers/video/sunxi/sunxi_dw_hdmi.c | 411 +++-
1 file changed, 279 insertions(+), 132 deletions(-)
diff --git a/drivers/video/sunx
With the next commit another clock and reset driver will be implemented
which requires DE2 related clocks and resets. Add them.
Cc: Lukasz Majewski
Signed-off-by: Jernej Skrabec
---
drivers/clk/sunxi/clk_a64.c | 6 ++
drivers/clk/sunxi/clk_h3.c | 6 ++
2 files changed, 12 insertions(+)
Currently DE2 uses hardcoded address based on SoC for which U-Boot is
built. Read it from DT instead so there is no need to specify it when
support for new SoC is added.
Signed-off-by: Jernej Skrabec
---
drivers/video/sunxi/sunxi_de2.c | 8
1 file changed, 4 insertions(+), 4 deletions(-
Currently DE2 driver is probed via driver info. Switch probing to device
tree compatible string method.
Display is now searched via driver name which has same limitation as
previous method. This can be improved only when all drivers in chain are
probed via device tree compatible strings.
Signed-o
Currently DE2 driver uses functions which are defined in -internal
header. They are not meant to be used outside of uclass framework.
Switch DE2 driver to public ones. This has additional benefit that
device_probe doesn't need to be called manually.
Signed-off-by: Jernej Skrabec
---
drivers/vide
Currently sunxi_dw_hdmi_enable() configures PHY timing related
parameters. However, sunxi_dw_hdmi_phy_cfg() is better suited place for
that. Move the code there. This also allows to easier driver expansion
when controller uses different PHY than currently supported (like that
in H6).
Signed-off-by
Currently HDMI controller MMIO address is hardcoded. Change that so
address is read from DT node. That will make adding support for new
variants a bit easier.
Signed-off-by: Jernej Skrabec
---
drivers/video/sunxi/sunxi_dw_hdmi.c | 38 ++---
1 file changed, 24 insertions(+
Currently sunxi dw-hdmi driver is probed unconditionally, even if there
is no such device.
Switch driver to probing via compatible string. This brings many
benefits - driver can read DT node and allows driver to be always
enabled.
Signed-off-by: Jernej Skrabec
---
drivers/video/sunxi/sunxi_dw_h
Currently PHY init callback has only pixel clock as a parameter, but
other timing parameters may be needed for custom PHYs. Modify callback
signature to include full timings.
Cc: Neil Armstrong
Signed-off-by: Jernej Skrabec
---
drivers/video/dw_hdmi.c | 6 +++---
drivers/video/meson
TV driver was never fully implemented. Remove search for it from DE2
driver.
Signed-off-by: Jernej Skrabec
---
drivers/video/sunxi/sunxi_de2.c | 15 +--
1 file changed, 1 insertion(+), 14 deletions(-)
diff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c
ind
It turns out that even though A64, H3 and H5 have custom PHY, standard
hot plug detection for DW-HDMI works just fine.
Remove custom hpd method to reduce amount of custom code.
Signed-off-by: Jernej Skrabec
---
drivers/video/sunxi/sunxi_dw_hdmi.c | 34 +
1 file chang
One of my monitors have only 4k@60 timing in base EDID block which is
out of range for devices with HDMI 1.4. It turns out that it has
additional detailed timings in CTA-861 Extension Block and two of them
are appropriate for HDMI 1.4.
Add additional search for valid detailed timing in extension b
No Allwinner boards with DW-HDMI controller use separate I2C bus for
EDID read. Remove that check.
Signed-off-by: Jernej Skrabec
---
drivers/video/sunxi/sunxi_dw_hdmi.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c
b/drivers/video/sunxi/sunxi_dw_hdmi.
Code which searches for valid detailed timing entry will be used in more
places. Extract it.
Signed-off-by: Jernej Skrabec
---
common/edid.c | 49 -
1 file changed, 28 insertions(+), 21 deletions(-)
diff --git a/common/edid.c b/common/edid.c
index
When searching for detailed timing in EDID, check for digital display
earlier. There is no point parsing other parameters if this flag is not
present.
Signed-off-by: Jernej Skrabec
---
common/edid.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/common/edid.c b/comm
Currently driver accepts all resolution which won't work on 4k screens.
Add validation callback which limits acceptable resolutions to 297 MHz.
Signed-off-by: Jernej Skrabec
---
drivers/video/sunxi/sunxi_dw_hdmi.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/video/sunxi/sun
Currently sunxi Makefile manually specifies full path to dw-hdmi common
code. However, that is not needed because it can be selected in Kconfig
instead.
Select proper symbol in Kconfig and drop path from Makefile.
Signed-off-by: Jernej Skrabec
---
arch/arm/mach-sunxi/Kconfig | 1 +
drivers/vid
This series greatly reworks DE2 mixer and accompanying DW-HDMI platform
driver. Main goal was to use as many information from device tree as
possible and thus removing SoC speficic ifdefs from the code. This was
largely accomplished for mixer driver and mostly for HDMI driver.
Most of these change
On 2/23/21 7:06 PM, Daniel Schwierzeck wrote:
Am Dienstag, den 23.02.2021, 15:19 +0100 schrieb Reinoud Zandijk:
Hi Daniel,
On Tue, Feb 23, 2021 at 01:03:05AM +0100, Daniel Schwierzeck wrote:
Am Montag, den 22.02.2021, 20:56 +0100 schrieb Reinoud Zandijk:
If I remove it, the machine just spins
VenHw and VenMedia device path nodes may carry vendor defined data of
arbitrary length. When converting a device path node to text ensure that we
do not overrun our internal buffer.
In our implementation of
EFI_DEVICE_PATH_TO_TEXT_PROTOCOL.ConvertDevicePathToText() we could first
determine the out
I think you can also be more aggressive and remove the checks:
if (!master)
return -EINVAL;
from dsa_port_send and dsa_port_recv. At least it sounds broken to me
that this could ever happen.
The following comment got me curious:
/*
* stop master onl
Am 2021-02-23 17:19, schrieb Michael Walle:
DSA needs to have the master device probed first for MAC inheritance.
Until now, it only works by chance because the only user (LS1028A SoC)
will probe the master device first. The probe order is given by the PCI
device ordering, thus it works because t
On 2/23/21 1:07 PM, Mark Kettenis wrote:
Hi Simon,
Commit c5819701a3de61e2ba2ef7ad0b616565b32305e5 broke the build on
OpenBSD and probably other non-Linux systems. ENODATA, which is now
used in fit_check_format(), isn't defined. It isn't part of POSIX[1]
and generally not available on BSD-deri
Hi Simon,
Commit c5819701a3de61e2ba2ef7ad0b616565b32305e5 broke the build on
OpenBSD and probably other non-Linux systems. ENODATA, which is now
used in fit_check_format(), isn't defined. It isn't part of POSIX[1]
and generally not available on BSD-derived systems. Could you pick
another error
On 23.02.2021 16:10, Neil Armstrong wrote:
> Fix the treshold typo in code by threshold.
>
> Fixes: c0165c85c3 ("button: add a simple Analog to Digital Converter device
> based button driver")
> Suggested-by: Tom Rini
> Signed-off-by: Neil Armstrong
Acked-by: Marek Szyprowski
> ---
> drivers/
Am Dienstag, den 23.02.2021, 15:19 +0100 schrieb Reinoud Zandijk:
> Hi Daniel,
>
> On Tue, Feb 23, 2021 at 01:03:05AM +0100, Daniel Schwierzeck wrote:
> > Am Montag, den 22.02.2021, 20:56 +0100 schrieb Reinoud Zandijk:
> > > If I remove it, the machine just spins in Qemu, no output,
> > > nothing.
On Mon, Feb 22, 2021 at 9:40 AM Tom Rini wrote:
>
> On Mon, Feb 22, 2021 at 09:24:22AM -0800, Tim Harvey wrote:
> > On Wed, Feb 17, 2021 at 10:35 AM Tom Rini wrote:
> > >
> > > On Wed, Feb 17, 2021 at 10:26:20AM -0800, Tim Harvey wrote:
> > > > On Wed, Feb 10, 2021 at 9:31 AM Tom Rini wrote:
> >
The ESRT is initialised during efi_init_objlist after
efi_initialize_system_table().
The ESRT is recreated from scratch at the following events:
- successful UpdateCapsule;
- FMP instance install.
The code ensures that every ESRT entry has a unique fw_class value.
Limitations:
- The ESRT is not
This commmit exercises the ESRT creation -- introduced in the previous
commit -- in two tests.
test 1:
A fake FMP, with TEST_ESRT_NUM_ENTRIES FW images, is installed in the
system leading to the corresponding ESRT entries being populated.
The ESRT entries are checked against the datastructure u
The following 2 commits add the ESRT and provide a test of the
functionality.
The first commit adds the ESRT as defined in the UEFI 2.8 specification.
An empty ESRT is created during the execution of the efi_init_obj_list().
The ESRT is updated when:
1) a FMP protocol is installed in the system:
Am 2021-02-23 17:32, schrieb Vladimir Oltean:
On Tue, Feb 23, 2021 at 05:19:05PM +0100, Michael Walle wrote:
It doesn't make sense to have DSA without a master port. Error out
early
if there is no master port.
Fixes: fc054d563bfb ("net: Introduce DSA class for Ethernet switches")
Signed-off-by
On Tue, Feb 23, 2021 at 05:19:06PM +0100, Michael Walle wrote:
> DSA needs to have the master device probed first for MAC inheritance.
> Until now, it only works by chance because the only user (LS1028A SoC)
> will probe the master device first. The probe order is given by the PCI
> device ordering
On Tue, Feb 23, 2021 at 05:15:49PM +0100, Heinrich Schuchardt wrote:
> On 2/23/21 5:03 PM, Tom Rini wrote:
> > On Tue, Feb 23, 2021 at 04:54:45PM +0100, Heinrich Schuchardt wrote:
> > > Am 23. Februar 2021 15:53:38 MEZ schrieb Tom Rini :
> > > > On Tue, Feb 23, 2021 at 01:59:52PM +0100, Heinrich Sc
On Tue, Feb 23, 2021 at 05:19:05PM +0100, Michael Walle wrote:
> It doesn't make sense to have DSA without a master port. Error out early
> if there is no master port.
>
> Fixes: fc054d563bfb ("net: Introduce DSA class for Ethernet switches")
> Signed-off-by: Michael Walle
> ---
Reviewed-by: Vla
On Tue, Feb 23, 2021 at 07:00:47AM +, Lim, Elly Siew Chin wrote:
> Hi Tom,
>
> > -Original Message-
> > From: Tom Rini
> > Sent: Saturday, February 20, 2021 5:02 AM
> > To: Lim, Elly Siew Chin
> > Cc: u-boot@lists.denx.de; Marek Vasut ; Tan, Ley Foon
> > ; See, Chin Liang ; Simon
> >
DSA needs to have the master device probed first for MAC inheritance.
Until now, it only works by chance because the only user (LS1028A SoC)
will probe the master device first. The probe order is given by the PCI
device ordering, thus it works because the master device has a "smaller"
BDF then the
Before a DSA port is probed, the master port needs to be probed first. For
now this worked, because the probing order was correct. But it already
falls short if you use the enetc6 port on the LS1028A SoC:
Device tree snippet:
&enetc6 {
status = "okay";
};
&mscc_felix_port5 {
ethe
It doesn't make sense to have DSA without a master port. Error out early
if there is no master port.
Fixes: fc054d563bfb ("net: Introduce DSA class for Ethernet switches")
Signed-off-by: Michael Walle
---
net/dsa-uclass.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
On 2/23/21 5:03 PM, Tom Rini wrote:
On Tue, Feb 23, 2021 at 04:54:45PM +0100, Heinrich Schuchardt wrote:
Am 23. Februar 2021 15:53:38 MEZ schrieb Tom Rini :
On Tue, Feb 23, 2021 at 01:59:52PM +0100, Heinrich Schuchardt wrote:
On 23.02.21 12:43, Asherah Connor wrote:
Updates the QFW driver to
- Forwarded message from scan-ad...@coverity.com -
Date: Mon, 22 Feb 2021 16:03:35 + (UTC)
From: scan-ad...@coverity.com
To: tom.r...@gmail.com
Subject: New Defects reported by Coverity Scan for Das U-Boot
Hi,
Please find the latest report on new defect(s) introduced to Das U-Boot fo
On Tue, Feb 23, 2021 at 04:54:45PM +0100, Heinrich Schuchardt wrote:
> Am 23. Februar 2021 15:53:38 MEZ schrieb Tom Rini :
> >On Tue, Feb 23, 2021 at 01:59:52PM +0100, Heinrich Schuchardt wrote:
> >> On 23.02.21 12:43, Asherah Connor wrote:
> >> > Updates the QFW driver to use the driver model, and
On Tue, 23 Feb 2021 at 06:44, Asherah Connor wrote:
>
> We minimally exercise the sandbox driver.
>
> Signed-off-by: Asherah Connor
> ---
>
> (no changes since v1)
>
> arch/sandbox/dts/sandbox.dtsi | 4 ++
> arch/sandbox/dts/test.dts | 4 ++
> drivers/misc/Makefile | 11 ++-
> d
Hi Asherah,
On Tue, 23 Feb 2021 at 06:44, Asherah Connor wrote:
>
> Split the qfw driver into qfw_pio and qfw_mmio, under their own uclass.
> Each driver does arch/platform-specific I/O.
>
> Signed-off-by: Asherah Connor
> ---
>
> Changes in v3:
> - Add new UCLASS_QFW, split qfw driver into PIO
On Tue, 23 Feb 2021 at 01:34, Siew Chin Lim
wrote:
>
> Commit "common: Drop asm/global_data.h from common header" added
> asm/global_data.h into secure.h. However, secure.h will be included
> by psci.S. Adding asm/global_data.h has caused compilation failure in
> pcsi.S. Add "ifndef __ASSEMBLY__"
Hi Reinoud,
On Tue, 23 Feb 2021 at 09:37, Reinoud Zandijk wrote:
>
> On Mon, Feb 22, 2021 at 06:04:03PM -0500, Tom Rini wrote:
> > On Mon, Feb 22, 2021 at 10:20:12PM +0100, Reinoud Zandijk wrote:
> >
> > > Re-enable FDT inclusion into the Malta u-boot binary to make them boot
> > > again. This co
Am 23. Februar 2021 15:53:38 MEZ schrieb Tom Rini :
>On Tue, Feb 23, 2021 at 01:59:52PM +0100, Heinrich Schuchardt wrote:
>> On 23.02.21 12:43, Asherah Connor wrote:
>> > Updates the QFW driver to use the driver model, and adds support
>for QFW
>> > on Arm platforms by configuring from the device t
Hi Tom,
please pull these changes to your tree. The major part were clock issues
we found for ZynqMP and Versal in some PM cases where u-boot didn't ask
for enabling clocks. And that's why drivers are shared we also had to
add clock enable function for Zynq to pass.
There are some other fixes espe
On 23.02.21 14:57, Aaron Williams wrote:
I am using the latest pull and it's still crashing.
Now that I have a (free) USB 3 hub I can reproduce this issue. With
latest TOT I get this:
=> usb start
starting USB...
Bus xhci@16800: Register 2000140 NbrPorts 2
Starting the controller
USB X
Fix the treshold typo in code by threshold.
Fixes: c0165c85c3 ("button: add a simple Analog to Digital Converter device
based button driver")
Suggested-by: Tom Rini
Signed-off-by: Neil Armstrong
---
drivers/button/button-adc.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-
Hi Marty,
On Thu, 13 Aug 2020 at 13:35, Alper Nebi Yasak wrote:
>
> Hi Simon, Marty,
>
> I'm interested in getting U-Boot to work with Kevin as well, but don't
> have a Servo (or the willingness to open up the case yet), so I've been
> trying to boot from depthcharge as in README.chromium-chainlo
Hi Eugen,
On 23.02.2021 11:41, Eugen Hristev - M18282 wrote:
> On 27.01.2021 15:00, Claudiu Beznea wrote:
>> SAMA7G5 supports slew rate configuration. Adapt the driver for this.
>> For switching frequencies lower than 50MHz the slew rate needs to
>> be enabled. Since most of the pins on SAMA7G5 fa
On Mon, Feb 22, 2021 at 10:48:42PM +0100, Heinrich Schuchardt wrote:
> On 2/22/21 10:20 PM, Reinoud Zandijk wrote:
> > 2) direct pointer access was used to read and write the registers instead
> > of the inb/inw/outb/outw functions/macros. Registers don't have to be
> > memory mapped and ATA_CURR_B
a2f4eecb5553e01edf9:
>>
>> Merge branch '2021-02-16-assorted-improvements' (2021-02-16 15:14:34 -0500)
>>
>> are available in the Git repository at:
>>
>> https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic.git
>> tags/u-boot-amlogic-2021
02-16 15:14:34 -0500)
>
> are available in the Git repository at:
>
> https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic.git
> tags/u-boot-amlogic-20210223
>
> for you to fetch changes up to ceeb50b3bf074960ddfa541b7be3732b
anks,
Neil
The following changes since commit 496f49464d90b564da5f1a2f4eecb5553e01edf9:
Merge branch '2021-02-16-assorted-improvements' (2021-02-16 15:14:34 -0500)
are available in the Git repository at:
https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic.git
tags/u-boot-amlogic
On Tue, Feb 23, 2021 at 01:59:52PM +0100, Heinrich Schuchardt wrote:
> On 23.02.21 12:43, Asherah Connor wrote:
> > Updates the QFW driver to use the driver model, and adds support for QFW
> > on Arm platforms by configuring from the device tree and using MMIO
> > accordingly. A sandbox driver for
On Mon, Feb 22, 2021 at 06:04:03PM -0500, Tom Rini wrote:
> On Mon, Feb 22, 2021 at 10:20:12PM +0100, Reinoud Zandijk wrote:
>
> > Re-enable FDT inclusion into the Malta u-boot binary to make them boot
> > again. This could indicate an unwanted toolchain version dependency.
> >
> > Signed-off-by:
On Tue, Feb 23, 2021 at 09:26:56AM -0500, Tom Rini wrote:
> On Tue, Feb 23, 2021 at 03:19:06PM +0100, Reinoud Zandijk wrote:
> > Hi Daniel,
> >
> > On Tue, Feb 23, 2021 at 01:03:05AM +0100, Daniel Schwierzeck wrote:
> > > Am Montag, den 22.02.2021, 20:56 +0100 schrieb Reinoud Zandijk:
> > > > If I
On Tue, Feb 23, 2021 at 03:19:06PM +0100, Reinoud Zandijk wrote:
> Hi Daniel,
>
> On Tue, Feb 23, 2021 at 01:03:05AM +0100, Daniel Schwierzeck wrote:
> > Am Montag, den 22.02.2021, 20:56 +0100 schrieb Reinoud Zandijk:
> > > If I remove it, the machine just spins in Qemu, no output, nothing.
> > >
Hi Daniel,
On Tue, Feb 23, 2021 at 01:03:05AM +0100, Daniel Schwierzeck wrote:
> Am Montag, den 22.02.2021, 20:56 +0100 schrieb Reinoud Zandijk:
> > If I remove it, the machine just spins in Qemu, no output, nothing.
> > If I add
> > it, it works fine again. I found out by bisecting. I have no ide
Hello Andre,
On Tue, 23 Feb 2021 13:30:38 +
Andre Przywara wrote:
y extension_board_scan board specific function, would you prefer if I
> > move to callback like below instead of Kconfig?
> >
> > if (of_machine_is_compatible("nextthing,chip"))
> > extension_board_register_callback(chip_e
I am using the latest pull and it's still crashing.
-Aaron
On Tuesday, February 23, 2021 2:39:41 AM PST Stefan Roese wrote:
> On 23.02.21 11:36, Mark Kettenis wrote:
> >> From: Nicolas Saenz Julienne
> >> Date: Tue, 23 Feb 2021 10:23:04 +0100
> >>
> >> On Tue, 2021-02-23 at 09:15 +0100, Stefan
st 20. 1. 2021 v 21:29 odesílatel Brandon Maier
napsal:
>
> If zynqmp_qspi_set_speed() is called multiple times with the same speed,
> then on the second call it will skip recalculating the baud_rate_val as
> it assumes the speed is already configured correctly. But it will still
> write the baud_
From: Amit Kumar Mahapatra
Update the following device tree properties for nand flash
- Set software ecc mode.
- Set bch as ecc algo.
- Set read block to 0.
Signed-off-by: Amit Kumar Mahapatra
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 8
1 file chan
Update clock/pll setup, ddr, MIOs based on 2020.2 hw design.
Signed-off-by: Michal Simek
---
.../zynqmp/zynqmp-zcu1275-revB/psu_init_gpl.c | 230 +++---
1 file changed, 148 insertions(+), 82 deletions(-)
diff --git a/board/xilinx/zynqmp/zynqmp-zcu1275-revB/psu_init_gpl.c
b/board/x
Add missing configurations file for zcu208 and zcu216.
Signed-off-by: Michal Simek
---
.../zynqmp/zynqmp-zcu208-revA/psu_init_gpl.c | 1880
.../zynqmp/zynqmp-zcu216-revA/psu_init_gpl.c | 1882 +
2 files changed, 3762 insertions(+)
create mode 100644 board/xil
There is Linux driver for these chips that's why add it to device tree.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-zcu208-revA.dts | 5 -
arch/arm/dts/zynqmp-zcu216-revA.dts | 5 -
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dt
From: Ashok Reddy Soma
EMMC will have bus-width 8 and it is non-removable in general. These
are missing from dt node. Add bus-width and non-removable parameters
to emmc node.
Signed-off-by: Ashok Reddy Soma
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-mini-emmc0.dts | 2 ++
arch/arm/d
From: Ashok Reddy Soma
size of malloc() pool for use before relocation is not sufficient
for ZynqMP mini u-boot with emmc configuration. Increase it to 4K.
Signed-off-by: Ashok Reddy Soma
Signed-off-by: Michal Simek
---
configs/xilinx_zynqmp_mini_emmc0_defconfig | 2 ++
configs/xilinx_zynqmp
From: Ashok Reddy Soma
Enable time command to get the elapsed time and timer commands.
Signed-off-by: Ashok Reddy Soma
Signed-off-by: Michal Simek
---
configs/xilinx_zynq_virt_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configs/xilinx_zynq_virt_defconfig
b/configs/xilinx
st 17. 2. 2021 v 9:10 odesílatel Michal Simek napsal:
>
> Folder names corresponds to DT name. These boards have been renamed from
> zc1275 to zcu1275 by commit shown below and this should be the part of that
> commit.
>
> Fixes: 420d44678119 ("arm64: zynqmp: Rename zc1275 to zcu1275")
> Signed-of
čt 11. 2. 2021 v 19:06 odesílatel Michal Simek napsal:
>
> Clean up error path in connection where priv->rxbuffers and priv->tx_bd are
> allocated.
>
> Signed-off-by: Michal Simek
> ---
>
> Based on
> https://lists.denx.de/pipermail/u-boot/2021-February/440943.html
> https://lists.denx.de/piperma
On 27.01.2021 15:00, Claudiu Beznea wrote:
> SAMA7G5 supports slew rate configuration. Adapt the driver for this.
> For switching frequencies lower than 50MHz the slew rate needs to
> be enabled. Since most of the pins on SAMA7G5 fall into this category
> enabled the slew rate by default.
>
> Sign
po 15. 2. 2021 v 10:56 odesílatel Michal Simek napsal:
>
> Hi,
>
> Add support to enable clocks using clock subsystem ops for
> zynqmp & versal platforms. Enable rx clock in ethernet driver
> for versal platform. Add clock enable feature in i2c-cdns
> driver.
>
> Thanks,
> Karthik, Michal
>
> Chan
út 9. 2. 2021 v 8:52 odesílatel Michal Simek napsal:
>
> There is no need to clear reset reason register because it is protected by
> PMUFW already which is reported when verbose log is enabled as:
> pm_core.c@733 APU> No write permission to 0xFF5E0220
>
> Signed-off-by: Michal Simek
> ---
>
> b
On Mon, 22 Feb 2021 15:23:08 +0100
Köry Maincent wrote:
Hi Köry,
> Thanks for your reviews.
>
> On Fri, 19 Feb 2021 17:29:26 +
> Andre Przywara wrote:
>
> > >
> > > And then based on my comment in the previous patch, similar to
> > > PINEPHONE_DT_SELECTION and other board-specific option
On 23.02.21 12:43, Asherah Connor wrote:
> Updates the QFW driver to use the driver model, and adds support for QFW
> on Arm platforms by configuring from the device tree and using MMIO
> accordingly. A sandbox driver for QFW is also included, and a simple DM
> unit test for it.
For which archite
On Tue, Jan 19, 2021 at 6:12 AM Pratyush Yadav wrote:
>
> On 18/01/21 03:32PM, Adam Ford wrote:
> > On the i.MX8M Mini, ret = clk_set_rate() sets ret to the value of the
> > rate the clock was able to set. When checking for errors, it only
> > checks that it is not NULL. Since positive numbers a
On Tue, Feb 23, 2021 at 10:38:17AM +, Priyanka Jain (OSS) wrote:
> >-Original Message-
> >From: U-Boot On Behalf Of Tom Rini
> >Sent: Monday, February 22, 2021 6:43 PM
> >To: Y.b. Lu
> >Cc: Priyanka Jain ; u-boot@lists.denx.de; Jiafei Pan
> >; Xiaobo Xie ; Poonam Aggrwal
> >
> >Subjec
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