Hi Sean,
> This adds support writing to the sandbox mmc backed by an in-memory
> buffer. The unit test has been updated to test reading, writing, and
> erasing. I'm not sure what MMCs erase to; I picked 0, but if it's 0xFF
> then that can be easily changed.
Could you rebase this patch series on t
Hi Heiko,
> Hello Roman,
>
> Am 27.01.21 um 10:34 schrieb Roman Stratiienko:
> > Hello Heiko,
> >
> > Looks like these commands will provide full access to any u-boot
> > commands, including working with memory.
> > It can be used to read/set any registers/data which is not in the
> > trust zone
Hi,
On 1/30/21 5:52 AM, Sean Anderson wrote:
> On 1/21/21 3:41 AM, Michal Simek wrote:
>> Hi,
>>
>> On 1/20/21 9:25 PM, Robert Hancock wrote:
>>> I've been trying to get the U-Boot SPL to work on a Xilinx ZCU102
>>> development board. I have been testing with U-Boot 2021.01, and using
>>> the gene
On Mon, Feb 1, 2021 at 2:18 PM Bin Meng wrote:
>
> On Mon, Feb 1, 2021 at 12:17 AM Simon Glass wrote:
> >
> > With the recent addition of ACPI generation, the image size has got beyond
> > its current limit.
> >
> > Samus does not actually use this, nor x86 emulation for PCI ROMs, so
> > disable
On Mon, Jan 25, 2021 at 1:51 AM Simon Glass wrote:
>
> These ops are missing at present which is not permitted. Add an empty
> operation struct.
>
> Note: If the uclass requires operations then the drivers should provide
> them. Otherwise, checking for missing operations must be done in every
> uc
On Mon, Jan 25, 2021 at 1:51 AM Simon Glass wrote:
>
> At present the version string is obtained from PLAIN_VERSION. Some boards
> may want to configure this using the device tree, since the build system
> can more easily insert things there after U-Boot itself is built. Add this
> option to the c
On Mon, Jan 25, 2021 at 1:51 AM Simon Glass wrote:
>
> We can store this in the context and avoid passing it to each function.
> This makes it easier to follow and will also allow keeping track of the
> end of the string table (in future patches).
>
> Add an 'eos' field to the context and create a
Hi Simon,
On Mon, Jan 25, 2021 at 1:51 AM Simon Glass wrote:
>
> While static configuration is useful it cannot cover every case. Sometimes
> board revisions are encoded in resistor straps and must be read at
> runtime.
>
> The easiest way to provide this information is via sysinfo, since the
> b
Hi Simon,
On Mon, Jan 25, 2021 at 1:50 AM Simon Glass wrote:
>
> There are quite a few available version options in U-Boot. Add a list of
> the available Makefile variables and #defines, along with examples.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v3:
> - Move to doc/ and .rst format
Hi Kory,
On Thu, Jan 21, 2021 at 11:01 AM Bin Meng wrote:
>
> On Sat, Dec 26, 2020 at 5:25 AM Kory Maincent
> wrote:
> >
> > Add "zboot" command to the list of supported boot in the label_boot
> > function.
> >
> > Signed-off-by: Kory Maincent
> > ---
> >
> > Change since v1:
> > - Modify co
Hi Simon,
On Mon, Jan 25, 2021 at 1:06 AM Simon Glass wrote:
>
> This series provides a few improvements for loading of images. It also
> provides a way to show more detailed model information as well as an
> of-platdata fix noticed recently.
>
> Changes in v2:
> - Add comment to .lds file
> - Ad
On Mon, Jan 25, 2021 at 1:06 AM Simon Glass wrote:
>
> The part of U-Boot that actually ends up in u-boot-nodtb.bin is not built
> with any particular alignment. It ends at the start of the BSS section.
> The BSS section selects its own alignment, which may larger.
may be
> This means that there
On Mon, Feb 1, 2021 at 2:22 PM Bin Meng wrote:
>
> On Sun, Jan 24, 2021 at 2:08 AM Simon Glass wrote:
> >
> > Some comments were provided after this patch was applied. Address them.
> >
> > Signed-off-by: Simon Glass
> > ---
> >
> > include/acpi/acpi_device.h | 9 +
> > 1 file changed,
On Sun, Jan 24, 2021 at 2:08 AM Simon Glass wrote:
>
> Some comments were provided after this patch was applied. Address them.
>
> Signed-off-by: Simon Glass
> ---
>
> include/acpi/acpi_device.h | 9 +
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
Reviewed-by: Bin Meng
On Mon, Feb 1, 2021 at 12:17 AM Simon Glass wrote:
>
> With the recent addition of ACPI generation, the image size has got beyond
> its current limit.
>
> Samus does not actually use this, nor x86 emulation for PCI ROMs, so
> disable both features.
>
> Signed-off-by: Simon Glass
> ---
>
> config
On Mon, Feb 1, 2021 at 2:10 PM Bin Meng wrote:
>
> On Thu, Jan 14, 2021 at 11:30 AM Simon Glass wrote:
> >
> > At present long delays such as msleep(2000) can cause an overflow in this
> > function. There is no need for this, since it already uses a 64-bit int.
> >
> > Add a cast to correct this.
On Mon, Feb 1, 2021 at 2:11 PM Bin Meng wrote:
>
> On Thu, Jan 14, 2021 at 11:30 AM Simon Glass wrote:
> >
> > Add a node for this so we can indicate that it is does not require any
> > ACPI code.
> >
> > Signed-off-by: Simon Glass
> > ---
> >
> > arch/x86/dts/chromebook_coral.dts | 6 ++
>
On Thu, Jan 14, 2021 at 11:30 AM Simon Glass wrote:
>
> Add a node for this so we can indicate that it is does not require any
> ACPI code.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/x86/dts/chromebook_coral.dts | 6 ++
> 1 file changed, 6 insertions(+)
>
Reviewed-by: Bin Meng
On Thu, Jan 14, 2021 at 11:30 AM Simon Glass wrote:
>
> At present long delays such as msleep(2000) can cause an overflow in this
> function. There is no need for this, since it already uses a 64-bit int.
>
> Add a cast to correct this.
>
> Signed-off-by: Simon Glass
> ---
>
> drivers/timer/tsc_
Sync all J721e related v5.11-rc6 Linux kernel dts into U-Boot.
HBMC nodes are not yet added in Linux kernel yet but were added
in U-Boot. In order to avoid any regressions, hbmc nodes are kept
intact. These will be added in kernel in future.
Signed-off-by: Lokesh Vutla
---
.../k3-j721e-common-pr
Sync all J7200 related v5.11-rc6 Linux kernel dts into U-Boot.
MCU R5F nodes are not yet added in Linux kernel yet but were added
in U-Boot. In order to avoid regressions, r5f nodes are kept intact.
These will be added in kernel in future.
Signed-off-by: Lokesh Vutla
---
.../k3-j7200-common-proc
Sync all AM65 related v5.11-rc6 Linux kernel dts into U-Boot.
Signed-off-by: Lokesh Vutla
---
arch/arm/dts/k3-am65-main.dtsi| 832 +++---
arch/arm/dts/k3-am65-mcu.dtsi | 221 +++--
arch/arm/dts/k3-am65-wakeup.dtsi | 48 +-
arch/arm/dts/k3
Sync are TI's K3 related v5.11-rc6 Linux kernel dts into U-Boot.
This series depends on the following two patch series:
https://patchwork.ozlabs.org/project/uboot/list/?series=226539
https://patchwork.ozlabs.org/project/uboot/list/?series=227056
Lokesh Vutla (3):
arm: dts: k3-am65: Sync Linux v
Dne ponedeljek, 01. februar 2021 ob 01:46:22 CET je Andre Przywara napisal(a):
> On Sun, 31 Jan 2021 21:25:39 +0100
> Jernej Skrabec wrote:
>
> Hi Jernej,
>
> > It turns out that there is a magic bit in PRCM region which seemingly
> > makes PLLs work if it's enabled. Sadly, there is no documenta
On Wed, Jan 6, 2021 at 8:59 PM Bin Meng wrote:
>
> U-Boot coding convention prefers tabs over spaces.
>
> Signed-off-by: Bin Meng
> ---
>
> include/linux/mtd/spi-nor.h | 20 ++--
> 1 file changed, 10 insertions(+), 10 deletions(-)
>
Ping?
On 27/01/21 5:50 am, Suman Anna wrote:
> The K3 R5F remoteproc driver in U-Boot was upstreamed prior to the
> equivalent remoteproc driver in the Linux kernel. Some of the DT
> properties used in U-Boot got upstreamed using different names
> in Linux kernel.
>
> The modified property names incl
On 19/01/21 2:58 am, Dario Binacchi wrote:
> With commit 38d6b7ebdaee ("spl: Drop bd_info in the data section") you
> need to enable this option to boot from mmc.
>
> Signed-off-by: Dario Binacchi
Applied to u-boot-ti/for-rc
Thanks and regards,
Lokesh
> ---
>
> configs/am335x_evm_defconfi
On Mon, Feb 1, 2021 at 8:34 AM Sean Anderson wrote:
>
> This device has four IOs connected to the SPI flash. Add the appropriate
> bindings.
>
> Signed-off-by: Sean Anderson
> ---
>
> arch/riscv/dts/k210-maix-bit.dts | 2 ++
> 1 file changed, 2 insertions(+)
>
Reviewed-by: Bin Meng
On Mon, Feb 1, 2021 at 8:36 AM Sean Anderson wrote:
>
> This prints some basic metadata about the SPI memory op. This information
> may be used to debug SPI drivers (e.g. determining the expected SPI mode).
> It is also helpful for verifying that the data on the wire matches the data
> intended to
On Mon, Feb 1, 2021 at 8:35 AM Sean Anderson wrote:
>
> This line should come before the docs for the next function.
>
> Fixes: 7aeedac0153 ("mtd: spi: Port SPI NOR framework from Linux")
>
> Signed-off-by: Sean Anderson
> ---
>
> include/linux/mtd/spi-nor.h | 2 +-
> 1 file changed, 1 insertion
On Mon, Feb 1, 2021 at 8:35 AM Sean Anderson wrote:
>
> This is useful for extending the default functionality.
>
> Signed-off-by: Sean Anderson
> ---
>
> include/spi-mem.h | 3 +++
> 1 file changed, 3 insertions(+)
>
Reviewed-by: Bin Meng
On Mon, Feb 1, 2021 at 8:35 AM Sean Anderson wrote:
>
> The sf test command is used to test spi flashes (and spi masters). Printing
> the exact error code is very helpful to those debugging the spi stack.
>
> Signed-off-by: Sean Anderson
> ---
>
> cmd/sf.c | 22 +-
> 1 file c
On Mon, Feb 1, 2021 at 8:35 AM Sean Anderson wrote:
>
> If there is an error while erasing SPI flash, no errno is displayed. This
> makes it difficult to determine the cause of the error. This change mirrors
> the logic for write errors above.
>
> Signed-off-by: Sean Anderson
> ---
>
> cmd/sf.c
On 1/17/21 7:27 AM, Bin Meng wrote:
Add some verbose debug output when crc16 check fails.
Signed-off-by: Bin Meng
Reviewed-by: Jaehoon Chung
---
Changes in v2:
- do the crc_ok assignment at the the same line where it's defined
drivers/mmc/mmc_spi.c | 6 --
1 file changed, 4 insertion
Hi Bin,
On 2/1/21 1:20 PM, Bin Meng wrote:
> From: Bin Meng
>
> After command is sent and before card response shows up on the line,
> there is a variable number of clock cycles in between called Ncr.
> The spec [1] says the minimum is 1 byte and the maximum is 8 bytes.
>
> Current logic in mmc
On 2/1/21 1:20 PM, Bin Meng wrote:
> From: Bin Meng
>
> mmc_spi_sendcmd(), mmc_spi_readdata() and mmc_spi_writedata() are
> currently undocumented. Add comment blocks to explain the arguments
> and the return value.
>
> Signed-off-by: Bin Meng
Reviewed-by: Jaehoon Chung
Best Regards,
Jaehoon
On 2/1/21 1:20 PM, Bin Meng wrote:
> From: Bin Meng
>
> The argument check should happen before any transfer on the SPI lines.
>
> Signed-off-by: Bin Meng
> ---
>
> drivers/mmc/mmc_spi.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/mmc/mmc_spi.c b/dr
From: Bin Meng
mmc_spi_sendcmd(), mmc_spi_readdata() and mmc_spi_writedata() are
currently undocumented. Add comment blocks to explain the arguments
and the return value.
Signed-off-by: Bin Meng
---
drivers/mmc/mmc_spi.c | 36 +++-
1 file changed, 35 insertions
From: Bin Meng
After command is sent and before card response shows up on the line,
there is a variable number of clock cycles in between called Ncr.
The spec [1] says the minimum is 1 byte and the maximum is 8 bytes.
Current logic in mmc_spi_sendcmd() has a flaw that it could only work
with cer
From: Bin Meng
The argument check should happen before any transfer on the SPI lines.
Signed-off-by: Bin Meng
---
drivers/mmc/mmc_spi.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/mmc_spi.c b/drivers/mmc/mmc_spi.c
index b1edb6a..85a2818 100644
--- a/d
After command is sent and before card response shows up on the line,
there is a variable number of clock cycles in between called Ncr.
The spec [1] says the minimum is 1 byte and the maximum is 8 bytes.
Current logic in mmc_spi_sendcmd() has a flaw that it could only work
with certain SD cards w
On Mon, Feb 01, 2021 at 03:54:39AM +0100, Heinrich Schuchardt wrote:
> On 1/31/21 2:49 PM, Tom Rini wrote:
> > On Sun, Jan 31, 2021 at 01:15:20PM +0100, Pali Rohár wrote:
> > > On Saturday 30 January 2021 22:17:45 Simon Glass wrote:
> > > > This test is not reliable. Quite often (20%?) it makes the
On Thu, Jan 28, 2021 at 11:14 PM Bin Meng wrote:
>
> On Sun, Jan 17, 2021 at 8:27 PM Bin Meng wrote:
> >
> > Add some verbose debug output when crc16 check fails.
> >
> > Signed-off-by: Bin Meng
> > Reviewed-by: Jaehoon Chung
> >
> > ---
> >
> > Changes in v2:
> > - do the crc_ok assignment at
On 1/31/21 2:49 PM, Tom Rini wrote:
On Sun, Jan 31, 2021 at 01:15:20PM +0100, Pali Rohár wrote:
On Saturday 30 January 2021 22:17:45 Simon Glass wrote:
This test is not reliable. Quite often (20%?) it makes the build fail and
a retry succeeds.
This test should work. Are there any logs with is
Hi,
On Mon, Feb 1, 2021 at 9:58 AM Kever Yang wrote:
>
> Hi Xiaobo,
>
>
> Thanks for your update, see comments in line.
>
> On 2021/1/29 下午10:34, alex tian wrote:
> > From c9563fe439e07e760d29a42e737b8265d5772150 Mon Sep 17 00:00:00 2001
> > From: Xiaobo Tian mailto:peterwil...@gmail.com>>
>
sqfs_opendir() called in sqfs_size(), sqfs_read(), sqfs_exists() may fail
leading to sqfs_closedir(NULL) being called. Do not dereference NULL.
Signed-off-by: Heinrich Schuchardt
---
fs/squashfs/sqfs.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/fs/squashfs/sqfs.c b/fs/squashfs/sqfs.c
sandbox_scmi_devices_ctx() may return NULL. We should not dereference this
value in sandbox_scmi_devices_remove().
The problem was indicated by 'gcc-11 -fanalyzer'.
Signed-off-by: Heinrich Schuchardt
---
drivers/firmware/scmi/sandbox-scmi_devices.c | 3 +++
1 file changed, 3 insertions(+)
diff
Hi Xiaobo,
Thanks for your update, see comments in line.
On 2021/1/29 下午10:34, alex tian wrote:
From c9563fe439e07e760d29a42e737b8265d5772150 Mon Sep 17 00:00:00 2001
From: Xiaobo Tian mailto:peterwil...@gmail.com>>
Date: Fri, 29 Jan 2021 22:30:22 +0800
Subject: [PATCH] arm64: rk3399: Add
On Sun, 31 Jan 2021 21:25:39 +0100
Jernej Skrabec wrote:
Hi Jernej,
> It turns out that there is a magic bit in PRCM region which seemingly
> makes PLLs work if it's enabled. Sadly, there is no documentation what
> it does exactly, so we'll just mimick BSP boot0 behaviour and enable it
> before
On Sun, Jan 31, 2021 at 03:58:01PM +0100, Marek Vasut wrote:
> The following changes since commit 472a716b8fdfd88a27cb675e4ea8e12cb4f79fc3:
>
> configs: Resync with savedefconfig (2021-01-29 13:56:04 -0500)
>
> are available in the Git repository at:
>
> git://git.denx.de/u-boot-usb.git mas
On Sun, Jan 31, 2021 at 03:57:24PM +0100, Marek Vasut wrote:
> The following changes since commit 472a716b8fdfd88a27cb675e4ea8e12cb4f79fc3:
>
> configs: Resync with savedefconfig (2021-01-29 13:56:04 -0500)
>
> are available in the Git repository at:
>
> git://git.denx.de/u-boot-sh.git mast
On Sat, Jan 30, 2021 at 08:28:26PM -0700, Simon Glass wrote:
> Hi Tom,
>
> https://gitlab.denx.de/u-boot/custodians/u-boot-dm/-/pipelines/6139
>
>
> The following changes since commit 472a716b8fdfd88a27cb675e4ea8e12cb4f79fc3:
>
> configs: Resync with savedefconfig (2021-01-29 13:56:04 -0500)
This adds support for DUAL/QUAD/OCTAL transfers. This adds
dw_spi_supports_op to do some sanity checks which would otherwise live in
exec_op. We only support byte transfers, but as far as I could tell only
bytes are supported by mem_ops (e.g. every part of the opcode has nbytes).
Signed-off-by: Se
This device has four IOs connected to the SPI flash. Add the appropriate
bindings.
Signed-off-by: Sean Anderson
---
arch/riscv/dts/k210-maix-bit.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/riscv/dts/k210-maix-bit.dts b/arch/riscv/dts/k210-maix-bit.dts
index e4dea205b2..902dcf
We don't always read/write to the FIFO fast enough. Enable clock stretching
for enhanced SPI transfers. This is only possible with DWC SSI devices more
recent than 1.01a. We also need to set the RXFTLR register to tell the
device when to start reciving again. In particular, the default of 0 will
re
This rewrites poll_transfer, dw_writer, and dw_reader.
* We now use RO transfers (instead of always using TR). This eliminates the
need to send out dummy words, and simplifies the transmit logic.
* All parameters (except regs and bits_per_word) are passed explicitly.
* Most parameters have been
These capabilities correspond to SSIC_SPI_MODE of 1, 2, or 3, respectively.
This doesn't do much yet, but it does add support for detection and for
disallowing unsupported modes. Unfortunately, we cannot discriminate
between these modes (only that SSIC_SPI_MODE != 0), so we only assume DUAL
if som
This adds some registers needed for DUAL/QUAD/OCTAL modes. It also adds the
fields in (R)ISR so we can check for over-/under-flow.
Signed-off-by: Sean Anderson
---
drivers/spi/designware_spi.c | 55 ++--
1 file changed, 52 insertions(+), 3 deletions(-)
diff --gi
Since Linux commit cc760f3143f5 ("spi: dw: Convert CS-override to DW SPI
capabilities"), the Linux driver has used capability flags instead of
using ad-hoc flags and functions. This is a great idea, and we should use
it as well.
The .data field in the compatible array has switched from being an
in
DWC_SPI has more than 8 interrupts. Write to the whole IMR to mask
everything.
Signed-off-by: Sean Anderson
---
drivers/spi/designware_spi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 519d6e32bd..29ec1503
This prints some basic metadata about the SPI memory op. This information
may be used to debug SPI drivers (e.g. determining the expected SPI mode).
It is also helpful for verifying that the data on the wire matches the data
intended to be transmitted (e.g. with a logic analyzer). The opcode is
pri
This logs the status register on timeout, so it is easier to determine the
cause of the failure.
Signed-off-by: Sean Anderson
---
drivers/spi/designware_spi.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 742121140d..519
This line should come before the docs for the next function.
Fixes: 7aeedac0153 ("mtd: spi: Port SPI NOR framework from Linux")
Signed-off-by: Sean Anderson
---
include/linux/mtd/spi-nor.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/linux/mtd/spi-nor.h b/include
The sf test command is used to test spi flashes (and spi masters). Printing
the exact error code is very helpful to those debugging the spi stack.
Signed-off-by: Sean Anderson
---
cmd/sf.c | 22 +-
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a/cmd/sf.c b/cmd
This is useful for extending the default functionality.
Signed-off-by: Sean Anderson
---
include/spi-mem.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/spi-mem.h b/include/spi-mem.h
index ca0f55c8fd..1dd556b6cf 100644
--- a/include/spi-mem.h
+++ b/include/spi-mem.h
@@ -236,6 +
If there is an error while erasing SPI flash, no errno is displayed. This
makes it difficult to determine the cause of the error. This change mirrors
the logic for write errors above.
Signed-off-by: Sean Anderson
---
cmd/sf.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --
This series adds support for enhanced SPI modes. It was tested on a K210 (DWC
SSI with QSPI flash).
If anyone has a designware device with QSPI flash attached (especially a DW SSI
APB device), I'd greatly appreciate them testing out this patch series.
Many of the earlier patches in this series ar
Hi Tom,
please pull the master branch from u-boot-sunxi, containing some late
sunxi patches for the 2021.04 merge window:
-
- Allwinner H616 Ethernet support
- sunxi ata debug fix
-
The H616 Ethernet support was used for a long time, but was reworke
gcc -fanalyzer needs the information that a function does not return to
provide accurate information.
os_abort() does not return. Mark it accordingly.
Signed-off-by: Heinrich Schuchardt
---
v2:
use __attribute__((noreturn)) instead of __return
---
include/os.h | 2 +-
1 file changed, 1
gcc -fanalyzer needs the information that a function does not return to
provide accurate information.
os_abort() does not return. Mark it accordingly.
Signed-off-by: Heinrich Schuchardt
---
include/os.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/os.h b/include/o
+Anatolij Gustschin which did not happen automatically, sorry
On Wed, 16 Dec 2020 at 20:52, Simon Glass wrote:
>
> This file contains characters which are not valid in utf-8. This confuses
> dtoc which wants to parse it. They don't really serve any purpose anyway,
> so drop them.
>
> To: U-Boot
It turns out that there is a magic bit in PRCM region which seemingly
makes PLLs work if it's enabled. Sadly, there is no documentation what
it does exactly, so we'll just mimick BSP boot0 behaviour and enable it
before any clock is set up.
Fixes: b18bd53d6cde ("sunxi: introduce support for H616 c
On Sunday 31 January 2021 10:10:56 Simon Glass wrote:
> Hi Pali,
>
> On Sun, 31 Jan 2021 at 10:05, Pali Rohár wrote:
> >
> > On Sunday 31 January 2021 09:51:44 Simon Glass wrote:
> > > Hi Pali,
> > >
> > > On Sun, 31 Jan 2021 at 08:52, Pali Rohár wrote:
> > > >
> > > > On Sunday 31 January 2021
Hi Pali,
On Sun, 31 Jan 2021 at 10:05, Pali Rohár wrote:
>
> On Sunday 31 January 2021 09:51:44 Simon Glass wrote:
> > Hi Pali,
> >
> > On Sun, 31 Jan 2021 at 08:52, Pali Rohár wrote:
> > >
> > > On Sunday 31 January 2021 08:43:19 Simon Glass wrote:
> > > > Hi Pali,
> > > >
> > > > On Sun, 31 Ja
> Date: Sun, 31 Jan 2021 16:29:21 +
> From: Andre Przywara
>
> On Sat, 30 Jan 2021 22:31:06 +0100
> Mark Kettenis wrote:
>
> Hi,
>
> > On implementations that support VHE, the layout of the CPTR_EL2
> > register depends on whether HCR_EL2.E2H is set. Check this bit
> > and and set the apr
On Sunday 31 January 2021 09:51:44 Simon Glass wrote:
> Hi Pali,
>
> On Sun, 31 Jan 2021 at 08:52, Pali Rohár wrote:
> >
> > On Sunday 31 January 2021 08:43:19 Simon Glass wrote:
> > > Hi Pali,
> > >
> > > On Sun, 31 Jan 2021 at 08:04, Pali Rohár wrote:
> > > >
> > > > On Sunday 31 January 2021
Hi Pali,
On Sun, 31 Jan 2021 at 08:52, Pali Rohár wrote:
>
> On Sunday 31 January 2021 08:43:19 Simon Glass wrote:
> > Hi Pali,
> >
> > On Sun, 31 Jan 2021 at 08:04, Pali Rohár wrote:
> > >
> > > On Sunday 31 January 2021 08:49:20 Tom Rini wrote:
> > > > On Sun, Jan 31, 2021 at 01:15:20PM +0100,
On Sat, 30 Jan 2021 22:31:06 +0100
Mark Kettenis wrote:
Hi,
> On implementations that support VHE, the layout of the CPTR_EL2
> register depends on whether HCR_EL2.E2H is set. Check this bit
> and and set the aprropriate bits to enable access to the FP/SIMD
> registers. This allows U-Boot to r
With the recent addition of ACPI generation, the image size has got beyond
its current limit.
Samus does not actually use this, nor x86 emulation for PCI ROMs, so
disable both features.
Signed-off-by: Simon Glass
---
configs/chromebook_samus_defconfig | 1 +
include/configs/chromebook_samus.h
On Sunday 31 January 2021 08:43:19 Simon Glass wrote:
> Hi Pali,
>
> On Sun, 31 Jan 2021 at 08:04, Pali Rohár wrote:
> >
> > On Sunday 31 January 2021 08:49:20 Tom Rini wrote:
> > > On Sun, Jan 31, 2021 at 01:15:20PM +0100, Pali Rohár wrote:
> > > > On Saturday 30 January 2021 22:17:45 Simon Glas
Hi Pali,
On Sun, 31 Jan 2021 at 08:04, Pali Rohár wrote:
>
> On Sunday 31 January 2021 08:49:20 Tom Rini wrote:
> > On Sun, Jan 31, 2021 at 01:15:20PM +0100, Pali Rohár wrote:
> > > On Saturday 30 January 2021 22:17:45 Simon Glass wrote:
> > > > This test is not reliable. Quite often (20%?) it ma
Hi Eugen,
On Sun, 31 Jan 2021 at 02:18, wrote:
>
> On 10.12.2020 02:26, Simon Glass wrote:
> > This function is not needed since the standard device_bind() can be used
> > instead.
> >
> > Signed-off-by: Simon Glass
> > ---
> >
> > arch/x86/cpu/apollolake/spl.c | 2 +-
> > driv
On Sunday 31 January 2021 08:49:20 Tom Rini wrote:
> On Sun, Jan 31, 2021 at 01:15:20PM +0100, Pali Rohár wrote:
> > On Saturday 30 January 2021 22:17:45 Simon Glass wrote:
> > > This test is not reliable. Quite often (20%?) it makes the build fail and
> > > a retry succeeds.
> >
> > This test sho
The following changes since commit 472a716b8fdfd88a27cb675e4ea8e12cb4f79fc3:
configs: Resync with savedefconfig (2021-01-29 13:56:04 -0500)
are available in the Git repository at:
git://git.denx.de/u-boot-usb.git master
for you to fetch changes up to 723fd5668ff2c8dd19e808778b5670d0fa6bdc4
The following changes since commit 472a716b8fdfd88a27cb675e4ea8e12cb4f79fc3:
configs: Resync with savedefconfig (2021-01-29 13:56:04 -0500)
are available in the Git repository at:
git://git.denx.de/u-boot-sh.git master
for you to fetch changes up to 8a73bef338d48095dfb8e805b643d7dd1f6b6d9b
The implementation of pytest_runtest_protocol() must call
pytest_runtest_logstart() and pytest_runtest_logfinish(). This appears to
be necessary even in pytest 5.2.1 judging by the default version of
pytest_runtest_protocol(), but evidently some form of code reorganization
in pytest only made this
On Sun, Jan 31, 2021 at 01:15:20PM +0100, Pali Rohár wrote:
> On Saturday 30 January 2021 22:17:45 Simon Glass wrote:
> > This test is not reliable. Quite often (20%?) it makes the build fail and
> > a retry succeeds.
>
> This test should work. Are there any logs with issues?
I don't see it faili
On Sat, Jan 30, 2021 at 08:30:46PM +0100, Heinrich Schuchardt wrote:
> The following changes since commit 472a716b8fdfd88a27cb675e4ea8e12cb4f79fc3:
>
> configs: Resync with savedefconfig (2021-01-29 13:56:04 -0500)
>
> are available in the Git repository at:
>
> https://gitlab.denx.de/u-boo
Hi Simon,
On Sun, Jan 31, 2021 at 8:36 PM Bin Meng wrote:
>
> When testing QEMU RISC-V 'virt' machine with a 2 GiB memory
> configuration, it was discovered gd->ram_top is assigned to
> value zero in setup_dest_addr().
>
> While 2 GiB QEMU RISC-V 'virt' happens to work with U-Boot today,
> increa
On 10.12.2020 02:26, Simon Glass wrote:
> This function is not needed since the standard device_bind() can be used
> instead.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/x86/cpu/apollolake/spl.c | 2 +-
> drivers/clk/at91/compat.c | 20
>
From: Bin Meng
There are some calls to bdinfo_print_num_l() with parameters that
could be a 64-bit value on a 32-bit system. Change those calls to
use bdinfo_print_num_ll() instead.
Signed-off-by: Bin Meng
---
(no changes since v1)
arch/arm/lib/bdinfo.c | 8
cmd/bdinfo.c |
From: Bin Meng
At present we have bdinfo_print_num() to print unsigned long numbers.
We also have print_phys_addr() which accept numbers that might be
64-bit on a 32-bit platform.
Rename these 2 functions to be clearer:
bdinfo_print_num() => bdinfo_print_num_l()
print_phys_addr() => bdinfo_pri
From: Bin Meng
phys_addr_t and phys_size_t are currently defined as `unsigned long`,
but RV32 supports 34-bit physical address, hence both phys_addr_t and
phys_size_t should be defined to 64-bit using `unsigned long long`.
Signed-off-by: Bin Meng
---
(no changes since v1)
arch/riscv/include/
From: Bin Meng
At present prior_stage_fdt_address is declared as phys_addr_t. On
a 32-bit platform where phys_addr_t can be 64-bit, assigning its
value to gd->fdt_blob which is a pointer, can cause warnings.
Cast it to uintptr_t before the assignment.
Signed-off-by: Bin Meng
Reviewed-by: Simon
From: Bin Meng
priv->iobase was declared as phys_addr_t which is now a 64-bit
address. In a 32-bit build, this causes the following warning
seen when building ftmac100.c:
warning: cast to pointer from integer of different size
[-Wint-to-pointer-cast]
Cast priv->iobase with uintptr_t.
Signed
From: Bin Meng
addr was delcared as fdt_addr_t which is now a 64-bit address.
In a 32-bit build, this causes the following warning seen when
building ax25-ae350.c:
warning: cast to pointer from integer of different size
[-Wint-to-pointer-cast]
Cast addr with uintptr_t.
Signed-off-by: Bin Me
From: Bin Meng
It's possible to have ram_top above 4 GiB in a 32-bit system, hence
we need to declare ram_top as `phys_addr_t`.
Signed-off-by: Bin Meng
Reviewed-by: Simon Glass
---
(no changes since v1)
include/asm-generic/global_data.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
From: Bin Meng
dev_read_addr() returns fdt_addr_t which is now a 64-bit address.
In a 32-bit build, this causes the following warning seen when
building serial_sifive.c:
warning: cast to pointer from integer of different size
[-Wint-to-pointer-cast]
Cast the return value with uintptr_t.
Sig
From: Bin Meng
The min() macro used in dram_init_banksize() requires two elements
to compare have the same type. Let's explicitly cast gd->ram_top.
Signed-off-by: Bin Meng
---
Changes in v2:
- new patch: arm: rockchip: Explicitly cast gd->ram_top in dram_init_banksize()
arch/arm/mach-rockchi
From: Bin Meng
When testing QEMU RISC-V 'virt' machine with a 2 GiB memory
configuration, it was discovered gd->ram_top is assigned to
value zero in setup_dest_addr().
While gd->ram_top should not be declared as type `unsigned long`,
which will be updated in a future patch, the current logic in
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