Enable CONFIG_DM_ETH and CONFIG_DM_MDIO and related configs for the
LS2080AQDS board.
Signed-off-by: Ioana Ciornei
---
configs/ls2088aqds_tfa_defconfig | 8
1 file changed, 8 insertions(+)
diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig
index a3486e4a50
Enable CONFIG_DM_ETH and CONFIG_DM_MDIO and related configs for the
LS1088AQDS board.
Signed-off-by: Ioana Ciornei
---
configs/ls1088aqds_tfa_defconfig | 8
1 file changed, 8 insertions(+)
diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig
index e4e20affec
Add support for selecting the appropriate DTS file depending on the
SERDES protocol used.
The fsl-ls2080a-qds DTS will be used by default if there isn't a DTS
file specifically made for the current SERDES protocol.
This patch adds the necessary DPMAC nodes (DPMAC 1-8) for
protocol 42 (0x2A) on SD
This patch set targets to add support for CONFIG_DM_ETH for the NXP
LS1088AQDS board.
The main focus is on changing the DTS based on the SERDES protocol used.
In order to accomplish this, the MULTI_DTB_FIT feature is employed and
the appropriate DTS is chosed on boot from a list of predefined file
Add support for selecting the appropriate DTS file depending on the
SERDES protocol used. The fsl-ls2088a-qds DTS will be used by default if
there isn't a DTS file specifically made for the current SERDES
protocol.
This patch adds support for the on-board ports (DPMAC 1,2 and 4,5) found
on the SER
In case CONFIG_DM_ETH is enabled, no hardcoding is necessary for DPAA2
Ethernet devices. Compile out any unnecessary setup when CONFIG_DM_ETH
is activated. Also, force the PCI devices to be enumerated at probe
time.
Signed-off-by: Ioana Ciornei
---
board/freescale/ls2080aqds/eth.c| 13 +
This patch set targets to add support for CONFIG_DM_ETH for the NXP
LS2080AQDS board.
The main focus is on changing the DTS based on the SERDES protocol used.
In order to accomplish this, the MULTI_DTB_FIT feature is employed and
the appropriate DTS is chosed on boot from a list of predefined file
In case CONFIG_DM_ETH is enabled, no hardcoding is necessary for DPAA2
Ethernet devices. Compile out any unnecessary setup when CONFIG_DM_ETH
is activated. Also, force the PCI devices to be enumerated at probe
time.
Signed-off-by: Ioana Ciornei
---
board/freescale/ls1088a/eth_ls1088aqds.c | 2 +
On 15.05.20 07:52, Rayagonda Kokatanur wrote:
> Hi Heinrich,
>
> On Fri, May 15, 2020 at 5:27 AM Heinrich Schuchardt
> wrote:
>>
>> On 5/13/20 5:27 PM, Rayagonda Kokatanur wrote:
>>> From: Corneliu Doban
>>>
>>> Add eMMC and GPT support.
>>> - GPT partition list and command to create the GPT add
Currently, the following scenario will rebuild the first commit even
though it is not really necessary - the commit sha or the position in the
patchset did not change:
$ git am
$ tools/buildman/buildman -P -E -W -b master mx6
$ git am
$ tools/buildman/buildman -P -E -W -b master mx6 <- will reb
Hello Patrick,
Am 14.05.2020 um 15:47 schrieb Patrick DELAUNAY:
Hi Heiko
From: Heiko Schocher
Sent: mardi 12 mai 2020 09:32
Hello tom, Patrick,
Am 12.05.2020 um 08:26 schrieb Heiko Schocher:
Hello Tom, Patrick,
Am 27.04.2020 um 08:47 schrieb Heiko Schocher:
Hello Tom, Patrick,
Am 27.04.
On Fri, May 15, 2020 at 1:09 PM Stefan Roese wrote:
>
> Add linefeeds before and after the announce string. This makes the
> output easier to read, especially if some text follows the announce
> message without a specific additional CR.
>
> Signed-off-by: Stefan Roese
> ---
> include/debug_uart.
Hi Heinrich,
On Fri, May 15, 2020 at 5:27 AM Heinrich Schuchardt wrote:
>
> On 5/13/20 5:27 PM, Rayagonda Kokatanur wrote:
> > From: Corneliu Doban
> >
> > Add eMMC and GPT support.
> > - GPT partition list and command to create the GPT added to u-boot
> > environment
> > - eMMC boot commands
Add linefeeds before and after the announce string. This makes the
output easier to read, especially if some text follows the announce
message without a specific additional CR.
Signed-off-by: Stefan Roese
---
include/debug_uart.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Hi Daniel,
On 14.05.20 18:31, Daniel Schwierzeck wrote:
Am 14.05.20 um 14:11 schrieb Jagan Teki:
Use IS_ENABLED to prevent ifdef in sf_probe.c
Cc: Simon Glass
Cc: Vignesh R
Cc: Daniel Schwierzeck
Signed-off-by: Jagan Teki
---
drivers/mtd/spi/sf_internal.h | 10 ++
drivers/mtd/
Hi Heinrich,
On 2020/5/10 上午3:31, Heinrich Schuchardt wrote:
Building with -Wtype-limits yields
tools/rkcommon.c: In function ‘rkcommon_check_params’:
tools/rkcommon.c:158:27: warning: comparison of
unsigned expression < 0 is always false [-Wtype-limits]
158 | if (spl_params.init_size < 0)
On 2020/5/10 上午12:56, Jagan Teki wrote:
Enable PCIe/M.2 support on
- NanoPC-T4
- ROC-RK3399-PC Mezzanine boards.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
---
Changes for v3:
- none
arch/arm/dts/rk3399-u-boot.dtsi | 1 +
configs/nanopc-t4-rk3399_defc
On 2020/5/10 上午12:56, Jagan Teki wrote:
Due to board limitation some SSD's would work
on rock960 PCIe M.2 only with 1.8V IO domain.
So, this patch enables grf io_sel explicitly to
make PCIe/M.2 to work.
Cc: Tom Cubie
Signed-off-by: Jagan Teki
Acked-by: Manivannan Sadhasivam
Reviewed-by:
On 2020/5/10 上午12:56, Jagan Teki wrote:
Yes, it is possible to have a dedicated UCLASS PHY driver
for this Rockchip PCIe PHY but there are some issues on
Generic PHY framework to support the same.
The Generic PHY framework is unable to get the PHY if
the PHY parent is of a different uclass.
S
On 2020/5/10 上午12:56, Jagan Teki wrote:
Yes, most of the high speed peripheral clocks
in rk3399 enabled by default.
But it would be better to handle them via clk
enable/disable API for handling proper reset
conditions like 'usb reset' over command line.
So, enable USB, GMAC clock via enable/d
On 2020/5/10 上午12:56, Jagan Teki wrote:
Enable/Disable the PCIEPHY clk for rk3399.
CLK is clear in both enable and disable functionality.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
---
Changes for v3:
- none
drivers/clk/rockchip/clk_rk3399.c | 6 ++
1 file
On 2020/5/13 下午3:18, Frank Wang wrote:
From: Jagan Teki
Enable USB3.0 Host support for ROC-RK3399-PC boards.
Tested USB3.0 SSD on Type C1 port on board.
=> usb start
starting USB...
Bus usb@fe38: USB EHCI 1.00
Bus usb@fe3c: USB EHCI 1.00
Bus dwc3: usb maximum-speed not found
Registe
On 2020/5/13 下午3:17, Frank Wang wrote:
Configure 'tcphy1' and 'usbdrd_dwc3_1' nodes to support USB3.0 host
for Rockchip RK3399 Evaluation Board.
Signed-off-by: Frank Wang
Reviewed-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3399-evb-u-boot.dtsi | 13 +
On 2020/5/13 下午3:17, Frank Wang wrote:
We have changed to use dwc3 generic driver for usb3.0 host, so the
legacy Rockchip's xHCI driver is not needed, and drop it.
Signed-off-by: Frank Wang
Reviewed-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/usb/host/Kconfig
On 2020/5/13 下午3:17, Frank Wang wrote:
Update evb-rk3399 default config to support USB3.0 Host.
Signed-off-by: Frank Wang
Reviewed-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
---
configs/evb-rk3399_defconfig | 6 ++
1 file changed, 6 insertions(+)
diff --git a/configs
On 2020/5/13 下午3:17, Frank Wang wrote:
RK3399 Type-C PHY is required that must hold whole USB3.0 OTG controller
in resetting to hold pipe power state in P2 before initializing the PHY.
This commit fixed it and added device compatible for rockchip platform.
Signed-off-by: Frank Wang
Signed-off
On 2020/5/13 下午3:17, Frank Wang wrote:
From: Jagan Teki
By default when core sees any transaction error (CRC or overflow) it
replies with terminating retry ACK (Retry=1 and Nump == 0).
Enabling this Auto Retry feature in controller will make the core send
a non-terminanting ACK upon such tra
On 2020/5/13 下午3:15, Frank Wang wrote:
From: Jagan Teki
This patch adds a quirk to disable USB 2.0 MAC linestate check
during HS transmit. Refer the dwc3 databook, we can use it for
some special platforms if the linestate not reflect the expected
line state(J) during transmission.
When use t
On 2020/5/13 下午3:15, Frank Wang wrote:
From: Jagan Teki
Add USB TYPEC PHY driver for rockchip platform.
Referenced from Linux TypeC PHY driver, currently
supporting usb3-port and dp-port need to add it
in the future.
Signed-off-by: Frank Wang
Signed-off-by: Jagan Teki
Reviewed-by: Kever
Hi Jagan, Frank,
On 2020/5/13 下午3:15, Frank Wang wrote:
From: Jagan Teki
Yes, This is changing the actual device tree u2phy
structure but the problem with the current Generic
PHY subsystem is unable to find PHY if the PHY node
is not part of the root structure.
I don't understand for this, i
On 2020/5/13 下午3:13, Frank Wang wrote:
From: Jagan Teki
Add Rockchip USB2PHY driver with initial support.
This will help to use it for EHCI controller in host
mode, and USB 3.0 controller in otg mode.
More functionality like charge, vbus detection will
add it in future changes.
Signed-off-
On 2020/5/13 下午3:13, Frank Wang wrote:
From: Jagan Teki
Due to v5.7-rc1 sync the SD controller nodes in rk3399.dtsi
have SCLK_UPHY0_TCPDCORE, SCLK_UPHY1_TCPDCORE assigned-clocks
which are usually required for Linux and don't require to
handle them in U-Boot.
assigned-clocks = <&cru SCLK_U
On 2020/5/13 下午3:13, Frank Wang wrote:
From: Jagan Teki
Enable/Disable the USB2PHY clk for rk3399.
CLK is clear in enable and set in disable functionality.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/clk/rockchip/clk_rk3399.c | 12
1 fi
On 2020/5/13 下午3:13, Frank Wang wrote:
From: Jagan Teki
Enable/Disable TCPHY clock for rk3399 platform.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/clk/rockchip/clk_rk3399.c | 24
1 file changed, 24 insertions(+)
diff --git
On 2020/5/12 下午6:34, Heiko Stuebner wrote:
From: Heiko Stuebner
In a loading chain SPL -> ATF (->OP-TEE) -> U-Boot, ATF and a subsequent
OP-TEE will re-use the same fdt as the U-Boot target and may need the
information about usable memory ranges.
Especially OP-TEE needs this to initialize dy
On 2020/5/12 下午6:34, Heiko Stuebner wrote:
From: Heiko Stuebner
Parts of later SPL may need RAM information as well, so do full
dram_init() call, which includes the existing dram probing but also
initializes the ram information in gd.
NAK.
I would prefer to use DM interface and leave the d
On 2020/5/14 上午3:15, Urja Rannikko wrote:
Veyrons do not need full pinctrl support for SPL.
The full pinctrl support does nothing when enabled with OF_PLATDATA,
thus was already unused.
This frees about 4kB of SPL size.
Signed-off-by: Urja Rannikko
Reviewed-by: Kever Yang
Thanks,
- Kever
On 2020/5/14 上午3:15, Urja Rannikko wrote:
Apparently speedy was forgotten from this list of veyron devices.
Fixes: 49105fb7ed ("rockchip: add common spl board file")
Signed-off-by: Urja Rannikko
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/mach-rockchip/spl.c | 3 ++-
1 fi
On 2020/5/14 上午3:15, Urja Rannikko wrote:
Previously veyron_init() was called in board_init() context, which is
called after relocation. Moving it to veyron.c used board_early_init_f
which is called way earlier, and causes veyron_init to hang.
Using board_early_init_r instead fixes this.
Fixes
On 2020/5/14 上午3:15, Urja Rannikko wrote:
gd->fdt_blob is null if using OF_PLATDATA in SPL, which causes a hang
after f0921f5098 ("fdt: Sync up to the latest libfdt").
We use the same test that is used in spl_common_init on whether to call
fdtdec_setup to unconditionally avoid linking in the fd
On Fri, May 15, 2020 at 12:41:52AM +0200, Pali Rohár wrote:
> On Saturday 09 May 2020 16:56:10 Tom Rini wrote:
> > On Sat, May 09, 2020 at 06:35:40PM +0200, Pali Rohár wrote:
> > > On Saturday 09 May 2020 21:58:19 Lokesh Vutla wrote:
> > > > On 08/05/20 6:40 PM, Tom Rini wrote:
> > > > > On Fri, Ma
On 5/13/20 5:27 PM, Rayagonda Kokatanur wrote:
> From: Corneliu Doban
>
> Add eMMC and GPT support.
> - GPT partition list and command to create the GPT added to u-boot
> environment
> - eMMC boot commands added to u-boot environment
> - new gpt commands (enumarate and setenv) that are used by b
On 5/15/20 12:27 AM, Heinrich Schuchardt wrote:
> On 5/15/20 12:02 AM, Michael Walle wrote:
>> Am 2020-05-14 23:03, schrieb Heinrich Schuchardt:
>>> On 5/14/20 9:04 PM, Michael Walle wrote:
Am 2020-05-14 20:27, schrieb Heinrich Schuchardt:
> On 5/14/20 2:38 PM, Michael Walle wrote:
>>
On Saturday 09 May 2020 16:56:10 Tom Rini wrote:
> On Sat, May 09, 2020 at 06:35:40PM +0200, Pali Rohár wrote:
> > On Saturday 09 May 2020 21:58:19 Lokesh Vutla wrote:
> > > On 08/05/20 6:40 PM, Tom Rini wrote:
> > > > On Fri, May 08, 2020 at 02:52:55PM +0200, Pali Rohár wrote:
> > > >> On Tuesday
On 5/15/20 12:02 AM, Michael Walle wrote:
> Am 2020-05-14 23:03, schrieb Heinrich Schuchardt:
>> On 5/14/20 9:04 PM, Michael Walle wrote:
>>> Am 2020-05-14 20:27, schrieb Heinrich Schuchardt:
On 5/14/20 2:38 PM, Michael Walle wrote:
> Commit 7a82c3051c8f ("efi_loader: Align runtime section
On 5/14/20 8:50 PM, Michael Walle wrote:
> Am 2020-05-14 20:35, schrieb Heinrich Schuchardt:
>> On 5/14/20 2:38 PM, Michael Walle wrote:
>>> The first argument has to be aligned with EFI_PAGE_SIZE. This alignment
>>> is already checked for external callers but it is not checked for
>>> internal cal
Am 2020-05-14 23:03, schrieb Heinrich Schuchardt:
On 5/14/20 9:04 PM, Michael Walle wrote:
Am 2020-05-14 20:27, schrieb Heinrich Schuchardt:
On 5/14/20 2:38 PM, Michael Walle wrote:
Commit 7a82c3051c8f ("efi_loader: Align runtime section to 64kb")
already aligned the memory region to 64kb, but
On 5/14/20 9:04 PM, Michael Walle wrote:
> Am 2020-05-14 20:27, schrieb Heinrich Schuchardt:
>> On 5/14/20 2:38 PM, Michael Walle wrote:
>>> Commit 7a82c3051c8f ("efi_loader: Align runtime section to 64kb")
>>> already aligned the memory region to 64kb, but it does not align the
>>> actual efi runt
Am 2020-05-14 22:17, schrieb Alexander Graf:
On 14.05.20 20:46, Heinrich Schuchardt wrote:
On 5/14/20 2:38 PM, Michael Walle wrote:
On some architectures, specifically the layerscape, the secondary
cores
wait for an interrupt before entering the spin-tables. This applies
only
to boards which d
On 14.05.20 20:46, Heinrich Schuchardt wrote:
On 5/14/20 2:38 PM, Michael Walle wrote:
On some architectures, specifically the layerscape, the secondary cores
wait for an interrupt before entering the spin-tables. This applies only
to boards which doesn't have PSCI provided by TF-a and u-boot
From: Pengpeng Chen
Add SPI Flash controller driver for Cortina Access
CA SoCs
Signed-off-by: Pengpeng Chen
Signed-off-by: Alex Nemirovsky
CC: Jagan Teki
CC: Vignesh R
ca slfash fixup
---
Changes in v7:
- Replace substring "OPCODE" with "OP" in MACROs to help
reduce code line lengths
Add I2C board support for Cortina Access Presidio Engineering Board
Signed-off-by: Alex Nemirovsky
CC: Heiko Schocher
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
configs/cortina_presidio-asic-emmc_defconfig | 3 ++
From: Jway Lin
Add Cortina Access LED controller support for CA SOCs
Signed-off-by: Jway Lin
Signed-off-by: Alex Nemirovsky
CC: Simon Glass
---
Changes in v7:
- rename OFFSET to SHIFT from macros
- add additinal struct comments
- Reading the DT should really happen in the ofdata_to_plat
Change DT compatibility name to match change in driver's name.
Remove unused io_ds and fifo_mode fields from DT.
Signed-off-by: Alex Nemirovsky
CC: Peng Fan
---
Changes in v7:
- Cleanup typos in commit subject line and description
Changes in v6: None
Changes in v5:
- Rebase on codebase basis
From: Jway Lin
Add LED support for Cortina Access Presidio Engineering Board
Signed-off-by: Jway Lin
Signed-off-by: Alex Nemirovsky
Reviewed-by: Simon Glass
CC: Simon Glass
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- rename DT blink rate symbol
Change
From: Arthur Li
Add I2C controller support for Cortina Access CA SoCs
Signed-off-by: Arthur Li
Signed-off-by: Alex Nemirovsky
CC: Heiko Schocher
CA_I2C: DT binding for I2C controller
DT binding document for Cortina I2C driver
---
Changes in v7:
- Added additional description info in I
Add SPI NOR support for Cortina Access
Presidio Engineering Board
Signed-off-by: Alex Nemirovsky
CC: Jagan Teki
CC: Vignesh R
---
Changes in v7: None
Changes in v6: None
Changes in v5:
- NAND support removed from presidio-asic board DT.
Changes in v4: None
Changes in v3: None
Changes in v2:
This release adds the following drivers and
integrates support into the Cortina Access
Presidio Engineering Board:
CA SoC eMMC/SD controller
CA SoC I2C controller
CA Soc LED controller
CA SPI NAND and NOR controller
Changes in v7:
- Cleanup typos in commit subject line and desc
From: Arthur Li
- Rename DT compatible name
- Remove uneccessary if-statement to support 8-bit buswidth
- Remove redundant error msg
- Use symbolic constants in switch statement
Signed-off-by: Arthur Li
Signed-off-by: Alex Nemirovsky
CC: Peng Fan
---
Changes in v7: None
Changes in v6: None
C
Am 2020-05-14 20:27, schrieb Heinrich Schuchardt:
On 5/14/20 2:38 PM, Michael Walle wrote:
Commit 7a82c3051c8f ("efi_loader: Align runtime section to 64kb")
already aligned the memory region to 64kb, but it does not align the
actual efi runtime code. Thus it is likely, that efi_add_memory_map()
Am 2020-05-14 20:35, schrieb Heinrich Schuchardt:
On 5/14/20 2:38 PM, Michael Walle wrote:
The first argument has to be aligned with EFI_PAGE_SIZE. This
alignment
is already checked for external callers but it is not checked for
internal callers. Unfortunately, most of the time the return value
On 5/14/20 2:38 PM, Michael Walle wrote:
> On some architectures, specifically the layerscape, the secondary cores
> wait for an interrupt before entering the spin-tables. This applies only
> to boards which doesn't have PSCI provided by TF-a and u-boot does the
%s/TF-a/TF-A/, %s/u-boot/U-Boot/
>
čt 14. 5. 2020 v 20:07 odesílatel Rob Herring napsal:
>
> On Thu, Apr 30, 2020 at 6:13 AM Michal Simek wrote:
> >
> > On 29. 04. 20 16:55, Rob Herring wrote:
> > > On Tue, Apr 28, 2020 at 8:51 AM Michal Simek
> > > wrote:
> > >>
> > >> On 28. 04. 20 15:23, Rob Herring wrote:
> > >>> On Wed, Apr
On 5/14/20 2:38 PM, Michael Walle wrote:
> The start parameter must be aligned to EFI_PAGE_SIZE.
>
> Fixes: 5a37a2f0140c ("armv8: ls2080a: Declare spin tables as reserved for efi
> loader")
> Signed-off-by: Michael Walle
> ---
> arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 2 +-
> 1 file changed, 1
On 5/14/20 2:38 PM, Michael Walle wrote:
> The first argument has to be aligned with EFI_PAGE_SIZE. This alignment
> is already checked for external callers but it is not checked for
> internal callers. Unfortunately, most of the time the return value is
> not checked, so scream loud and clear.
Wh
On 5/14/20 2:38 PM, Michael Walle wrote:
> Commit 7a82c3051c8f ("efi_loader: Align runtime section to 64kb")
> already aligned the memory region to 64kb, but it does not align the
> actual efi runtime code. Thus it is likely, that efi_add_memory_map()
> actually adds a larger memory region than the
Use CONFIG_IS_ENABLED to prevent ifdef in sf_probe.c
Cc: Simon Glass
Cc: Vignesh R
Cc: Daniel Schwierzeck
Signed-off-by: Jagan Teki
---
Changes for v2:
- CONFIG_IS_ENABLED() instead of IS_ENABLED()
drivers/mtd/spi/sf_internal.h | 10 ++
drivers/mtd/spi/sf_probe.c| 17 ---
Right now, the sf have common driver to handle
both dm and nodm code, where nondm has spi_flash
probe and dm has U_BOOT_DRIVER for dm spi flash.
Having a common code base for dm and nodm with
ifdef make it difficult to extend functionalities
and also difficult to read.
So, keep them separate and
Handling probing code for a particular uclass between
dm vs nodm always confusing and requires additional
ifdefs to handle them properly.
But, having separate low-level code bases for dm and
nodm can make it easy for the command level to use same
function name to probe the devices. This would inde
On Thu, Apr 30, 2020 at 6:13 AM Michal Simek wrote:
>
> On 29. 04. 20 16:55, Rob Herring wrote:
> > On Tue, Apr 28, 2020 at 8:51 AM Michal Simek
> > wrote:
> >>
> >> On 28. 04. 20 15:23, Rob Herring wrote:
> >>> On Wed, Apr 1, 2020 at 4:23 AM Michal Simek
> >>> wrote:
>
> Hi Rob and
Hi Faiz,
On Thu, 14 May 2020 at 10:40, Faiz Abbas wrote:
>
> Hi Tom,
>
> On 14/05/20 8:29 pm, Tom Rini wrote:
> > On Thu, May 14, 2020 at 01:49:37PM +0530, Faiz Abbas wrote:
> >> Simon,
> >>
> >> On 05/05/20 12:20 pm, Faiz Abbas wrote:
> >>> Hi,
> >>>
> >>> On 04/05/20 6:44 pm, Simon Glass wrote:
On Mon, May 04, 2020 at 02:38:30PM +0200, Jan Kiszka wrote:
> From: Jan Kiszka
>
> The dts dir must exists when running this rule.
>
> That missing dependency broke e.g. "make -j" for the am65x targets.
>
> Fixes: 2f57c95100f2 ("spl: dm: Make it possible for the SPL to pick its own
> DTB from
On Mon, May 04, 2020 at 02:38:31PM +0200, Jan Kiszka wrote:
> From: Jan Kiszka
>
> This avoids needless rebuilding.
>
> Fixes: 2f57c95100f2 ("spl: dm: Make it possible for the SPL to pick its own
> DTB from a FIT")
> CC: Jean-Jacques Hiblot
> Signed-off-by: Jan Kiszka
Applied to u-boot/mast
On Thu, May 14, 2020 at 10:03:33AM +, Patrick DELAUNAY wrote:
> Hi Tom,
>
> Please pull the STM32 related fixes for v2020.07-rc3 = u-boot-stm32-20200514
>
> With the following changes:
> - stm32mp1: migrate MTD and DFU configuration in Kconfig
> - stm32mp1:
On Wed, May 13, 2020 at 03:34:49PM +, Alexey Brodkin wrote:
> Hi Tom,
>
> The following changes since commit 10bca13ea6d9d4b85f80f02c8795227f63240f59:
>
> Merge https://gitlab.denx.de/u-boot/custodians/u-boot-usb (2020-05-12
> 16:20:10 -0400)
>
> are available in the Git repository at:
>
On Thu, May 14, 2020 at 10:51:35AM +0200, Matthias Brugger wrote:
> Hi Tom,
>
> Please have a look at the updates for RPi below.
> I know I'm a bit late in the cycle. I'll try to send my pull requests earlier
> next time, sorry for that.
>
> I just pushed the tag, so the CI is not green yet:
> h
On Thu, 2020-05-14 at 12:10 +0800, Chen-Yu Tsai wrote:
> Hi Kurt
>
> On Tue, May 12, 2020 at 3:00 AM Kurt Miller
> wrote:
> >
> >
> > On Mon, 2020-04-27 at 14:52 +0800, Chen-Yu Tsai wrote:
> > >
> > > From: Chen-Yu Tsai
> > >
> > > This syncs rk3328 device tree files from the Linux kernel n
This is needed to obtain the MAC from EEPROM/OTP only after the final
env is populated, otherwise the ethaddr might be overriden.
Signed-off-by: Marek Vasut
Cc: Claudius Heine
Cc: Harald Seiler
Cc: Ludwig Zenz
Cc: Stefano Babic
---
board/dhelectronics/dh_imx6/dh_imx6.c | 4 ++--
1 file chang
On Thu, May 14, 2020 at 10:02:08AM -0600, Simon Glass wrote:
> On Wed, 13 May 2020 at 03:55, Andy Shevchenko
> wrote:
> > On Tue, May 12, 2020 at 05:22:38PM -0600, Simon Glass wrote:
> > > On Tue, 12 May 2020 at 06:32, Andy Shevchenko
> > > wrote:
> > > > On Tue, May 12, 2020 at 01:55:49PM +0200,
Am 14.05.20 um 14:11 schrieb Jagan Teki:
> Use IS_ENABLED to prevent ifdef in sf_probe.c
>
> Cc: Simon Glass
> Cc: Vignesh R
> Cc: Daniel Schwierzeck
> Signed-off-by: Jagan Teki
> ---
> drivers/mtd/spi/sf_internal.h | 10 ++
> drivers/mtd/spi/sf_probe.c| 17 -
>
Hi,
On Wed, 13 May 2020 at 03:55, Andy Shevchenko
wrote:
>
> On Tue, May 12, 2020 at 05:22:38PM -0600, Simon Glass wrote:
> > Hi Andy,
> >
> > On Tue, 12 May 2020 at 06:32, Andy Shevchenko
> > wrote:
> > >
> > > On Tue, May 12, 2020 at 01:55:49PM +0200, Wolfgang Wallner wrote:
> > >
> > > > > Si
Hi Wolfgang,
On Wed, 13 May 2020 at 07:01, Wolfgang Wallner
wrote:
>
> Hi Simon,
>
> -"Simon Glass" schrieb: -
> >Betreff: [PATCH v2 04/35] irq: Add a method to convert an interrupt
> >to ACPI
> >
> >When generating ACPI tables we need to convert IRQs in U-Boot to the
> >ACPI
> >structur
Hi Faiz,
+Walter Lozano
On Thu, 14 May 2020 at 02:43, Faiz Abbas wrote:
>
> Simon,
>
> On 05/05/20 12:20 pm, Faiz Abbas wrote:
> > Hi,
> >
> > On 04/05/20 6:44 pm, Simon Glass wrote:
> >> Hi Bart,
> >>
> >> On Mon, 4 May 2020 at 01:10, Bartosz Golaszewski wrote:
> >>>
> >>> pt., 1 maj 2020 o 20
On Thu, May 14, 2020 at 08:55:01PM +0530, Faiz Abbas wrote:
> Hi Tom,
>
> On 14/05/20 8:29 pm, Tom Rini wrote:
> > On Thu, May 14, 2020 at 01:49:37PM +0530, Faiz Abbas wrote:
> >> Simon,
> >>
> >> On 05/05/20 12:20 pm, Faiz Abbas wrote:
> >>> Hi,
> >>>
> >>> On 04/05/20 6:44 pm, Simon Glass wrote:
Hi Tom,
On 14/05/20 8:29 pm, Tom Rini wrote:
> On Thu, May 14, 2020 at 01:49:37PM +0530, Faiz Abbas wrote:
>> Simon,
>>
>> On 05/05/20 12:20 pm, Faiz Abbas wrote:
>>> Hi,
>>>
>>> On 04/05/20 6:44 pm, Simon Glass wrote:
Hi Bart,
On Mon, 4 May 2020 at 01:10, Bartosz Golaszewski wrote
On Thu, May 14, 2020 at 01:49:37PM +0530, Faiz Abbas wrote:
> Simon,
>
> On 05/05/20 12:20 pm, Faiz Abbas wrote:
> > Hi,
> >
> > On 04/05/20 6:44 pm, Simon Glass wrote:
> >> Hi Bart,
> >>
> >> On Mon, 4 May 2020 at 01:10, Bartosz Golaszewski wrote:
> >>>
> >>> pt., 1 maj 2020 o 20:32 Tom Rini n
From: Suneel Garapati
Add support for GPIO controllers found on Octeon II/III and Octeon TX
TX2 SoC platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Suneel Garapati
Cc: Simon Glass
Cc: Daniel Schwierzeck
Cc: Aaron Williams
Cc: Chandrakala Chavva
---
RFC -> v1 (Stefan)
- Separated th
Hi Matthias,
On Thu, 14 May 2020 at 02:56, Matthias Brugger wrote:
>
>
>
> On 15/04/2020 21:59, Tom Rini wrote:
> > On Tue, Apr 14, 2020 at 08:23:10PM -0600, Simon Glass wrote:
> >> Hi,
> >>
> >> On Sun, 22 Mar 2020 at 21:16, Simon Glass wrote:
> >>>
> >>> At present the pinctrl nodes are not en
Hi Heiko
> From: Heiko Schocher
> Sent: mardi 12 mai 2020 09:32
>
> Hello tom, Patrick,
>
> Am 12.05.2020 um 08:26 schrieb Heiko Schocher:
> > Hello Tom, Patrick,
> >
> > Am 27.04.2020 um 08:47 schrieb Heiko Schocher:
> >> Hello Tom, Patrick,
> >>
> >> Am 27.04.2020 um 07:16 schrieb Heiko Schoc
Hi Patrick
On 5/14/20 3:00 PM, Patrick Delaunay wrote:
> Update the compatible associated with the STM32 MPU glue
> in the DWC ethernet driver.
>
> The supported compatible is the specific "st,stm32mp1-dwmac"
> as indicated in Linux binding
> Documentation/devicetree/bindings/net/stm32-dwmac.txt
>
On 5/14/20 2:30 PM, Tom Rini wrote:
> Unless we mark the function as 'static inline' it may end up being
> non-inlined by the compiled and result in duplicate functions.
>
> Cc: Marek Vasut
> Cc: Simon Goldschmidt
> Cc: Ley Foon Tan
> Signed-off-by: Tom Rini
Acked-by: Marek Vasut
On 5/14/20 2:30 PM, Tom Rini wrote:
> Enable the new CONFIG_OPTIMIZE_INLINING and CONFIG_SPL_OPTIMIZE_INLINING
> options for this platform. With gcc-9.2 from kernel.org this saves us
> 1784 bytes in U-Boot and 80 bytes in SPL.
>
> Cc: Marek Vasut
> Cc: Chin-Liang See
> Cc: Dinh Nguyen
> Signed
UCLASS_SPI_FLASH driver at driver/mtd/spi is a generic
spi flash driver to probe jedec,spi-nor flash chips.
Technically a probe call in U_BOOT_DRIVER is local to that
driver and not applicable to use it another driver or in
another code.
The apollolake SPL code using the generic probe by adding
e
Signed-off-by: Christian Gmeiner
---
arch/x86/cpu/coreboot/tables.c | 14 ++
arch/x86/include/asm/arch-coreboot/sysinfo.h | 2 ++
arch/x86/include/asm/coreboot_tables.h | 11 +++
3 files changed, 27 insertions(+)
diff --git a/arch/x86/cpu/coreboot/tables.
Update the compatible associated with the STM32 MPU glue
in the DWC ethernet driver.
The supported compatible is the specific "st,stm32mp1-dwmac"
as indicated in Linux binding
Documentation/devicetree/bindings/net/stm32-dwmac.txt
and not the "snps,dwmac-4.20a" only used to the select IP
version.
Hi Simon,
On 14.05.20 14:49, Simon Glass wrote:
OK. Feel free to pull it in if you like as you have my review tag.
Thanks Simon. Since Daniel will be the one pulling the Octeon patchset
once we've reached the necessary ack's, he now knows that he can pull
this one as well. But this will take a
The get_sw_write_prot API is used to get the write-protected
bits of flash by reading the status register and other wards
it's API for reading register bits.
1) This kind of requirement can be achieved using existing
flash operations and flash locking API calls instead of
making a separate f
Hi Stefan,
OK. Feel free to pull it in if you like as you have my review tag.
Regards,
SImon
On Thu, 14 May 2020 at 03:30, Stefan Roese wrote:
>
> Hi Simon,
>
> On 29.04.20 20:04, Simon Glass wrote:
> > On Wed, 29 Apr 2020 at 01:08, Stefan Roese wrote:
> >>
> >> Including the assembler headers
Update the compatible associated with the STM32 MPU glue
in the DWC ethernet driver.
The supported compatible is the specific "st,stm32mp1-dwmac"
as indicated in Linux binding
Documentation/devicetree/bindings/net/stm32-dwmac.txt
and not the "snps,dwmac-4.20a" only used to the select IP
version.
CC: ja...@amarulasolutions.com
вт, 12 мая 2020 г. в 21:25, Roman Stratiienko :
>
> H6 SOC needs additional initialization of PHY registers. Corresponding
> changes can be found in the kernel patch [1].
>
> Without this changes there is no enumeration of 'musb' gadget.
>
> [1] -
> https://git.ker
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