The new PWM driver supports PWM polarity, lock and more functions.
Signed-off-by: David Wu
---
arch/arm/include/asm/arch-rockchip/pwm.h | 17 ++-
drivers/pwm/rk_pwm.c | 139 +++
2 files changed, 131 insertions(+), 25 deletions(-)
diff --git a/arch/arm/in
>-Original Message-
>From: U-Boot On Behalf Of Holger Brunck
>Sent: Monday, November 18, 2019 9:58 PM
>To: u-boot@lists.denx.de
>Cc: Holger Brunck ; Valentin Longchamp
>
>Subject: [U-Boot] [PATCH] ppc/km: enable DM driver support in all defconfigs
>
>This is the first step to use DM supp
On 11/24/19 9:11 PM, Cristian Ciocaltea wrote:
Add support for booting EFI binaries contained in FIT images.
A typical usage scenario is chain-loading GRUB2 in a verified
boot environment.
Signed-off-by: Cristian Ciocaltea
---
cmd/Kconfig | 9 -
cmd/bootefi.c | 2 +-
com
On 11/25/19 2:32 AM, Andre Przywara wrote:
doc/README.drivers.eth seems like a good source for understanding
U-Boot's network subsystem, but is only talking about legacy network
drivers. This is particularly sad as proper documentation would help in
porting drivers over to the driver model.
Rewr
Hi Kever,
As per Rockchip RK3399 TRM V1.4 Part1 RK3399 have
dual-core Cortex-A72 and a quad-core Cortex-A53 +
Cortex-M0 for power management firmware.
So can this feature be enabled for all RK3399 SBC.
or is this meant for specific RK3399 family of processor.
-Anand
_
Add these entries to the ROM so that we can list the contents of an image
with 'binman ls'. The image-header is not essential but does speed up
access.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/x86
Add support for coral which is a range of Apollo Lake-based Chromebook
released in 2017. This also includes reef released in 2016, since it is
based on the same SoC.
Signed-off-by: Simon Glass
---
Changes in v5:
- Add gpio-controller to GPIO nodes
- Comment out GPIOs in the fsp_s node since we d
It is useful to store the mmio base in platdata. It reduces the amount of
casting needed. Update the code and move the struct to the C file at the
same time, as we will need to use with of-platdata.
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4:
- Use priv->pch instead of dev-
Add a GPIO driver which uses the pinctrl driver to access the pad
information. This driver relies on the GPIO nodes being subnodes to the
pinctrl device.
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
.../gpio/intel,apl-gpio.txt
At present if SPL sets up the microcode then it is still included in
U-Boot as well. This is wasteful as microcode is large. Adjust the logic
in the image to prevent this.
Reviewed-by: Bin Meng
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in
This driver handles communication with the systemagent which needs to be
told when U-Boot has completed its init.
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4:
- Add a comment for enable_bios_reset_cpl()
- Tidy up header guards
- use GENMASK() for VTBAR_MASK
Changes in v3:
Add a driver for the Apollo Lake Platform Controller Hub. It does not have
any functionality and is just a placeholder for now.
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4:
- Tidy up header guards
- Update SPI flash protection only in SPL
- apollolake -> Apollo Lake
Changes
Apollo Lake (APL) only supports hardware sequencing. Add support for this
into the SPI driver, as an option.
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4:
- Fix comment for exec_sync_hwseq_xfer()
- apollolake -> Apollo Lake
Changes in v3: None
Changes in v2: None
drivers/
With of-platdata we need to create drivers for particular chips, or at
least drivers that are separate from the standard code, since C structures
are created by dtoc which are private to that driver.
To avoid duplicating the probing code, export this probe function for use
by these drivers.
Signe
Add some fixed IO and mmap addresses for use in the device tree and with
some early-init code.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v5:
- Add ACPI base address and size
Changes in v4:
- Drop TCO_BASE_ADDRESS
- Tidy up header guards
Changes in v3: None
Changes in v2
Add a driver for the Apollo Lake UART. It uses the standard ns16550 device
but also sets up the input clock with LPSS and supports configuration via
of-platdata.
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4:
- Add an extra comment to apl_uart_init()
- Tidy up header guards
-
This subsystem is present on various Intel SoCs.
Add very basic support for taking an lpss device out of reset.
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4:
- Add support for updating power state
- Move this to intel_common
Changes in v3: None
Changes in v2: None
arch/x
Add a driver for the Apollo Lake P-unit (power unit). It is modelled as a
syscon driver since it only needs to be probed.
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4:
- Name this P-Unit instead of power unit, in the commit message
- apollolake -> Apollo Lake
Changes in v3:
Many Intel SoCs require a FIT in order to boot properly. Add an option to
include this and enable it by default.
This term can be confused with FIT (Flat Image Tree) in U-Boot so the
CONFIG option has to include 'X86'.
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4: None
Chang
The fsp_notify() API is the same for FSP1 and FSP2. Move it into a new
common API file.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v5: None
Changes in v4:
- Drop incorrect coreboot reference from header file
Changes in v3: None
Changes in v2: None
arch/x86/include/asm/fs
This incorrectly shortens read operations if there is a maximum write size
but no maximum read size. Fix it.
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/spi/ich.c | 8 +---
1 file changed, 5 insertions(+), 3 deletio
Add a driver for the Apollo Lake pinctrl. This mostly makes use of the
common Intel pinctrl support.
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4:
- Allow pinctrl nodes to have subnodes (i.e. GPIO nodes)
- Drop GPIO_NUM_PAD_CFG_REGS
- Switch over to use pinctrl for pad init/c
Add code to init the system both in TPL and SPL. Each phase has its own
procedure.
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4:
- Switch over to use pinctrl for pad init/config
Changes in v3:
- Adjust fast_spi_cache_bios_region() to avoid using SPI driver
- Drop calls to x8
This function is specific to qemu so it seems best to keep it separate
from the generic code.
Move it out to a new file and update the condition to use if() instead of
Signed-off-by: Simon Glass
---
Changes in v5:
- Add a new patch to move qemu CPU fixup function into its own file
Changes in v
This driver models some sort of interrupt thingy but there are so many
abreviations that I cannot find out what it stands for. Possibly something
to do with interrupts.
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4:
- Tidy up header guards
Changes in v3:
- Add snapshot/restor
These are mostly specific to a particular SoC. Add the definitions for
Apollo Lake.
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4:
- apollolake -> Apollo Lake
Changes in v3:
- Add VBT signature
- Add structures for FSP-S also
- Drop struct fsp_usp_header as it is now in the A
Add this method so that the memory-mapped location of the SPI flash can
be queried.
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4:
- Use the new pci_ofplat_get_devfn() function
Changes in v3: None
Changes in v2: None
drivers/spi/ich.c | 32
With FSP2 we need to run silicon init early after relocation. Add a new
hook for this.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
common/board_r.c | 3 +++
include/init.h | 11 +++
2 files cha
We don't want to include dt-structs.h in header files, so add a note about
that.
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4:
- Add a patch to explain of-platdata and header files
Changes in v3: None
Changes in v2: None
doc/driver-model/of-plat.rst | 6 ++
1 file chan
These drivers are not needed on all platforms. While they are small, it
is useful in TPL to drop then. Add Kconfig control to allow this.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Change 'queensbay' to 'bayt
Move the header files into the right order.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/spi/ich.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/ich.c b/driver
This generic FSP file should include the generic FSP support header, not
the FSP1 version. Fix it.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/x86/lib/fsp/fsp_support.c | 2 +-
1 file changed, 1 inse
With Apollo Lake we need to support a normal cache, which almost never
changes and a much smaller 'variable' cache which changes every time.
Update the code to add a cache type, use an array for the caches and use a
for loop to iterate over the caches.
Signed-off-by: Simon Glass
Reviewed-by: Bin
Add basic plumbing to allow Apollo Lake support to be used.
Signed-off-by: Simon Glass
---
Changes in v5:
- Enable SMP
Changes in v4:
- Enable HAVE_X86_FIT
- Enable INTEL_GPIO
- Switch over to use pinctrl for pad init/config
- Use existing VBT Kconfig option
- apollolake -> Apollo Lake
Changes
The Intel Fast SPI interface is similar to ICH. Add of-platdata support
for this using the "intel,fast-spi" compatible string.
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4:
- Use the new pci_ofplat_get_devfn() function
Changes in v3: None
Changes in v2: None
drivers/spi/ic
This function is only used within the implementation so make it static.
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4:
- Add new patch to make mrccache_update() static
Changes in v3: None
Changes in v2: None
arch/x86/include/asm/mrccache.h | 15 ---
arch/x86/lib
FSP-S is used by the notify call after it has been used for silicon init.
To avoid having to load it again, add a field to store the location.
Reviewed-by: Bin Meng
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/x86/include/
Recent Intel SoCs share a pinctrl mechanism with many common elements. Add
an implementation of this core functionality, allowing SoC-specific
drivers to avoid adding common code.
As well as a pinctrl driver this provides a GPIO driver based on the same
code.
Once other SoCs use this driver we ma
Add support for Apollo Lake to the ICH driver. This involves adjusting the
mmio address and skipping setting of the bbar.
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4:
- apollolake -> Apollo Lake
Changes in v3: None
Changes in v2: None
drivers/spi/ich.c | 19 ++
Newer Intel SoCs have different ways of setting up cache-as-ram (CAR).
Add support for these along with suitable configuration options.
To make the code cleaner, adjust a few definitions in processor.h so that
they can be used from assembler.
Signed-off-by: Simon Glass
---
Changes in v5: None
C
For Apollo Lake we need to take the I2C bus controller out of reset before
using this. Add this functionality to the driver.
Signed-off-by: Simon Glass
Reviewed-by: Heiko Schocher
---
Changes in v5: None
Changes in v4:
- Drop unrelated change metioned by Heiko
- apollolake -> Apollo Lake
Chang
Use debug() instead of printf() to reduce code size and change a bool
return value to the use the 'bool' type. Also drop the global data
declaration since it not actually used. Finally, set the log category.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v5: None
Changes in v4:
We don't generally have enough space to run this, so don't build it into
TPL. This helps reduce the size of TPL.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/x86/lib/Makefile | 2 ++
1 file changed, 2
Add support for a second cache type, for Apollo Lake.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v5: None
Changes in v4:
- apollolake -> Apollo Lake
Changes in v3:
- Move the mrccache_get_region() change into this patch
Changes in v2: None
arch/x86/include/asm/mrccache.
At present we have to have an xfer() method even if it does nothing. This
is not correct, so fix it.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/spi/ich.c| 9 +
drivers/spi/spi-ucl
At present the interrupt table is included in all phases of U-Boot. Allow
it to be omitted, e.g. in TPL, to reduce size.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v5: None
Changes in v4: None
Changes in v3:
- Move write_pirq_routing_table() to avoid 64-bit build error
Cha
In TPL we want to reduce code size and support running with CONFIG_PCI
disabled. Add special code to handle this using a fixed BAR programmed
into the SPI on boot. Also cache the SPI flash to speed up boot.
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4: None
Changes in v3: Non
The memory and silicon init parts of the FSP need support code to work.
Add this for Apollo Lake.
Signed-off-by: Simon Glass
---
Changes in v5:
- Allocate the FSP-S data instead of using the stack
- Rename APOLLOLAKE_USB2_PORT_MAX
Changes in v4:
- Adjust the comment for struct dw_i2c_speed_conf
Use dev_get_driver_data() to obtain the device type. It has the same
effect and is shorter.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/spi/ich.c | 22 +-
1 file changed, 5 ins
Update this uclass to support the needs of the Apollo Lake ITSS. It
supports four operations.
Move the uclass into a separate directory so that sandbox can use it too.
Add a new Kconfig to control it and enable this on x86.
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4:
- Dro
The existing work-around for positioning U-Boot in the ROM when it
actually runs from RAM still exists and there is not obvious way to change
this.
Add a proper Kconfig option to handle this case. This also adds a new bool
property to indicate whether CONFIG_SYS_TEXT_BASE exists.
Signed-off-by: S
At present we don't support loading microcode with FSP2. The correct way
to do this is by adding it to the FIT. For now, disable including
microcode in the image.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v5: None
Changes in v4: None
Changes in v3:
- Drop unnecessary #else
Add a driver for the Apollo Lake SoC. It supports the basic operations and
can use device tree or of-platdata.
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4:
- Fix Makefile copyright message
- Fix incorrect mask check in pmc_gpe_init()
- Switch over to use pinctrl for pad init
Define this symbol so that we can use binman symbols correctly.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/x86/cpu/u-boot-spl.lds | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --gi
Add a bare-bones CPU driver so that CPUs can be probed.
Signed-off-by: Simon Glass
---
Changes in v5:
- Add L2 cache flush function
- Drop SAFETY_MARGIN
Changes in v4:
- Change apollolake to apl
- Tidy up header guards
Changes in v3:
- Add two more defines for the CPU driver
- Expand comments
Include the IFWI section and the FSP-M binary. The FSP-T binary is not
currently used, as CAR is set up manually.
Also drop the FSP binary as this relates only to FSP1.
Reviewed-by: Bin Meng
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4: None
Changes in v3:
- Add FSP-S and V
Add a sandbox driver and PCI-device emulator for p2sb. Also add a test
which uses a simple 'adder' driver to test the p2sb functionality.
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4:
- Drop change to message about a missing uclass
- Drop empty operations struct since p2sb do
If these phases are used we typically want to enable pinctrl in then, so
that pad setup and GPIO access are possible.
Signed-off-by: Simon Glass
---
Changes in v5:
- Correct build error in chromebook_samus_tpl
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/Kconfig
Add loaders for SPL and TPL so that the next stage can be loaded from
memory-mapped SPI or, failing that, the Fast SPI driver.
Signed-off-by: Simon Glass
---
Changes in v5:
- Add L2 cache flush functoin
- Drop SAFETY_MARGIN
Changes in v4: None
Changes in v3:
- Add a driver for APL SPI for TPL
This is used on several boards so add it to the common file. Also add a
useful power-limit value while we are here.
Reviewed-by: Bin Meng
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/x86/include/asm/arch-broadwell/cpu.h
At present binman does not support updating a device tree that is part of
U-Boot (i.e u-boot.bin). Separate the entries into two so that we can get
updated entry information. This makes binman_entry_find() work correctly.
Do the same for SPL tool.
In both cases, group the two parts into a section
Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports
various child devices. It supposed both device tree and of-platdata.
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4:
- Detect zero mmio address
- Use BIT() macro bit more
- apollolake -> Apollo Lake
Chang
On x86 platforms the timer is reset to 0 when the SoC is reset. Having
this as the timer base is useful since it provides an indication of how
long it takes before U-Boot is running.
When U-Boot sets the timer base to something else, time is lost and we
no-longer have an accurate account of the ti
For Apollo Lake SPL is run from CAR (cache-as-RAM) which is in a different
location from where SPL must be placed in ROM. In other words, although
SPL runs before SDRAM is set up, it is not execute-in-place (XIP).
Add a Kconfig option for the ROM position.
Signed-off-by: Simon Glass
Reviewed-by:
This driver the LPC and provides a few functions to set up LPC features.
These should probably use ioctls() or perhaps, better, have specific
uclass methods.
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4:
- Add comments for exported functions
- Tidy up header guards
- Use 'Apo
At present we reuse the mrc_output char * to also point to the cache
record after it has been set up. This is confusing and doesn't save much
data space.
Add a new mrc_cache member instead.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v5: None
Changes in v4: None
Changes in
Add a simple PMC for sandbox to permit tests to run.
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4: None
Changes in v3:
- Rename power-mgr uclass to acpi-pmc
- Tidy up Makefile rules to reduce duplication
Changes in v2: None
arch/Kconfig | 2 +
arch/s
Reduce the size of the probe function but putting this code into its own
function.
Also remove the assumption that the PCH is always a parent of the SPI
controller, as this is not the case APL platforms. Use driver model to
find the PCH instead.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
It is annoying to have some of the init code in a different part of the
file. Move ich_init_controller() to just above probe() to keep things
together.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/
We don't normally need this on x86 unless the size of SPI flash devices is
larger than 16MB. This can be enabled by particular SoCs as needed, since
it adds to code size.
Drop the default enabling of this option on x86.
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4: None
Chan
Both versions of FSP can use the same graphics support, so move it into
the common directory.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/x86/lib/fsp/Makefile | 3 +++
arch/x86/lib/{f
This function is a bit confusing at present due to the error handling.
Update it to remove the goto, returning errors as they happen.
While we are here, use hex for the data size since this is the norm in
U-Boot.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v5: None
Changes
Set up MTRRs for the FSP SDRAM regions to improve performance.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v5:
- Fix FST typo
Changes in v4: None
Changes in v3:
- Move mtrr_add_request() call into this patch
Changes in v2: None
arch/x86/lib/fsp/fsp_dram.c | 5 +
1 fi
At present with fsp a single DRAM bank is added which extends to the
whole size of memory. However there is typically only 2GB of memory
available below the 4GB boundary, and this is what is used by U-Boot while
running in 32-bit mode.
Scan the tables to set the banks correct. The first bank is se
At present the records are 4KB in size. This is unnecessarily large when
the SPI-flash erase size is 256 bytes. Reduce it so it will be more
efficient with Apollo Lake's 24-byte variable-data record.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v5: None
Changes in v4:
- apol
We don't want to pull in libfdt if of-platdata is being used, since it
reduces the available code-size saves. Also, SPI flash is seldom needed
in TPL.
Drop these options.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v5: None
Changes in v4: None
Changes in v3:
- Don't imply S
This driver models the hostbridge as a northbridge. It simply sets up the
graphics BAR. It supports of-platdata.
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4:
- Avoid needing to know internals of pinctrl in this driver
- Move code to pinctrl driver
- Switch over to use pinctr
The current 'fsp' command only works with FSP1. Update it to handle FSP2
as well. Convert everything to hex which is what U-Boot uses.
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4:
- Explain why FSP-M cannot be shown
- Use hex for size values also
Changes in v3:
- Convert co
The FSP-S may do this but at least for coral it does not. Set this up so
that graphics is not deathly slow.
It isn't clear whether the FSP is expected to set up MTRR. It is not
mentioned in the APL FSP document.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v5: None
Changes i
Drivers are not allowed to use static data since they may be used in SPL
where BSS is not available.
It is possible that driver model may provide support for numbering devices
in the future. But for now, move this to global_data.
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4:
Change the algorithm to first find the flash device then read the
properties using the livetree API. With this change the device is not
probed so this needs to be done in mrccache_save().
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4: None
Changes in v3:
- Update mrccache live
Add support for some important configuration options and FSP memory init.
The memory init uses swizzle tables from the device tree.
Support for the FSP_S binary is also included.
Bootstage timing is used for both FSP_M and FSP_S and memory-mapped SPI
reads.
Signed-off-by: Simon Glass
---
Chang
This function needs to be different for FSP2, so move the existing
function into the fsp1 directory. Since it is only called from one file,
drop it from the header file.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v
The Primary-to-Sideband bus (P2SB) is used to access various peripherals
through memory-mapped I/O in a large chunk of PCI space. The space is
segmented into different channels and peripherals are accessed by
device-specific means within those channels. Devices should be added in
the device tree as
Add a simple sandbox test for this uclass.
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4:
- Drop itss uclass change in Makefile (now in previous patch)
- Drop sandbox defconfig change now that p2sb change is correct
- Enable IRQ for sandbox64 too to avoid build error
Changes
When reseting sandbox for tests, disable mmio support since that is the
default state.
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4:
- Split out into a separate patch
Changes in v3: None
Changes in v2: None
arch/sandbox/cpu/state.c | 1 +
1 file changed, 1 insertion(+)
di
These warnings appear every thing sandbox is run (see below) and dwarf the
actual useful output. Suppress them in two ways:
1. For the mismatch warnings, only set the ethaddr environment
variables when running tests.
2. For the 'MAC address from ROM' warning, never print this on sandbox.
Signed-
Add a simple command to show information about the PMC.
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4: None
Changes in v3:
- Rename power-mgr uclass to acpi-pmc
Changes in v2: None
arch/Kconfig | 1 +
cmd/Kconfig | 8 ++
cmd/Makefile | 1 +
cmd/pmc.c| 81 +++
When device-tree compilation fails it is sometimes tricky to see which
line is broken, since the input file to dtc is a pre-processed version
of the device tree.
Add a line that points to the file that needs to be checked:
When the error is in the main .dts file, output is something like this:
We don't expect an exception in TPL and don't need to set up interrupts in
TPL. Drop this whole file.
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4:
- Drop the whole interrupt file for TPL
Changes in v3: None
Changes in v2: None
arch/x86/cpu/i386/Makefile | 2 ++
1 file cha
At present the early timer init happens as soon as driver mode is set up.
This makes it impossible to do any in that needs driver model but must run
before devices are problem (as needed with Intel's FSP-S, for example).
In any case it is not a good idea to tie probing of particular drivers too
cl
It is now possible to obtain the memory map for a SPI controllers instead
of having it hard-coded in the device tree. Update the code to support
this.
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Use SPI mmap() instead of SPI flash
This reverts commit 96ac4def8b6686de8566b91419ce98cd5765079b.
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/sandbox/cpu/state.c | 12 ++--
arch/sandbox/include/asm/state.h | 5 +
cmd/nvedit.c
We don't need to know every detail about the CPU in TPL. Drop some
superfluous functions to reduce code size. Add a simple CPU detection
algorithm which just supports Intel and AMD, since we only support TPL
on Intel, so far.
Signed-off-by: Simon Glass
---
Changes in v5: None
Changes in v4:
- Dr
This should take account of the end of the new cache record since a record
cannot extend beyond the end of the flash region. This problem was not
seen before due to the alignment of the relatively small amount of MRC
data.
But with Apollo Lake the MRC data is about 45KB, even if most of it is
zero
Most of the timer-calibration methods are not needed on recent Intel CPUs
and just increase code size. Add an option to use the known-good way to
get the clock frequency in TPL. Size reduction is about 700 bytes.
Note that version 1 of this commit caused bootstage to crash since the CPU
was not id
Intel x86 SoCs have a power manager/controller which handles several
power-related aspects of the platform. Add a uclass for this, with a few
useful operations.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v5: None
Changes in v4:
- Fix alpha order in Kconfig
- Switch over to
These functions are used by code outside the network support, so move them
to lib/ to be more accessible.
Without this, the functions are only accessible if CONFIG_NET is defined.
Many boards do not enable that option but still want to do checksums in
this format.
Fix up a few code-style nits whi
This is hacked into the driver at present. It seems better to have it as
a separate driver that uses the base driver. Create a new file and put
the X86 code into it.
Actually the Baytrail settings should really come from the device tree.
Note that 'has_max_speed' is added as well. This is current
At present PCI auto-configuration happens in U-Boot both before and after
relocation. This is a waste of time and may mess up static addresses used
in board_init_f(). Adjust the code to supporting doing auto-configuration
once, after relocation, under control of a device-tree property.
This is nee
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