On Mon, Sep 17, 2018 at 2:29 PM Bin Meng wrote:
>
> On Tue, Sep 11, 2018 at 6:33 PM Georgii Staroselskii
> wrote:
> >
> > This interface will be used to configure properly some pins on
> > Merrifield that are shared with SCU.
> >
> > scu_ipc_raw_command() writes SPTR and DPTR registers before sen
On Tue, Sep 11, 2018 at 6:33 PM Georgii Staroselskii
wrote:
>
> This interface will be used to configure properly some pins on
> Merrifield that are shared with SCU.
>
> scu_ipc_raw_command() writes SPTR and DPTR registers before sending
> a command to SCU.
>
> This code has been ported from Linux
On Fri, Sep 7, 2018 at 3:35 PM Bin Meng wrote:
>
> On Fri, Sep 7, 2018 at 3:30 PM Christian Gmeiner
> wrote:
> >
> > This will add support for a baud rate of 57600.
> >
> > Signed-off-by: Christian Gmeiner
> > ---
> > include/configs/x86-common.h | 2 --
> > 1 file changed, 2 deletions(-)
> >
>
On Mon, Sep 3, 2018 at 1:08 PM Jagdish Gediya wrote:
>
> This entry contains the PowerPC mpc85xx boot page and resetvec
> sections.
>
> Signed-off-by: Jagdish Gediya
> ---
> Changes for v2:
> - Updated README for new binman entry
> - Added test
>
> Changes for v3:
> - Chan
On Mon, Sep 3, 2018 at 1:08 PM Jagdish Gediya wrote:
>
> 'board_fdt_blob_setup' function sets up fdt blob at '&_end' so
> define '_end' symbol in mpc85xx lds files.
>
> Signed-off-by: Jagdish Gediya
> ---
> Changes for v2:
> - Define '_end' symbol in lds file instead of defining new
>
On 09/17/2018 04:45 AM, Alexander Graf wrote:
> The UEFI spec mandates that runtime sections are 64kb aligned to enable
> support for 64kb page size OSs.
Where in the spec did you find this? I could neither find the term
"runtime section" nor "64kb" in the text.
Best regards
Heinrich
>
> This
On 09/17/2018 04:45 AM, Alexander Graf wrote:
> The UEFI spec mandates that runtime sections are 64kb aligned to enable
%s/kb/ kiB/g
The spec requires a multiple of 64,000 not of 65,536.
> support for 64kb page size OSs.
>
> This patch ensures that we extend the runtime section to 64kb to be spec
Hi Jagan,
Could you please take some time to look into this mail and let me now your
comments.
Thanks,
Siva
> -Original Message-
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Siva
> Durga Prasad Paladugu
> Sent: Wednesday, September 12, 2018 2:47 PM
> To: u-boot@list
Now that we already disable the "strict-aliasing" globally, remove
the duplicates in the nds32/riscv/x86 arch-specific Makefiles.
Signed-off-by: Bin Meng
Reviewed-by: Rick Chen
---
arch/nds32/config.mk | 2 +-
arch/riscv/config.mk | 2 +-
arch/x86/config.mk | 1 -
3 files changed, 2 inserti
The -fstrict-aliasing option is implicitly enabled at levels -O2,
-O3, -Os by GCC. This option allows the compiler to assume the
strictest aliasing rules applicable to the language being compiled.
For example, the practice of reading from a different union member
than the one most recently written
Hi Lukas,
On Mon, Sep 17, 2018 at 5:02 AM Auer, Lukas
wrote:
>
> Hi Bin,
>
> On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> > This adds QEMU RISC-V 'virt' board target support, with the hope of
> > helping people easily test U-Boot on RISC-V.
> >
> > The QEMU virt machine models a generic R
Hi Lukas,
On Mon, Sep 17, 2018 at 5:09 AM Auer, Lukas
wrote:
>
> Hi Bin,
>
> On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> > We don't have a reset method on any RISC-V board yet. Instead of
> > adding the same 'unsupported' message for each CPU variant it might
> > make more sense to add a
Hi Lukas,
On Mon, Sep 17, 2018 at 4:54 AM Auer, Lukas
wrote:
>
> Hi Bin,
>
> On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> > This adds a helper routine to print CPU information. Currently
> > it prints all the instruction set extensions that the processor
> > core supports.
> >
> > Signed-
The UEFI spec mandates that runtime sections are 64kb aligned to enable
support for 64kb page size OSs.
This patch ensures that we extend the runtime section to 64kb to be spec
compliant.
Signed-off-by: Alexander Graf
---
lib/efi_loader/efi_memory.c | 7 ---
1 file changed, 4 insertions(+),
We currently do not combine memory entries that are adjacent and have
the same attributes. The problem with that is that our memory map can
easily grow multiple hundreds of entries in a simple UEFI Shell
environment.
So let's make sure we always combine all entries to make the memory
map as small
On Sun, Sep 16, 2018 at 6:16 PM Otavio Salvador wrote:
>
> This upgrades U-Boot to 2018.09 release and drop the backported
> security fixes which are now included upstream.
>
> Signed-off-by: Otavio Salvador
When I mentioned, on IRC, about this bump to Marek, he mentioned that
there is a regress
This upgrades U-Boot to 2018.09 release and drop the backported
security fixes which are now included upstream.
Signed-off-by: Otavio Salvador
---
.../u-boot/files/CVE-2018-1000205-1.patch | 59
.../u-boot/files/CVE-2018-1000205-2.patch | 143 --
..._2018.07.in
Hi Bin,
On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> We don't have a reset method on any RISC-V board yet. Instead of
> adding the same 'unsupported' message for each CPU variant it might
> make more sense to add a generic do_reset function for all CPU
> variants to lib/, similar to the on
Hi Bin,
On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> This adds QEMU RISC-V 'virt' board target support, with the hope of
> helping people easily test U-Boot on RISC-V.
>
> The QEMU virt machine models a generic RISC-V virtual machine with
> support for the VirtIO standard networking and b
On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> RISC-V is a pretty new architecture and should support DM and
> OF_CONTROL by default.
>
> Signed-off-by: Bin Meng
>
Reviewed-by: Lukas Auer
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On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> There are quite a lot of mixed tabs and spaces in the ae350.dts.
> Clean them up.
>
> Signed-off-by: Bin Meng
>
Reviewed-by: Lukas Auer
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On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> Currently start.S is inside arch/riscv/cpu/ax25/, but it can be
> common for all RISC-V targets.
>
> Signed-off-by: Bin Meng
>
Reviewed-by: Lukas Auer
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h
On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> So far this is hardcoded to zero, and we should read the value from
> mhartid CSR and pass it to Linux kernel.
>
> Suggested-by: Lukas Auer
> Signed-off-by: Bin Meng
>
>
Reviewed-by: Lukas Auer
_
On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> There is no reason to keep two versions of CSR read/write defines
> in encoding.h. We already have one set of defines in csr.h, which
> is from Linux kernel, and let's drop the one in encoding.h.
>
> Signed-off-by: Bin Meng
>
>
Reviewed-by:
Hi Bin,
On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> This adds a helper routine to print CPU information. Currently
> it prints all the instruction set extensions that the processor
> core supports.
>
> Signed-off-by: Bin Meng
> ---
>
> Changes in v2: None
>
> arch/riscv/Makefile
On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> At present the compiler flag against which architecture and abi
> variant the riscv image is built for is not explicitly indicated
> which means the default compiler configuration is used. But this
> does not work if we want to build a different
On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> There are several coding style issues in the linker script. Fix them.
>
> Signed-off-by: Bin Meng
>
Reviewed-by: Lukas Auer
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On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> The linker script can be shared by all RISC-V targets. Move it to
> a common place.
>
> Signed-off-by: Bin Meng
>
Reviewed-by: Lukas Auer
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On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> Since the mach_id is not used by RISC-V, remove it.
>
> Signed-off-by: Bin Meng
>
Reviewed-by: Lukas Auer
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On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> The first argument of Linux kernel is the risc-v core hart id,
> from which the kernel is booted from. It is not the mach_id,
> which seems to be copied from arm.
>
> While we are here, this also changes the Linux kernel entry
> parameters' type
On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> This was copied from ARM, and does not apply to RISC-V. While we
> are here, bootm.h is eventually removed as its content is only
> the inclusion of setup.h.
>
> Signed-off-by: Bin Meng
>
Reviewed-by: Lukas Auer
_
On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> It's RISC-V that is the official name, not RISCV.
>
> Signed-off-by: Bin Meng
>
Reviewed-by: Lukas Auer
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Hi Bin,
Apologize for the delay. I came back from vacation a few days ago.
On Tue, Sep 04, 2018 at 12:00:14PM +0800, Bin Meng wrote:
> Hi Eugeniu,
>
> On Sat, Sep 1, 2018 at 6:59 PM Eugeniu Rosca wrote:
[..]
> > Just wanted to let you know that coreboot folks are going through
> > similar disc
Migrate SYS_I2C_TEGRA from headers to Kconfig
Signed-off-by: Peter Robinson
Cc: Tom Warren
Cc: Stephen Warren
Cc: Heiko Schocher
Cc: Marcel Ziswiler
Cc: peter.ch...@data61.csiro.au
Cc: Lucas Stach
Cc: Stefan Agner
Cc: Alban Bedel
Cc: Allen Martin
---
configs/apalis-tk1_defconfig | 1
All other Tegra devices that define USB_EHCI_TXFIFO_THRESH use hex
representation, fix tegra20 to be the same format.
Signed-off-by: Peter Robinson
Cc: Tom Warren
Cc: Stephen Warren
---
include/configs/tegra20-common.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include
Migrate USB_EHCI_TEGRA from headers to Kconfig
Signed-off-by: Peter Robinson
Cc: Tom Warren
Cc: Stephen Warren
Cc: Marek Vasut
Cc: Marcel Ziswiler
Cc: peter.ch...@data61.csiro.au
Cc: Lucas Stach
Cc: Stefan Agner
Cc: Alban Bedel
Cc: Allen Martin
---
configs/apalis-tk1_defconfig | 1 +
co
The CONFIG_KEYBOARD does nothing as it's legacy and unused
so just drop it from the config.
Signed-off-by: Peter Robinson
Cc: Tom Warren
Cc: Stephen Warren
Cc: Allen Martin
---
include/configs/nyan-big.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/configs/nyan-big.h b/include
Migrate TEGRA_KEYBOARD from headers to Kconfig, only the seaboard uses it but we
drop CONFIG_KEYBOARD as the driver doesn't use the legacy drv_keyboard_init.
Signed-off-by: Peter Robinson
Cc: Tom Warren
Cc: Stephen Warren
---
configs/seaboard_defconfig | 1 +
drivers/input/Kconfig| 6
There's a number of dangling comments in various tegra configs post migrations
of various configs so lets clean them up.
Signed-off-by: Peter Robinson
Cc: Tom Warren
Cc: Stephen Warren
Cc: Marcel Ziswiler
Cc: Tom Warren
Cc: Stephen Warren
Cc: peter.ch...@data61.csiro.au
Cc: Lucas Stach
Cc:
The following patches are a few cleanups to dangling comments from Kconfig
cleanups and migrations of SYS_I2C_TEGRA, USB_EHCI_TEGRA and TEGRA_KEYBOARD.
There's also a couple of other minors fixes and cleanups as well.
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Hi Rick,
On Tue, Sep 11, 2018 at 12:50 PM Bin Meng wrote:
>
> This series adds QEMU RISC-V 'virt' board target support, with the
> hope of helping people easily test U-Boot on RISC-V.
>
> Some existing RISC-V codes have been changed to make it easily to
> support new targets. Some spotted coding
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