option from spi_slave {} never used so drop the same.
Signed-off-by: Jagan Teki
---
include/spi.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/spi.h b/include/spi.h
index 8c4b882..08c7480 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -104,7 +104,6 @@ struct spi_slave {
Add uart2-pins for A64 SOC.
Signed-off-by: Jagan Teki
---
arch/arm/dts/sun50i-a64.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi
index 65a344d..93c2d01 100644
--- a/arch/arm/dts/sun50i-a64.dtsi
+++ b/arch/arm/dts/sun50i-a
Order sun50i-h5-orangepi-prime.dts nodes in alphabetic
Signed-off-by: Jagan Teki
---
arch/arm/dts/sun50i-h5-orangepi-prime.dts | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/dts/sun50i-h5-orangepi-prime.dts
b/arch/arm/dts/sun50i-h5-orangepi-prime.d
Add USB host node, ehci1 and usbphy for bananapi m64
Signed-off-by: Jagan Teki
---
arch/arm/dts/sun50i-a64-bananapi-m64.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/dts/sun50i-a64-bananapi-m64.dts
b/arch/arm/dts/sun50i-a64-bananapi-m64.dts
index 02db114..31ae1f9 1006
Hi Vasily,
On Tue, 28 Nov 2017 22:33:27 -0800
Vasily Khoruzhick anars...@gmail.com wrote:
> These are actually different bits, and since some monitors (Benq BL2420PT)
> have modes with different HSYNC and VSYNC polarity, we should set them
> independently
>
> Tested on Pine64-LTS with Benq BL242
On 24.11.2017 23:35, Simon Glass wrote:
> Hi Simon,
>
> On 20 November 2017 at 22:38, Goldschmidt Simon
> wrote:
>> Hi,
>>
>>> Simon Glass wrote:
>>> On 10 November 2017 at 07:17, Goldschmidt Simon >> fuchs.com> wrote:
This drops the limit that fpga is only loaded from FIT images for Xilinx.
Hi Philipp:
On 2017年11月28日 21:59, Philipp Tomsich wrote:
+sjg
On Tue, 28 Nov 2017, Andy Yan wrote:
Most the current rockchip based boards use adc channel
1 detect the download key, but there are also some
boards like rv1108 based plaform use adc channel 0.
So we parse the adc channel from dt
These are actually different bits, and since some monitors (Benq BL2420PT)
have modes with different HSYNC and VSYNC polarity, we should set them
independently
Tested on Pine64-LTS with Benq BL2420PT monitor.
Signed-off-by: Vasily Khoruzhick
---
drivers/video/sunxi/sunxi_dw_hdmi.c | 14 +---
On Tue, Nov 28, 2017 at 07:14:29PM +0100, Stefano Babic wrote:
>On 28/11/2017 13:31, Peng Fan wrote:
>> Add clock driver to support i.MX8M.
>>
>> There are two kind PLLs, FRAC pll and SSCG pll. ROM already
>> configured SYS PLL1/2, we only need to configure the output.
>> ocotp/i2c/pll decoding an
In Linux, the warning messages are printed out by pr_warn().
We can use Linux-like log functions in tree-wide.
Signed-off-by: Masahiro Yamada
---
drivers/firmware/psci.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c
Remove unnecessary DECLARE_GLOBAL_DATA_PTR and header includes.
has been replaced with and .
Signed-off-by: Masahiro Yamada
---
arch/arm/mach-uniphier/board_init.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-uniphier/board_init.c
b/arch/arm/mach-
On Tue, Nov 28, 2017 at 06:40:40PM +0100, Stefano Babic wrote:
>Hi Peng,
>
>On 28/11/2017 13:31, Peng Fan wrote:
>> Add register definition header file for i.MX8M
>>
>> Signed-off-by: Peng Fan
>> ---
>> arch/arm/include/asm/arch-mx8m/imx-regs.h | 298
>> ++
>> 1 file
Hello Marek,
Am 29.11.2017 um 03:48 schrieb Marek Vasut:
Add driver for the RCar IIC or DVFS I2C controller. This driver is based
on the SH I2C driver, but supports DM and DT probing as well as modern
I2C framework API.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
drivers/i2c/Kconfi
Hi Stefano,
On Tue, Nov 28, 2017 at 06:15:30PM +0100, Stefano Babic wrote:
>Hi Peng,
>
>On 28/11/2017 13:31, Peng Fan wrote:
>> Add i.MX8M into Kconfig, create a new folder mx8m
>> dedicated for i.MX8M.
>>
>> Signed-off-by: Peng Fan
>> ---
>> arch/arm/Kconfig | 8
>> arc
Hi Stefano,
> -Original Message-
> From: Stefano Babic [mailto:sba...@denx.de]
> Sent: Tuesday, November 28, 2017 10:46 PM
> To: Peng Fan ; sba...@denx.de; Fabio Estevam
>
> Cc: u-boot@lists.denx.de; van.free...@gmail.com
> Subject: Re: [PATCH 00/23] imx: add i.MX8M support and i.MX8MQ EV
On 11/28/2017 05:19 AM, Peng Fan wrote:
> For external data, FIT has a optional property "data-position" which
> can set the external data to a fixed offset to FIT beginning.
> Add the support for this property in SPL FIT.
>
> Signed-off-by: Ye Li
> Signed-off-by: Peng Fan
> Cc: Simon Glass
> C
On 28.11.2017 14:46, Michal Simek wrote:
> On 28.11.2017 10:08, Goldschmidt Simon wrote:
>> Simon Goldschmidt wrote:
>>> Hi Simon,
>>>
>>> Simon Glass wrote:
I see that, although it is adding to the fpga header so presumably
making it harder for someone to move this over.
>>>
>>> Yes, I'm
On Tue, Nov 28, 2017 at 10:13:30PM +0100, Daniel Schwierzeck wrote:
> Hi Tom,
>
> The following changes since commit 73a01d90c0b2ed2527283f289f73d69ef52cafa5:
>
> test: Correct operation when tests pass (2017-11-27 23:05:22 -0500)
>
> are available in the Git repository at:
>
> git://git.d
On Wed, Nov 29, 2017 at 12:41:12AM +0900, Masahiro Yamada wrote:
> Hi Tom,
>
> This is a retry for the NAND + UniPhier pull request.
>
> I inserted
> http://patchwork.ozlabs.org/patch/842106/
>
> The build test of openrd boards passed.
>
>
>
>
> The following changes since commit 73a01d90c0
The .probe_chip function is supposed to probe an i2c device on the bus to
determine whether a device is answering to a particular address.
at91_i2c_probe_chip() did not do anything resembling this and always
returned 0.
It looks as though at91_i2c_probe_chip() was intended to be a .probe
function
The driver must wait for TXRDY after each byte is pushed into
the i2c FIFO before pushing the next byte. Previously this was
not done for the first byte, causing a race condition with zeros
sometimes being sent for the next byte (which is typically the
first actual data byte).
Signed-off-by: Alan
Two patches to fix the I2C on SAMA5D3. The first fixes a race
condition in pushing TX data to the hardware, and the second
removes an errant probe_chip function which prevents devices from
being probed properly
These have been tested on master and on 2017.07
Alan Ott (2):
i2c: at91_i2c: Wait fo
[primary] Check MMC 0:1 for /extlinux/extlinux.conf and boot
[fallback 1] Check MMC 0:1 zImage and run mmcbootz
[fallback 2] Check MMC 0:1 uImage and run mmcboot
[fallback 3] Check NAND partitions and run nandboot
If 'extlinux.conf' is not found on MMC 0, the previous boot behavior is
followed.
S
On 11/29/2017 03:58 AM, Tom Rini wrote:
> On Wed, Nov 29, 2017 at 03:45:45AM +0100, Marek Vasut wrote:
>
>> It is legal to have multiple /memory nodes in a device tree . Currently,
>> fdtdec_setup_memory_size() only supports parsing the first node . This
>> patch extends the function such that if
Add code to handle single pins nodes from DT in addition to already
support groups handling.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
drivers/pinctrl/renesas/pfc.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/drivers/pinctrl/renesas/pfc.c b/dr
Add hook into the PFC driver to allow the GPIO driver to toggle
GPSR registers into GPIO mode when GPIO is requested.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
drivers/pinctrl/renesas/pfc.c| 29 +
drivers/pinctrl/renesas/sh_pfc.h | 1 +
2 files change
Rework the ULCB CPLD driver and make it into a sysreset driver,
since that is what the ULCB CPLD driver is mostly for.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
arch/arm/dts/ulcb.dtsi | 9 ++
board/renesas/ulcb/cpld.c | 212 +++--
co
2017-11-29 11:30 GMT+09:00 Tom Rini :
> On Wed, Nov 29, 2017 at 11:01:02AM +0900, Masahiro Yamada wrote:
>> 2017-11-29 10:42 GMT+09:00 Tom Rini :
>> > On Wed, Nov 29, 2017 at 12:17:35AM +0900, Masahiro Yamada wrote:
>> >> 2017-11-28 23:52 GMT+09:00 Tom Rini :
>> >> > On Tue, Nov 28, 2017 at 09:23:1
When requesting a GPIO, set the PFC GPSR register to GPIO mode,
otherwise the GPIO cannot work.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
drivers/gpio/gpio-rcar.c | 20 +++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/gpio/gpio-rcar.c b/drive
On Wed, Nov 29, 2017 at 12:02:44PM +0900, Masahiro Yamada wrote:
> 2017-11-29 11:30 GMT+09:00 Tom Rini :
> > On Wed, Nov 29, 2017 at 11:01:02AM +0900, Masahiro Yamada wrote:
> >> 2017-11-29 10:42 GMT+09:00 Tom Rini :
> >> > On Wed, Nov 29, 2017 at 12:17:35AM +0900, Masahiro Yamada wrote:
> >> >> 20
These macros are no longer needed since the DRAM configuration is parsed
from the DT. Drop them all.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
include/configs/rcar-gen3-common.h | 24 +++-
include/configs/ulcb.h | 8
2 files changed, 3 insert
Stop using the old ad-hoc SH I2C driver and use the new RCar IIC
driver instead. The SH I2C driver should be deprecated and removed
eventually.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
arch/arm/dts/ulcb.dtsi | 4
configs/r8a7795_salvator-x_defconfig | 3 +++
con
Mark the PRR as u-boot,dm-pre-reloc in all Gen3 board DTs as it is
needed very early and turn on the CONFIG_SYSCON to allow the PRR
driver to bind as a syscon uclass.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
arch/arm/dts/r8a7795.dtsi| 1 +
arch/arm/dts/r8a7796.dtsi
On Wed, Nov 29, 2017 at 03:45:45AM +0100, Marek Vasut wrote:
> It is legal to have multiple /memory nodes in a device tree . Currently,
> fdtdec_setup_memory_size() only supports parsing the first node . This
> patch extends the function such that if a particular /memory node does
> no longer have
As we have a proper clock framework driver, these macros are not
needed, so drop them and clean up the whitelist.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
include/configs/salvator-x.h | 13 +
include/configs/ulcb.h | 13 +
scripts/config_whitelist.txt |
These files no longer contain anything useful, so remove them.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
arch/arm/mach-rmobile/include/mach/r8a7795.h | 29
arch/arm/mach-rmobile/include/mach/r8a7796.h | 29
arch/arm/mach-rmobi
Enable the XHCI support on all boards.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
configs/r8a7795_salvator-x_defconfig | 1 +
configs/r8a7795_ulcb_defconfig | 1 +
configs/r8a7796_salvator-x_defconfig | 1 +
configs/r8a7796_ulcb_defconfig | 1 +
4 files changed, 4 insertio
Pull out the GIC macros from the board configuration files
into the common Gen3 configuration file since these macros
are the same for all Gen3 systems.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
include/configs/rcar-gen3-common.h | 5 +
include/configs/salvator-x.h | 5
On 11/28/2017 01:07 PM, Chris Brandt wrote:
> On Monday, November 27, 2017 1, Marek Vasut wrote:
>>> wait_for_bit() wants you to pass a direct address of a 32-bit register.
>>> The register I am waiting for is a 16-bit register and the hardware
>>> manual doesn't say 32-bit is allowed.
>>> When I d
Implement DM driver for the Renesas PRR into RCar cpu info and convert
all users with DM and OF enabled to this new driver. This means all of
the boards with DM and OF enabled can fetch PRR address from DT, which
is useful on ie. V3M which has different PRR address than the rest of
Gen3 SoCs.
Sign
We can now use rmobile_get_cpu_type() to check the CPU ID rather
than using a macro, make it so.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
board/renesas/salvator-x/salvator-x.c | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/board/renesas/salvator
Unify the R7A7795 and R8A7796 memory maps in memmap-gen3 and, for now,
select which one is used based on which SoC is selected. Since this is
done in C code instead of statically assigned now, the decision can be
taken by PRR SoC match as well, which will be done in a subsequent patch.
Signed-off-
Since the RCar Gen3 no longer uses the SH SDHI driver, but rather
uses the Matsushita SD driver, which loads all the properties from
device tree, these macros are no longer used, remove them.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
arch/arm/mach-rmobile/include/mach/r8a7795.h
Replace the ad-hoc values in the PRR CPU ID table with macros,
so that users can use rmobile_get_cpu_type() can compare the
returned value with these macros to figure out on which CPU they
are running.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
arch/arm/mach-rmobile/cpu_info.c
Since we use DM and DT, these SCIF configuration options are useless.
Remove them.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
include/configs/salvator-x.h | 7 ---
include/configs/ulcb.h | 7 ---
2 files changed, 14 deletions(-)
diff --git a/include/configs/salvator-x.h
Since both R8A7795 and R8A7796 now use the same files, unify the
Makefile entry to CONFIG_RCAR_GEN3.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
arch/arm/mach-rmobile/Makefile | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/mach-rmobile/Makefile b/arch/ar
The checkboard() function showing hard-coded board model for which the
U-Boot was built is superseded on Gen3 by show_board_info() displaying
the Model from device tree. Add small ifdef to stop compiling the
function into U-Boot.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
arch/arm/mac
Since checkboard() is gone, rmobile_sysinfo is also pointless on Gen3.
Furthermore, nuke ad-hoc CONFIG_RCAR_BOARD_STRING which is also dead.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
board/renesas/salvator-x/salvator-x.c | 4
board/renesas/ulcb/ulcb.c | 4
inclu
This command is useless on Salvator-X as it is reading DRAM info from
SPD. We have no SPD on Salvator-X.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
configs/r8a7795_salvator-x_defconfig | 1 -
configs/r8a7796_salvator-x_defconfig | 1 -
2 files changed, 2 deletions(-)
diff --git a/con
Since the Gen3 clock driver now has a .remove callback, it is no
longer necessary to shut the clock down before booting Linux in the
arch_preboot_os hook. Stop using it and while doing so, remove all
the ad-hoc config options which this hook used.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
Drop the ad-hoc DRAM configuration with macros and just decode
the DRAM configuration from device tree instead. This makes it
far cleaner and easier.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
board/renesas/salvator-x/salvator-x.c | 28
board/renesas/ulcb/
Enable the Micrel KSZ90x1 driver on ULCB, since the board is populated
with KSZ9031 and without this driver, the PHY cannot be operated.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
configs/r8a7795_ulcb_defconfig | 2 ++
configs/r8a7796_ulcb_defconfig | 2 ++
include/configs/ulcb.h
The USB support has been switched to DM, so this macro is no
longer meaningful, drop it.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
include/configs/salvator-x.h | 7 ---
include/configs/ulcb.h | 7 ---
2 files changed, 14 deletions(-)
diff --git a/include/configs/salvat
The eMMC is 1V8 device only and the signaling is always 1V8,
fix the DT for ULCB to describe the hardware correctly.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
arch/arm/dts/ulcb.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/ulcb.dtsi b/arch/arm/
Fix handling of the reset GPIO. Drop the _nodev() suffix from the
gpio_request_by_name() call as there is now a proper DM capable
GPIO driver. Also check if the GPIO is valid before freeing it in
remove path, otherwise U-Boot will crash.
Signed-off-by: Marek Vasut
Cc: Joe Hershberger
Cc: Nobuhir
Add driver for the RCar IIC or DVFS I2C controller. This driver is based
on the SH I2C driver, but supports DM and DT probing as well as modern
I2C framework API.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
drivers/i2c/Kconfig| 6 ++
drivers/i2c/Makefile | 1 +
drivers/i2c/rc
Unify the CONFIG_R8A7795 and CONFIG_R8A7796 as CONFIG_RCAR_GEN3
so that every time we add a new SoC, we won't have to add more
stuff to this list.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
drivers/serial/serial_sh.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git
Add xHCI entry into the clock tables, so that the xHCI USB driver
can enable the clock for the xHCI block via clock framework.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
drivers/clk/renesas/clk-rcar-gen3.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/renesas/clk-rca
The MSTP registers were poked in boards/renesas/rcar-common/common.c
in arch_preboot_os hook thus far to shut down the clock before Linux
takes over. With DM, this is no longer needed and we can do the same
in the clock driver .remove callback. This patch adds such a .remove
callback for R8A7795 an
It is legal to have multiple /memory nodes in a device tree . Currently,
fdtdec_setup_memory_size() only supports parsing the first node . This
patch extends the function such that if a particular /memory node does
no longer have further "reg" entries and CONFIG_NR_DRAM_BANKS still
allows for more
Hi Diego,
On Tue, Nov 28, 2017 at 02:42:20PM -0200, Diego Dorta wrote:
>Hi Peng Fan,
>
>2017-11-28 10:31 GMT-02:00 Peng Fan :
>> This patchset is to add i.MX8M and i.MX8MQ-EVK support
>>
>> patch: "power: pmic.h: include dm/ofnode.h" and
>> "power: pmic/regulator allow dm be omited by SPL" is prev
On Wed, Nov 29, 2017 at 11:01:02AM +0900, Masahiro Yamada wrote:
> 2017-11-29 10:42 GMT+09:00 Tom Rini :
> > On Wed, Nov 29, 2017 at 12:17:35AM +0900, Masahiro Yamada wrote:
> >> 2017-11-28 23:52 GMT+09:00 Tom Rini :
> >> > On Tue, Nov 28, 2017 at 09:23:18PM +0900, Masahiro Yamada wrote:
> >> >
> >
2017-11-29 10:42 GMT+09:00 Tom Rini :
> On Wed, Nov 29, 2017 at 12:17:35AM +0900, Masahiro Yamada wrote:
>> 2017-11-28 23:52 GMT+09:00 Tom Rini :
>> > On Tue, Nov 28, 2017 at 09:23:18PM +0900, Masahiro Yamada wrote:
>> >
>> >> Buildman test passed.
>> >>
>> >>
>> >> Masahiro Yamada (5):
>> >> Mov
> Could you please post your patch to the u-boot list. Then hopefully someone
> (Lokesh?) will suggest if anything better can be done. Thanks.
Here's a patch that essentially just reverts the deletions under
`CONFIG_SPL_BUILD && CONFIG_SPL_ETH_SUPPORT` from the aforementioned
commit.
Regards,
D
On Wed, Nov 29, 2017 at 12:17:35AM +0900, Masahiro Yamada wrote:
> 2017-11-28 23:52 GMT+09:00 Tom Rini :
> > On Tue, Nov 28, 2017 at 09:23:18PM +0900, Masahiro Yamada wrote:
> >
> >> Buildman test passed.
> >>
> >>
> >> Masahiro Yamada (5):
> >> Move CONFIG_PANIC_HANG to Kconfig
> >> ARM: openr
The following changes since commit 73a01d90c0b2ed2527283f289f73d69ef52cafa5:
test: Correct operation when tests pass (2017-11-27 23:05:22 -0500)
are available in the Git repository at:
git://git.denx.de/u-boot-mips.git master
for you to fetch changes up to caead80a66271d2de809acf410f8648c31
On Tue, Nov 28, 2017 at 08:33:29AM +0100, Marek Vasut wrote:
> The following changes since commit 93a51d301ad051ec6f8c6016862c7719b8b434d3:
>
> Merge git://git.denx.de/u-boot-arc (2017-11-24 11:45:15 -0500)
>
> are available in the Git repository at:
>
> git://git.denx.de/u-boot-socfpga.git
On Tue, Nov 28, 2017 at 08:32:53AM +0100, Marek Vasut wrote:
> The following changes since commit 93a51d301ad051ec6f8c6016862c7719b8b434d3:
>
> Merge git://git.denx.de/u-boot-arc (2017-11-24 11:45:15 -0500)
>
> are available in the Git repository at:
>
> git://git.denx.de/u-boot-usb.git mas
The order of members in struct hws_topology_map is cas_wl, cas_l. The
comments in the original db-88f6820-gp.c had this wrong and have been
copied to other Armada-385 based boards. Practically this hasn't made a
difference since all these boards set both cas_wl and cas_l to 0
(autodetect) but if th
Hi Tom,
The following changes since commit 73a01d90c0b2ed2527283f289f73d69ef52cafa5:
test: Correct operation when tests pass (2017-11-27 23:05:22 -0500)
are available in the Git repository at:
git://git.denx.de/u-boot-mips.git master
for you to fetch changes up to caead80a66271d2de809acf41
Hi Simon,
On Mon, 20 Nov 2017 08:40:22 -0700
Simon Glass s...@chromium.org wrote:
> Hi Anatolij,
>
> On 16 November 2017 at 18:14, Anatolij Gustschin wrote:
> > From: Markus Valentin
> >
> > Introduce functions that check the integrity of U-Boot by utilising
> > the hashes stored in the OEM-da
Erratum NO. FE-9144572: The device SPI interface supports frequencies of
up to 50 MHz. However, due to this erratum, when the device core clock
is 250 MHz and the SPI interfaces is configured for 50MHz SPI clock and
CPOL=CPHA=1 there might occur data corruption on reads from the SPI
device.
Imple
Kever,
This series causes build-breakage (even outside of the rockchip targets)...
See https://travis-ci.org/ptomsich/u-boot-rockchip/builds/308522589
Please fix and resubmit.
Also: did you test this using buildman or travis?
Thanks,
Philipp.
> On 28 Nov 2017, at 11:06, Philipp Tomsich
> wro
The Synopsys HSDK clock controller generates and supplies clock to various
controllers and peripherals within the SoC.
Each clock is assigned an identifier and client device tree nodes can use
this identifier to specify the clock which they consume. All available
clocks are defined as preprocessor
This patch fixes a problem in the mvneta driver where if more than
one packet arrives between calls to mvneta_recv(), the additional
descriptors will be marked as free even though only one descriptor
has been read and processed from the receive queue. This causes
the additional packet(s) to be del
On 28/11/2017 13:31, Peng Fan wrote:
> Add USB_BOOT entry.
>
> Signed-off-by: Peng Fan
> ---
> arch/arm/include/asm/mach-imx/boot_mode.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/include/asm/mach-imx/boot_mode.h
> b/arch/arm/include/asm/mach-imx/boot_mode.h
> index a823
On 28/11/2017 13:31, Peng Fan wrote:
> Add SIP function to issue SMC call to Arm Trusted Firmware.
I admit I do not know what is a SIP function. Patch simply adds a
wrapper, can you add a commit message with a more detailed explanation
for this ?
>
> Signed-off-by: Peng Fan
> ---
> arch/arm/in
On 28/11/2017 13:31, Peng Fan wrote:
> Add clock driver to support i.MX8M.
>
> There are two kind PLLs, FRAC pll and SSCG pll. ROM already
> configured SYS PLL1/2, we only need to configure the output.
> ocotp/i2c/pll decoding and configuration/usdhc/lcdif/dram pll/
> enet clock are configured in
On 11/28/2017 07:37 AM, Madalin-cristian Bucur wrote:
>> -Original Message-
>> From: Andrew Lunn [mailto:and...@lunn.ch]
>> Sent: Tuesday, November 28, 2017 4:13 PM
>> To: Madalin-cristian Bucur
>> Subject: Re: [RFC] Support for SGMII 2500
>>
>>> Hi Andrew,
>>>
>>> Bhaskar is working on en
Hi Peng,
On 28/11/2017 13:31, Peng Fan wrote:
> Add register definition header file for i.MX8M
>
> Signed-off-by: Peng Fan
> ---
> arch/arm/include/asm/arch-mx8m/imx-regs.h | 298
> ++
> 1 file changed, 298 insertions(+)
> create mode 100644 arch/arm/include/asm/ar
On 11/27/2017 06:32 PM, Peng Fan wrote:
> To page mapping the lowest 2 bits needs to be 0x3.
> If not fix this, the final lowest 3 bits for page mapping is 0x1
> which is marked as reserved.
>
> Signed-off-by: Peng Fan
> ---
> arch/arm/cpu/armv8/cache_v8.c| 5 -
> arch/arm/include/asm/ar
Hi Peng,
On 28/11/2017 13:31, Peng Fan wrote:
> Add i.MX8M into Kconfig, create a new folder mx8m
> dedicated for i.MX8M.
>
> Signed-off-by: Peng Fan
> ---
> arch/arm/Kconfig | 8
> arch/arm/Makefile | 4 ++--
> arch/arm/mach-imx/mx8m/Kconfig | 10 +
On 11/27/2017 07:20 PM, Peng Fan wrote:
> For external data, FIT has a optional property "data-position" which
> can set the external data to a fixed offset to FIT beginning.
> Add the support for this property in SPL FIT.
>
> Signed-off-by: Ye Li
> Signed-off-by: Peng Fan
> Cc: Simon Glass
> C
The reset circuitry in the RK3399 only resets 'almost all logic' when
a software reset is performed. To make our software maintenance
easier in the future, we want to have the option (controlled by a DTS
property) to force all reset causes other than a power-on reset to
trigger a power-on reset vi
On the RK3399-Q7, we want to trigger a full platform reset (so the
various software stacks supported don't have to deal with the same
complexities over and over again) in case that anything other than a
power-on reset occurred.
To do so, this defines the /config/sysreset-gpio property and has it
p
Hi Peng Fan,
2017-11-28 10:31 GMT-02:00 Peng Fan :
> This patchset is to add i.MX8M and i.MX8MQ-EVK support
>
> patch: "power: pmic.h: include dm/ofnode.h" and
> "power: pmic/regulator allow dm be omited by SPL" is previously reviewed
> in mailist to not merged. Pick it up.
>
> The board support i
From: Patrice Chotard
Add missing dev_count_phandle_with_args() to avoid
compilation issue.
Signed-off-by: Patrice Chotard
---
drivers/core/read.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/core/read.c b/drivers/core/read.c
index 5d440ce..f346cc1 100644
--- a/drivers/co
From: Patrice Chotard
This implementation manages several clocks, disable and
free all of them in case of error during probe and in remove
callback.
Signed-off-by: Patrice Chotard
---
drivers/net/designware.c | 43 +++
drivers/net/designware.h | 4
From: Patrice Chotard
_ Patch 1 adds dev_count_phandle_with_args() in read.c to avoid compilation
errors for Rockchip puma-rk3399 and lion-rk3368 platforms with patch 2.
_ Patch 2 adds clock support to designware net driver.
Patrice Chotard (2):
dm: core: add missing dev_count_phandle_with_
Hi all,
On 28/11/2017 13:15, Tom Rini wrote:
On Tue, Nov 28, 2017 at 11:20:04AM +0900, Jaehoon Chung wrote:
Dear Tom,
Could you pull these patches to u-boot/master?
After applied these patches, i will send the patches relevant to fixing patches.
- I have tested the buildman, it's passed.
No
Hi Tom,
This is a retry for the NAND + UniPhier pull request.
I inserted
http://patchwork.ozlabs.org/patch/842106/
The build test of openrd boards passed.
The following changes since commit 73a01d90c0b2ed2527283f289f73d69ef52cafa5:
test: Correct operation when tests pass (2017-11-27 23:05
2017-11-28 21:23 GMT+09:00 Masahiro Yamada :
> These boards are on the boundary of "u-boot-nodtb.bin exceeds file
> size limit" error.
>
> Reduce the log-level to save memory footprint.
>
> Signed-off-by: Masahiro Yamada
> ---
>
Applied to u-boot-uniphier
because I need this for the NAND updates.
> -Original Message-
> From: Andrew Lunn [mailto:and...@lunn.ch]
> Sent: Tuesday, November 28, 2017 4:13 PM
> To: Madalin-cristian Bucur
> Subject: Re: [RFC] Support for SGMII 2500
>
> > Hi Andrew,
> >
> > Bhaskar is working on enabling a PFE [1] MAC connected to an Aquantia
> AQR107
> >
Hi Simon,
On Mon, 20 Nov 2017 08:40:32 -0700
Simon Glass s...@chromium.org wrote:
> Hi Anatolij,
>
> On 16 November 2017 at 18:16, Anatolij Gustschin wrote:
> > Generate u-boot-verified.rom image containing Secure Boot Manifest
> > when secure boot option is enabled.
> >
> > Signed-off-by: Anat
2017-11-28 23:52 GMT+09:00 Tom Rini :
> On Tue, Nov 28, 2017 at 09:23:18PM +0900, Masahiro Yamada wrote:
>
>> Buildman test passed.
>>
>>
>> Masahiro Yamada (5):
>> Move CONFIG_PANIC_HANG to Kconfig
>> ARM: openrd: set CONFIG_LOGLEVEL to 2
>> Enable CONFIG_PANIC_HANG for boards without do_res
On Wed, Nov 29, 2017 at 12:12:58AM +0900, Masahiro Yamada wrote:
> 2017-11-28 23:17 GMT+09:00 Tom Rini :
> > On Tue, Nov 28, 2017 at 09:52:24AM +0900, Masahiro Yamada wrote:
> >
> >> Hi Tom,
> >>
> >> Please pull a large number of NAND core syncing
> >> and a little bit UniPhier updates.
> >>
> >>
2017-11-28 23:17 GMT+09:00 Tom Rini :
> On Tue, Nov 28, 2017 at 09:52:24AM +0900, Masahiro Yamada wrote:
>
>> Hi Tom,
>>
>> Please pull a large number of NAND core syncing
>> and a little bit UniPhier updates.
>>
>> I picked up commits from Linux one by one
>> in order not to break existing drivers
On Tue, Nov 28, 2017 at 09:23:18PM +0900, Masahiro Yamada wrote:
> Buildman test passed.
>
>
> Masahiro Yamada (5):
> Move CONFIG_PANIC_HANG to Kconfig
> ARM: openrd: set CONFIG_LOGLEVEL to 2
> Enable CONFIG_PANIC_HANG for boards without do_reset()
> treewide: convert assert() to BUG_ON(
> Hi Andrew,
>
> Bhaskar is working on enabling a PFE [1] MAC connected to an Aquantia AQR107
> PHY [2] on a LS1012AQDS board. Initially I've indicated 2500Base-X too, but it
> seems the HW actually works in SGMII mode. The QDS boards are lower volume,
> higher spec boards than the RDBs [3], they
On Tue, Nov 28, 2017 at 11:34:38AM +0100, Maxime Ripard wrote:
> On some SoCs, the SPL needs to be located right in the middle of the GPT
> partition entries.
>
> One way to work around that is to create partition entries for a smaller
> number of partitions to accomodate with where the SPL will
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