On Thu, Feb 16, 2017 at 01:32:19AM +, André Przywara wrote:
> Whether we need PSCI on an UP system is a separate question, I don't
> know from the top of my head if ARM(32) uses it for suspend/resume. But
> anyway this is not implemented in U-Boot's PSCI implementation, IIRC.
Antoine (in CC) d
Hi Vikas,
On 15 February 2017 23:50, Vikas MANOCHA wrote:
> Hi Phil,
>
> > -Original Message-
> > From: Phil Edworthy [mailto:phil.edwor...@renesas.com]
> > Sent: Monday, February 13, 2017 11:48 PM
> > To: Albert Aribaud
> > Cc: Tom Rini ; Vikas MANOCHA
> ; Kamil Lulko ; Michael
> > Kurz
This parameter is redundant because we can know the number of
channels by checking if dram_ch[2].size is zero.
Signed-off-by: Masahiro Yamada
---
arch/arm/mach-uniphier/boards.c| 12
arch/arm/mach-uniphier/dram/umc-ld11.c | 2 +-
arch/arm/mach-uniphier/dram/umc-ld20.c | 15
Enable SPL_DM on all AM43xx based platforms
Signed-off-by: Lokesh Vutla
---
configs/am43xx_evm_defconfig | 8 +++-
configs/am43xx_evm_usbhost_boot_defconfig | 8 +++-
configs/am43xx_hs_evm_defconfig | 8 +++-
include/configs/am43xx_evm.h | 7 ++
am43xx_evm defconfig has been modified without making changes
in am43xx_usbhost_boot defconfig. Synce here.
Signed-off-by: Lokesh Vutla
---
configs/am43xx_evm_usbhost_boot_defconfig | 5 +
1 file changed, 5 insertions(+)
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig
b/configs/am43
Enable SPL_DM on all AM4xx based boards.
This series depends on:
- DRA7 SPL_DM series[1]
- http://patchwork.ozlabs.org/patch/727106/
[1] https://www.mail-archive.com/u-boot@lists.denx.de/msg238751.html
Changes since v1:
- Fixed build error with non-SPL_DM defconfigs
- Increased SYS_MALLOC_F_LEN
Add u-boot specific dtsi for am43xx-gp-evm so
that it will be used for SPL.
Signed-off-by: Lokesh Vutla
---
arch/arm/dts/am437x-gp-evm-u-boot.dtsi | 38 ++
1 file changed, 38 insertions(+)
create mode 100644 arch/arm/dts/am437x-gp-evm-u-boot.dtsi
diff --git a/ar
On Monday 13 February 2017 08:47 PM, Jean-Jacques Hiblot wrote:
> This is required by the ti_qspi driver to get from the DTS the address of
> the ctrl_mod_mmap register in SPL and in u-boot.
>
> Signed-off-by: Jean-Jacques Hiblot
Tested-by: Lokesh Vutla
Thanks and regards,
Lokesh
__
Hi Marek
On Mon, Jan 23, 2017 at 11:58 AM, Marek Vasut wrote:
>
> On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
> > From: Tien Fong Chee
> >
> > There is no dependency on doing a separate clrbits first in the
> > dwmac_deassert_reset function. Combine them into a single
> > clrsetbits call.
> >
On Wed, 2017-02-15 at 23:20 +0100, Marek Vasut wrote:
> On 02/15/2017 10:48 PM, Dalon Westergreen wrote:
> >
> > On Wed, 2017-02-15 at 22:15 +0100, Marek Vasut wrote:
> > >
> > > On 02/14/2017 07:28 PM, Dalon Westergreen wrote:
> > > >
> > > >
> > > > When CSEL=0x0 the socfpga bootrom does not
On Thu, Feb 16, 2017 at 9:32 AM, André Przywara wrote:
> On 14/02/17 07:36, Maxime Ripard wrote:
>> On Mon, Feb 13, 2017 at 04:12:04PM +0800, Icenowy Zheng wrote:
>>>
>>> 2017年2月13日 15:17于 Maxime Ripard 写道：
Hi,
On Sat, Feb 11, 2017 at 07:11:02PM +0800, Icenowy Zheng wrote:
These version tests should be
#if (OPENSSL_VERSION_NUMBER < 0x1010L) || defined(LIBRESSL_VERSION_NUMBER)
or better yet have tests based on functionality rather than version.
opensslv.h on OpenBSD-current/LibreSSL portable master has
/* $OpenBSD: opensslv.h,v 1.39 2017/02/14 03:50:25 bcook E
On 14/02/17 07:36, Maxime Ripard wrote:
> On Mon, Feb 13, 2017 at 04:12:04PM +0800, Icenowy Zheng wrote:
>>
>> 2017年2月13日 15:17于 Maxime Ripard 写道：
>>>
>>> Hi,
>>>
>>> On Sat, Feb 11, 2017 at 07:11:02PM +0800, Icenowy Zheng wrote:
@@ -0,0 +1,13 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=
The OrangePi PC 2 is a typical SBC with the 64-bit Allwinner H5 SoC.
Create a new .dts file for it by including the (32-bit) H3 SoC .dtsi
and changing the differing components accordingly.
This is a preliminary device tree mostly for U-Boot's own sake, it
is expected to be updated once the official
The Allwinner H5 Soc is bascially an H3 with high SRAM and ARMv8 cores.
As the peripherals and the pinmuxing are almost identical, we piggy
back on the shared MACH_SUN8I_H3_H5 config symbol.
Signed-off-by: Andre Przywara
Acked-by: Maxime Ripard
---
arch/arm/mach-sunxi/cpu_info.c | 2 ++
board/s
The OrangePi PC 2 is a typical SBC with the 64-bit Allwinner H5 SoC.
Add a (64-bit only) defconfig defining the required options to build
the U-Boot proper.
Signed-off-by: Andre Przywara
Acked-by: Maxime Ripard
---
board/sunxi/MAINTAINERS| 5 +
configs/orangepi_pc2_defconfig | 19 +
Addresses passed on to readl and writel are expected to be of the same
size as a pointer. Change the parameter types of sunxi_spi0_read_data()
to make the compiler happy and allow a warning-free aarch64 compile.
Signed-off-by: Andre Przywara
Reviewed-by: Simon Glass
Reviewed-by: Maxime Ripard
R
The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores.
To allow sharing the clocks, GPIO and driver code easily, create an
architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol.
Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and
let it be selected by a new shared Kc
The DRAM controller in the Allwinner H5 SoC is again very similar to
the one in the H3 and A64.
Based on the existing socid parameter, add support for this controller
by reusing the bulk of the code and only deviating where needed.
These new bits set or cleared here and there have been mostly found
Some Freescale boards used an extra version of the constant to hold the
Generic Timer frequency. This can easily be covered by the now unified
COUNTER_FREQUENCY constant, so remove this extra variable from those
boards.
Signed-off-by: Andre Przywara
Reviewed-by: York Sun
Reviewed-by: Jagan Teki
Instead of enumerating all SoC families that need that bit set, let's
just express this more clearly: The SMP bits needs to be set on
SMP capable ARMv7 CPUs. It's much easier in Kconfig to express it the
other way round, so we use ! CPU_IS_UP and ! ARM64.
Signed-off-by: Andre Przywara
Acked-by: M
Traditionally Allwinner SoCs have their boot ROM mapped just below 4GB,
while the first SRAM region is mapped at address 0.
With the extended physical memory support of the A80 this was changed,
so the BROM is now at address 0 and the SRAM region starts right behind
this at 64KB. This configuration
For some reason we were pretty conservative when defining the maximum
SPL size for the Allwinner A80(sun9i) SoC.
According to the manual the SRAM A1 is even 40KB, but the BROM
probably still has the 32 KiB load limit. For the sake of simplicity,
merge the SPL memory definitions for the A64 and A80
Many ARMv8 boards define a constant COUNTER_FREQUENCY to specify the
frequency of the ARM Generic Timer (aka. arch timer).
ARMv7 boards traditionally used CONFIG_TIMER_CLK_FREQ for the same
purpose. It seems useful to unify them.
Since there are less occurences of the latter version, lets convert a
Every armv8 board needs the memory map, so change the #ifdef to
ARM64 to avoid enumerating every single board or SoC.
Signed-off-by: Andre Przywara
Acked-by: Maxime Ripard
Reviewed-by: Jagan Teki
---
arch/arm/mach-sunxi/board.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Hi,
thanks for all the reviews and ACKs!
Only minor changes this time, see the Changelog below.
Cheers,
Andre.
--
This series introduces support for the Allwinner H5 SoC with four
Cortex-A53 cores. The SoC's peripherals are very similar to the H3,
although the cores and
If we take the liberty to use register r0 to perform our bit set, we
should be nice enough to tell the compiler about it.
Add r0 to the clobber list to avoid potential mayhem.
Signed-off-by: Andre Przywara
Acked-by: Maxime Ripard
Acked-by: Jagan Teki
---
arch/arm/mach-sunxi/board.c | 3 ++-
1
Hi Simon,
I've tried porting u-boot to the veyron-speedy Chromebook, based upon
the veyron-minnie patch.
I've attached a patch with my changes to this email.
However, when I boot, all I get is a black screen. So, I have some
questions:
1. Does u-boot show output to the laptop's screen, or do I
On 14/02/17 13:49, Icenowy Zheng wrote:
> Allwinner SoCs after H3 (e.g. A64, H5, R40, V3s) uses a H3-like
> DesignWare DRAM controller, which do not have official free DRAM
> initialization code, but can use modified dram_sun8i_h3.c.
>
> Add a invisible option for easier DRAM initialization code r
On Wed, Feb 15, 2017 at 01:45:47PM -0600, Andrew F. Davis wrote:
> Add a Kconfig option that enables Legacy image support, this allows
> boards to explicitly disable this, for instance when needed for
> security reasons.
>
> Signed-off-by: Andrew F. Davis
> Reviewed-by: Simon Glass
Reviewed-by
On Wed, Feb 15, 2017 at 01:45:46PM -0600, Andrew F. Davis wrote:
> CONFIG_SPL_ABORT_ON_RAW_IMAGE causes SPL to abort and move on when it
> encounters RAW images, express this same functionality as a positive
> option enabling support for RAW images: CONFIG_SPL_RAW_IMAGE_SUPPORT
>
> Also move uses
On Wed, Feb 15, 2017 at 01:45:45PM -0600, Andrew F. Davis wrote:
> Hello all,
>
> To address a needed feature brought up by Andreas[0], we need a way to
> disable SPL from loading non-FIT images.
>
> The function spl_parse_image_header is common to all SPL loading paths
> (common/spl/spl_(nand|n
On Wed, Feb 15, 2017 at 9:26 AM, Ashish Kumar wrote:
> From: Prabhakar Kushwaha
>
> Even after memory free of phydev, priv is still pointing to the
> obsolete address.
> So update priv->phydev as NULL after memory free.
>
> Signed-off-by: Prabhakar Kushwaha
> Signed-off-by: Ashish Kumar
Please
Hi Phil,
> -Original Message-
> From: Phil Edworthy [mailto:phil.edwor...@renesas.com]
> Sent: Monday, February 13, 2017 11:48 PM
> To: Albert Aribaud
> Cc: Tom Rini ; Vikas MANOCHA ;
> Kamil Lulko ; Michael
> Kurz ; u-boot@lists.denx.de; Phil Edworthy
>
> Subject: [PATCH v2] armv7m: A
In early MMU table, DDR has to be mapped as device memory to avoid
speculative access. After DDR is initialized, it needs to be updated
to normal memory to allow code execution. To simplify the code,
dram_init() is moved into a common file as a weak function.
Signed-off-by: York Sun
---
Changes
Update mapping with actual DDR size. Non-existing memory should not
be mapped as "normal" memory to avoid speculative access.
Signed-off-by: York Sun
---
Changes in v2: None
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 42 +++--
1 file changed, 40 insertions(+), 2 dele
For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved
at the end of DDR. DDR is spit into two or three banks. This patch
reverts commit aabd7ddb and simplifies the calculation of reserved
memory, and moves the code into common SoC file. Secure memory is
carved out first. DDR bank siz
A recent debug revealed MMU for DDR shouldn't be enabled before
DDR is initialized. Otherwise, a "normal memory" mapping may cause
speculative access which may hang the system if accessing to DDR
is not allowed at time. For Layerscape platforms, we have early
MMU setup to speed up execution on emu
Function mmu_change_region_attr() is added to change existing mapping
with updated PXN, UXN and memory type. This is a break-before-make
process during which the mapping becomes fault (invalid) before final
attributres are set.
Signed-off-by: York Sun
---
Changes in v2: None
arch/arm/cpu/armv8
MMU tables should be flushed if current code runs with d-cache on. This
applies to early MMU tables with SPL boot, and all final MMU tables.
Signed-off-by: York Sun
---
Changes in v2: None
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch
Use Kconfig option instead of config macro in header file.
Clean up existing usage.
Signed-off-by: York Sun
---
Changes in v2: None
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 8
include/configs/ls2080a_common.h | 1 -
scripts/config_whitelist.txt | 1 -
3 files
Instead of adding all memory banks, add a hook so individual SoC/board
can has its own implementation.
Signed-off-by: York Sun
CC: Alexander Graf
---
Changes in v2:
Add change to efi mapping
lib/efi_loader/efi_memory.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
Use Kconfig option instead of config macro in header file.
Signed-off-by: York Sun
---
Changes in v2: None
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 8
include/configs/ls2080a_common.h | 1 -
scripts/config_whitelist.txt | 1 -
3 files changed, 8 insertions(+),
Since the reserved RAM is tracked by gd->arch.resv_ram, calculation
of MC memory blocks can be simplified. The MC RAM is guaranteed to be
aligned by the reservation process.
Signed-off-by: York Sun
CC: Priyanka Jain
---
Changes in v2: None
drivers/net/fsl-mc/mc.c | 59 +++-
Use gd->arch.resv_ram to track reserved memory allocation.
Signed-off-by: York Sun
---
Changes in v2: None
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 ++
arch/arm/include/asm/global_data.h| 3 +++
cmd/bdinfo.c | 4
3 files changed, 13 insertions
On 02/15/2017 10:48 PM, Dalon Westergreen wrote:
> On Wed, 2017-02-15 at 22:15 +0100, Marek Vasut wrote:
>> On 02/14/2017 07:28 PM, Dalon Westergreen wrote:
>>>
>>> When CSEL=0x0 the socfpga bootrom does not touch the clock
>>> configuration for the device. This can lead to a boot failure
>>> on w
On 02/15/2017 10:50 PM, Tom Rini wrote:
> On Wed, Feb 15, 2017 at 09:46:38PM +0100, Marek Vasut wrote:
>> On 02/15/2017 12:11 AM, Tom Rini wrote:
>>> On Wed, Feb 15, 2017 at 12:03:32AM +0100, Marek Vasut wrote:
On 02/14/2017 11:58 PM, Tom Rini wrote:
> On Sun, Feb 12, 2017 at 12:52:45PM +0
On 15/02/2017 19:52, york sun wrote:
Reduce CC list.
On 02/14/2017 11:56 AM, Alexander Graf wrote:
On 14/02/2017 18:38, york sun wrote:
On 02/14/2017 09:00 AM, york@nxp.com wrote:
On 02/14/2017 07:31 AM, Alexander Graf wrote:
On 14/02/2017 04:45, York Sun wrote:
For ARMv8 Layersca
On Wed, Feb 15, 2017 at 09:46:38PM +0100, Marek Vasut wrote:
> On 02/15/2017 12:11 AM, Tom Rini wrote:
> > On Wed, Feb 15, 2017 at 12:03:32AM +0100, Marek Vasut wrote:
> >> On 02/14/2017 11:58 PM, Tom Rini wrote:
> >>> On Sun, Feb 12, 2017 at 12:52:45PM +0100, Andreas Färber wrote:
> Hi Marek,
On Wed, 2017-02-15 at 22:15 +0100, Marek Vasut wrote:
> On 02/14/2017 07:28 PM, Dalon Westergreen wrote:
> >
> > When CSEL=0x0 the socfpga bootrom does not touch the clock
> > configuration for the device. This can lead to a boot failure
> > on warm resets. To address this, the bootrom is config
On 02/14/2017 07:28 PM, Dalon Westergreen wrote:
> When CSEL=0x0 the socfpga bootrom does not touch the clock
> configuration for the device. This can lead to a boot failure
> on warm resets. To address this, the bootrom is configured to
> run a bit of code in the last 4KB of onchip ram on a warm
On 02/15/2017 12:11 AM, Tom Rini wrote:
> On Wed, Feb 15, 2017 at 12:03:32AM +0100, Marek Vasut wrote:
>> On 02/14/2017 11:58 PM, Tom Rini wrote:
>>> On Sun, Feb 12, 2017 at 12:52:45PM +0100, Andreas Färber wrote:
Hi Marek,
Am 01.12.2016 um 02:06 schrieb Marek Vasut:
> From: Paul
On 02/15/2017 07:56 AM, Chin Liang See wrote:
> On Sel, 2017-02-14 at 10:28 -0800, Dalon Westergreen wrote:
>> When CSEL=0x0 the socfpga bootrom does not touch the clock
>> configuration for the device. This can lead to a boot failure
>> on warm resets. To address this, the bootrom is configured
On 02/15/2017 04:23 AM, Udit Agarwal wrote:
> For Layerscape chasis Gen 3 based platforms, during PPA execution
> exception level transition happens from EL3 to EL2. While in EL2 state
> SNVS state doesnot changes from secure to non secure state in
> case of ESBC failure.
>
> So to enable the SNVS
Reduce CC list.
On 02/14/2017 11:56 AM, Alexander Graf wrote:
>
>
> On 14/02/2017 18:38, york sun wrote:
>> On 02/14/2017 09:00 AM, york@nxp.com wrote:
>>> On 02/14/2017 07:31 AM, Alexander Graf wrote:
On 14/02/2017 04:45, York Sun wrote:
> For ARMv8 Layerscape SoCs, secure
Disable support for loading non-FIT images for AM335x platforms using
the high-security (HS) device variant.
Signed-off-by: Andrew F. Davis
Reviewed-by: Simon Glass
---
configs/am335x_hs_evm_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configs/am335x_hs_evm_defconfig b/config
Add a Kconfig option that enables Legacy image support, this allows
boards to explicitly disable this, for instance when needed for
security reasons.
Signed-off-by: Andrew F. Davis
Reviewed-by: Simon Glass
---
Kconfig | 8
common/spl/spl.c | 10 --
2 files changed, 16
Hello all,
To address a needed feature brought up by Andreas[0], we need a way to
disable SPL from loading non-FIT images.
The function spl_parse_image_header is common to all SPL loading paths
(common/spl/spl_(nand|net|nor|etc..)) so we add the check here.
This version of the series is a bit di
Disable support for loading non-FIT images for AM57xx platforms using
the high-security (HS) device variant.
Signed-off-by: Andrew F. Davis
Reviewed-by: Simon Glass
---
configs/am57xx_hs_evm_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configs/am57xx_hs_evm_defconfig b/config
CONFIG_SPL_ABORT_ON_RAW_IMAGE causes SPL to abort and move on when it
encounters RAW images, express this same functionality as a positive
option enabling support for RAW images: CONFIG_SPL_RAW_IMAGE_SUPPORT
Also move uses of this to defconfigs.
Signed-off-by: Andrew F. Davis
---
Kconfig
Disable support for loading non-FIT images for AM43xx platforms using
the high-security (HS) device variant.
Signed-off-by: Andrew F. Davis
Reviewed-by: Simon Glass
---
configs/am43xx_hs_evm_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configs/am43xx_hs_evm_defconfig b/config
Disable support for loading non-FIT images for DRA7xx platforms using
the high-security (HS) device variant.
Signed-off-by: Andrew F. Davis
Reviewed-by: Simon Glass
---
configs/dra7xx_hs_evm_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configs/dra7xx_hs_evm_defconfig b/config
On 02/14/2017 03:04 PM, Tom Rini wrote:
> On Tue, Feb 14, 2017 at 02:32:42PM -0600, Andrew F. Davis wrote:
>> On 02/14/2017 02:15 PM, Tom Rini wrote:
>>> On Mon, Feb 13, 2017 at 12:47:36PM -0600, Andrew F. Davis wrote:
>>>
CONFIG_SPL_ABORT_ON_RAW_IMAGE causes SPL to abort and move on when it
>
On Wed, Feb 15, 2017 at 09:16:53AM -0600, Andrew F. Davis wrote:
> When using early malloc the allocated memory can overflow into the SRAM
> scratch space, move NON_SECURE_SRAM_IMG_END down a bit to allow more
> dynamic allocation at the expense of a slightly smaller maximum image
> size.
>
> Sig
On Wed, Feb 15, 2017 at 9:32 AM, Konstantin Porotchkin
wrote:
>
>
> On 02/15/2017 11:07 AM, Konstantin Porotchkin wrote:
>>
>> Hi, Joe,
>>
>> On 02/14/2017 07:17 PM, Joe Hershberger wrote:
>>>
>>> On Tue, Feb 14, 2017 at 6:32 AM, Stefan Roese wrote:
>>> > (added Joe to Cc as network custodian)
>>
On Wed, Feb 15, 2017 at 2:04 PM, Gary Bisson
wrote:
> Hi,
>
> I've been testing fastboot to flash a sparse image on a i.MX6Q platform
> (Nitrogen6x) with U-Boot v2017.01.
>
> This test shows a lot of "misaligned operation" traces:
> => fastboot 0
> Starting download of 415679660 bytes
> ...
> down
Hi Peter,
2017-02-14 11:10 GMT-02:00 Peter Robinson :
> From: Peter Robinson
> Date: Tue, Feb 14, 2017 at 11:10 AM
> Subject: [U-Boot] [PATCH 1/3] mx6sx: udoo_neo: Define the default serial
> console
> To: Breno Lima , Francesco Montefoschi
> , Stefano Babic ,
> u-boot@lists.denx.de
>
>
> Stand
This enables the support for the Allwinner A23 Evaluation Board (EVB),
that already had a device tree (from Linux) but no defconfig.
This board has an AXP223 PMIC, some NAND, Audio out and in plugs, an
accelerometer and light sensor, as well as a USB HSIC hub and a USB
OTG mini-USB connector. It a
Hi Haikun Wang,
I have a question about the source of uboot.
http://lists.denx.de/pipermail/u-boot/2015-June/217446.html
>u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
>val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
The question is this,
why does DCFG_RCWSR13 device by 4.
(1)dcfg_ccsr
Hi,
I've been testing fastboot to flash a sparse image on a i.MX6Q platform
(Nitrogen6x) with U-Boot v2017.01.
This test shows a lot of "misaligned operation" traces:
=> fastboot 0
Starting download of 415679660 bytes
...
downloading of 415679660 bytes finished
Flashing sparse image at offset 821
On 02/15/2017 11:07 AM, Konstantin Porotchkin wrote:
Hi, Joe,
On 02/14/2017 07:17 PM, Joe Hershberger wrote:
On Tue, Feb 14, 2017 at 6:32 AM, Stefan Roese wrote:
> (added Joe to Cc as network custodian)
>
>
> On 14.02.2017 13:13, Konstantin Porotchkin wrote:
>>
>> Hi, Stefan,
>>
>> On 2/14/2
LS1088A is an ARMv8 implementation. The LS1088ARDB is an evaluatoin
platform that supports the LS1088A family SoCs. This patch add basic
support of the platform.
Signed-off-by: Alison Wang
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Ashish Kumar
Signed-off-by: Raghav Dogra
Signed-off-by:
From: Prabhakar Kushwaha
Even after memory free of phydev, priv is still pointing to the
obsolete address.
So update priv->phydev as NULL after memory free.
Signed-off-by: Prabhakar Kushwaha
---
drivers/net/ldpaa_eth/ldpaa_eth.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --
The QorIQ LS1088A processor is built on the Layerscape
architecture combining eight ARM A53 processor cores
with advanced, high-performance datapath acceleration
and networks, peripheral interfaces required for
networking, wireless infrastructure, and general-purpose
embedde
This patch add support of LS1088AQDS platform.
The LS1088A QorIQTM Development System (QDS) is a
high-performance computing, evaluation, and
development platform that supports the LS1088A QorIQ Architecture
processor.
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Ashish Kumar
Signed-off-by:
From: Prabhakar Kushwaha
SerDes information is not necessary to be present in RCWSR29 register.
It may vary from SoC to SoC.
So Avoid RCWSR28 register hard-coding.
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Ashish Kumar
---
v2:
Incorporate York's Review comments
.../cpu/armv8/fsl-laye
From: Prabhakar Kushwaha
Even after memory free of phydev, priv is still pointing to the
obsolete address.
So update priv->phydev as NULL after memory free.
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Ashish Kumar
---
v2:
Add signoff
drivers/net/ldpaa_eth/ldpaa_eth.c | 4 +++-
1 file ch
When using early malloc the allocated memory can overflow into the SRAM
scratch space, move NON_SECURE_SRAM_IMG_END down a bit to allow more
dynamic allocation at the expense of a slightly smaller maximum image
size.
Signed-off-by: Andrew F. Davis
Reviewed-by: Lokesh Vutla
---
arch/arm/include/
From: Prabhakar Kushwaha
MAC number used per QSGMII is not fixed. It may wary from SoC to SoC.
So move QSGMII wriop_init_dpmac() to SoC file.
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Ashish Kumar
---
v2:
Incorporate York's Review comments
.../cpu/armv8/fsl-layerscape/fsl_lsch3_serde
For Layerscape chasis Gen 3 based platforms, during PPA execution
exception level transition happens from EL3 to EL2. While in EL2 state
SNVS state doesnot changes from secure to non secure state in
case of ESBC failure.
So to enable the SNVS transition in EL2 state, NPSWA_EN bit has to be set
whe
On 02/15/2017 01:30 PM, Roger Quadros wrote:
On 15/02/17 10:24, Roger Quadros wrote:
On 14/02/17 22:12, Tom Rini wrote:
On Tue, Feb 14, 2017 at 01:26:24PM -0600, Nishanth Menon wrote:
On 02/14/2017 01:20 PM, Tom Rini wrote:
On Tue, Feb 14, 2017 at 01:18:20PM -0600, menon.nisha...@gmail.com
On Tue, Feb 14, 2017 at 4:07 PM, Tom Rini wrote:
> On Tue, Feb 14, 2017 at 03:56:43PM -0600, Adam Ford wrote:
>> On Feb 14, 2017 3:10 PM, "Tom Rini" wrote:
>>
>> On Tue, Feb 14, 2017 at 03:03:44PM -0600, Adam Ford wrote:
>>
>> > Tom,
>> >
>> > I noticed there was an update to the omap3_logic_defc
The size field in GP header that is expected by ROM is size of the
image + size of the header. But omapimage generates a gp header
only with size of the image as size field. Fix it
Signed-off-by: Lokesh Vutla
---
tools/omapimage.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On Wed, Feb 15, 2017 at 06:02:37PM +0530, Lokesh Vutla wrote:
> Hi Tom,
>
> On Friday 10 February 2017 08:37 PM, Lokesh Vutla wrote:
> > The size field in GP header that is expected by ROM is size of the
> > image + size of the header. But omapimage generates a gp header
> > only with size of the
Hi Tom,
On Friday 10 February 2017 08:37 PM, Lokesh Vutla wrote:
> The size field in GP header that is expected by ROM is size of the
> image + size of the header. But omapimage generates a gp header
> only with size of the image as size field. Fix it
Unfortunately this is not ture for Keystone2.
Hi,
On 01/16/2017 08:36 PM, Michael Nazzareno Trimarchi wrote:
> Hi
>
>
>
> On 14 Jan 2017 3:54 a.m., "Anatolij Gustschin" wrote:
>
> From: "tomas.me...@vaisala.com"
>
> SPLASH_STORAGE_RAW is defined as 0, so a check against & will
> never be true. These flags are never combined so do a ch
On 15/02/17 10:24, Roger Quadros wrote:
> On 14/02/17 22:12, Tom Rini wrote:
>> On Tue, Feb 14, 2017 at 01:26:24PM -0600, Nishanth Menon wrote:
>>> On 02/14/2017 01:20 PM, Tom Rini wrote:
On Tue, Feb 14, 2017 at 01:18:20PM -0600, menon.nisha...@gmail.com wrote:
> On Mon, Feb 13, 2017 at 7:
Hi,
On Wednesday 08 February 2017 11:21 PM, Davis, Andrew wrote:
> FIT support in the net boot case is much like the RAM boot case in that
> we load our image to "load_addr" and pass a dummy read function into
> "spl_load_simple_fit()". As the load address is no longer hard-coded to
> the final ex
On Wed, 2017-02-15 at 18:09 +0800, Bin Meng wrote:
> Hi Andy,
>
> On Wed, Feb 15, 2017 at 5:50 PM, Andy Shevchenko
> wrote:
> > On Wed, 2017-02-15 at 11:00 +0800, Bin Meng wrote:
> > > On Tue, Feb 14, 2017 at 10:47 PM, Andy Shevchenko
> > > wrote:
> > > What's the architecture of Intel Edison?
Hi Andy,
On Wed, Feb 15, 2017 at 5:50 PM, Andy Shevchenko
wrote:
> On Wed, 2017-02-15 at 11:00 +0800, Bin Meng wrote:
>> Hi Andy,
>>
>> On Tue, Feb 14, 2017 at 10:47 PM, Andy Shevchenko
>> wrote:
>> > Intel Mobile Internet Device (MID) platforms have special treatment
>> > in
>> > some cases, su
On Wed, 2017-02-15 at 11:10 +0800, Bin Meng wrote:
> Hi Andy,
>
> On Tue, Feb 14, 2017 at 10:47 PM, Andy Shevchenko
> wrote:
> > There is no microcode update available for SoCs used on Intel MID
> > platforms.
> >
> > Use conditional to bypass it.
> >
> > Signed-off-by: Andy Shevchenko
> > ---
On Wed, 2017-02-15 at 11:00 +0800, Bin Meng wrote:
> Hi Andy,
>
> On Tue, Feb 14, 2017 at 10:47 PM, Andy Shevchenko
> wrote:
> > Intel Mobile Internet Device (MID) platforms have special treatment
> > in
> > some cases, such as CPU enumeration or boot parameters
> > configuration.
> >
> > Here w
On 02/14/2017 02:25 PM, Konstantin Porotchkin wrote:
On 2/14/2017 14:21, Stefan Roese wrote:
On 14.02.2017 13:07, Konstantin Porotchkin wrote:
Hi, Stefan,
On 2/14/2017 13:43, Stefan Roese wrote:
Hi Kosta,
On 13.02.2017 14:38, kos...@marvell.com wrote:
From: Konstantin Porotchkin
Fix t
On 14/02/2017 19:52, Tom Rini wrote:
On Tue, Feb 14, 2017 at 02:16:13PM +0100, Jean-Jacques Hiblot wrote:
Hi Tom,
Have you had a chance to look at the patch below?
It looks fine but was too close to the release window (given the
potential impact) to merge. Thanks!
Ok Thank you for the fee
Hi, Joe,
On 02/14/2017 07:17 PM, Joe Hershberger wrote:
On Tue, Feb 14, 2017 at 6:32 AM, Stefan Roese wrote:
> (added Joe to Cc as network custodian)
>
>
> On 14.02.2017 13:13, Konstantin Porotchkin wrote:
>>
>> Hi, Stefan,
>>
>> On 2/14/2017 13:49, Stefan Roese wrote:
>>>
>>> Hi Kosta,
>>>
>>>
On Tue, 14 Feb 2017 14:27:30 -0700 (MST)
brendan wrote:
> I am storing some information regarding my board within EEPROM (in
> memory after I use the >eeprom read command) and I was wondering if
> it was possible for me to somehow read from memory and store the
> values into an environment variab
On 14/02/17 22:12, Tom Rini wrote:
> On Tue, Feb 14, 2017 at 01:26:24PM -0600, Nishanth Menon wrote:
>> On 02/14/2017 01:20 PM, Tom Rini wrote:
>>> On Tue, Feb 14, 2017 at 01:18:20PM -0600, menon.nisha...@gmail.com wrote:
On Mon, Feb 13, 2017 at 7:27 AM, Tom Rini wrote:
> On Mon, Feb 13,
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