Hi Jaehoon,
On 11/18/2016 07:07 AM, Jaehoon Chung wrote:
>> On 11/16/2016 03:39 PM, Jaehoon Chung wrote:
>>>
>>> On 11/16/2016 10:12 PM, Tomas Melin wrote:
Hi,
On 11/16/2016 02:05 PM, Jaehoon Chung wrote:
>
> Why needs to set bkops on bootloader? Is there special reason?
>
Hi Andre,
On Sun, Nov 20, 2016 at 02:57:05PM +, Andre Przywara wrote:
> The ENABLE_ARM_SOC_BOOT0_HOOK option is a generic option shared with
> other boards. To allow alternative code to be inserted, we create
> another, now function specific config symbol on top of it to simplify
> later addit
From: Tang Yuantian
Commit d97dc8a0 separated the non-command code into its own file
which caused variable sata_curr_device can not be set to a correct
value.
Before commit d97dc8a0, variable sata_curr_device can be set
correctly in sata_initialize().
After commit d97dc8a0, sata_initialize() is
Hi Simon,
On Saturday 19 November 2016 01:04 AM, Simon Glass wrote:
> Hi Mugunthan,
>
> On 17 November 2016 at 01:09, Mugunthan V N wrote:
>> Convert usb ether gadget to adopt usb driver model
>>
>> Signed-off-by: Mugunthan V N
>> Reviewed-by: Simon Glass
>
> Sorry, but I'd like to 'un-review
Hi Jagan,
On Thursday 13 October 2016 06:24 PM, Tom Rini wrote:
> On Thu, Oct 13, 2016 at 05:45:52PM +0530, Jagan Teki wrote:
>> On Thu, Oct 13, 2016 at 3:53 PM, Vignesh R wrote:
>>> Unlike Linux kernel, U-Boot depends on "spi-flash" compatible to probe
>>> m25p80 spi-nor devices. Hence, add "spi
Ok, will resend this patch.
Thanks,
Yuantian
> -Original Message-
> From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
> Sent: Saturday, November 19, 2016 3:34 AM
> To: Y.T. Tang
> Cc: Bin Meng ; U-Boot Mailing List b...@lists.denx.de>; S.H. Xie
> Subject: Re: [PAT
- add additional function erratum_a009942_check_cpo to check if the
board needs tuning CPO calibration for optimal setting.
- move ERRATUM_A009942(with revision to check cpo_sample option) from
fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts.
- move ERRATUM_A008378 from fsl_ddr_g
Fix following warning in case multiple erratum macro was not defined.
warning: unused variable 'tmp'
warning: unused variable 'ddr_freq'
Signed-off-by: Shengzhou Liu
---
v2: fix compile issue on some platforms.
drivers/ddr/fsl/fsl_ddr_gen4.c | 57 ++
1 fi
From: Konstantin Porotchkin
Enable mvebu pin control support in the default configuration
files for Armada-7040 and Armada-8040 development boards
Change-Id: Icc133c97c6f9fea374dd26ea5ab3f65fd66cc796
Signed-off-by: Konstantin Porotchkin
Cc: Stefan Roese
Cc: Nadav Haklai
Cc: Neta Zur Hershkovi
From: Konstantin Porotchkin
Enable mvebu "bubt" command support in the default configuration
file for Armada-7040 and Armada-8040 development boards
Change-Id: I9dba917baa68fc1e14007e66fda5d22d64bc94c1
Signed-off-by: Konstantin Porotchkin
Cc: Stefan Roese
Cc: Nadav Haklai
Cc: Neta Zur Hershko
From: Konstantin Porotchkin
Add pin control nodes to APN806, CP-master, CP-slave and
Armada-7040 and Armada-8040 boards DTS files
Change-Id: I51522f33f23e3f9e94c6f5a5f9af19f5dc86e6b7
Signed-off-by: Konstantin Porotchkin
Cc: Stefan Roese
Cc: Nadav Haklai
Cc: Neta Zur Hershkovits
Cc: Omri Itac
From: Konstantin Porotchkin
This set of patches is adding more features for bards based on new
Marvell MoChi platforms - Armada-70x0 and Armada-80x0.
The patches were applied on top of Stefan's patch set with the
last patch named "arm64: mvebu: Add PCI support to DB-88F8040 board".
The test was
From: Konstantin Porotchkin
Add support for mvebu bubt command for flash image
load, check and burn on boot device.
Change-Id: If2b971069ae44232761b601bbbcf0162567f5603
Signed-off-by: Konstantin Porotchkin
Cc: Stefan Roese
Cc: Nadav Haklai
Cc: Neta Zur Hershkovits
Cc: Omri Itach
Cc: Igal Li
From: Konstantin Porotchkin
Add a port of Marvell pin control driver.
The A8K SoC family contains several silicone dies interconnected
in a single package. Every die is normally equuipped with its own
pin controller unit.
Since the UCLASS_PINCTRL device only calls the probe method for
the first d
From: Konstantin Porotchkin
Align the Armada-8040-db SPI and I2C DTS settings with latest
A8040 DB settings:
- disable i2c0 and spi0 on AP (pins are reserved for eMMC)
- disable cps_i2c0 on CP1
- enable spi1 on CP1 (the new location of the boot flash)
Change-Id: I54698ce4dc8dbe6a2af14099f5bcc3ca
When compiling the SPL for the Allwinner A64 in AArch64 mode, we can't
use the more compact Thumb2 encoding, which only exists for AArch32
code. This makes the SPL rather big, up to a point where any code
additions or even a different compiler may easily exceed the 32KB limit
that the Allwinner BRO
The ARMv8 capable Allwinner A64 SoC comes out of reset in AArch32 mode.
To run AArch64 code, we have to trigger a warm reset via the RMR register,
which proceeds with code execution at the address stored in the RVBAR
register.
If the bootable payload in the FIT image is using a different
architectu
At the moment we use the arch/arm directory for arm64 boards as well,
so the Makefile will pick up the "arm" name for the architecture to use
for tagging binaries in U-Boot image files.
Differentiate between the two by looking at the CPU variable being defined
to "armv8", and use the arm64 architec
Since the SPL FIT loader can now differentiate between different
architectures, teach it how to tell arm and arm64 apart when a FIT
image is used.
We just support those two for now, as these are so far the only sensible
alternatives.
Signed-off-by: Andre Przywara
---
arch/arm/lib/spl.c | 15
Read the specified "arch" value from a legacy or FIT U-Boot image and
store it in our SPL data structure.
This allows loaders to take the target architecture in account for
custom loading procedures.
Having the complete string -> arch mapping for FIT based images in the
SPL would be too big, so we
Fix the output of the DRAM size on AArch64 SPLs.
Signed-off-by: Andre Przywara
---
arch/arm/mach-sunxi/dram_sun8i_h3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c
b/arch/arm/mach-sunxi/dram_sun8i_h3.c
index 3d569fc..5ee8b3d 100644
---
Now that the SPL is ready to be compiled in AArch64 and the DRAM
init code is ready, enable SPL support for the A64 SoC and in the
Pine64 defconfig.
For now we keep the boot0 header in the U-Boot proper, as this allows
to still use boot0 as an SPL replacement without hurting the SPL use
case.
We di
From: Jens Kuske
Instead of setting the delay for whole bytes allow setting
it for each individual bit. Also add support for
address/command lane delays.
Signed-off-by: Jens Kuske
Signed-off-by: Andre Przywara
---
arch/arm/mach-sunxi/dram_sun8i_h3.c | 54 ++---
From: Jens Kuske
The A64 DRAM controller is very similar to the H3 one,
so the code can be reused with some small changes.
[Andre: fixed up typo, merged in fixes from Jens]
Signed-off-by: Jens Kuske
Signed-off-by: Andre Przywara
---
arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 1 +
arc
According to Jens disabling the on-die-termination should set bit 5,
not bit 1 in the respective register. Fix this.
Reported-by: Jens Kuske
Signed-off-by: Andre Przywara
---
arch/arm/mach-sunxi/dram_sun8i_h3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-su
From: Jens Kuske
The IOCR registers got renamed to BDLR to match the public
documentation of similar controllers.
Signed-off-by: Jens Kuske
Signed-off-by: Andre Przywara
---
arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h | 43 ++---
arch/arm/mach-sunxi/dram_sun8i_h3.c
To avoid enumerating the very same DRAM values in defconfig files
for each and every Allwinner A64 board out there, let's put some sane
default values in the Kconfig file.
Boards with different needs can override them at any time.
Signed-off-by: Andre Przywara
---
board/sunxi/Kconfig |
The Allwinner A64 SoC starts execution in AArch32 mode, and both
the boot ROM and Allwinner's boot0 keep running in this mode.
So U-Boot gets entered in 32-bit, although we want it to run in AArch64.
By using a "magic" instruction, which happens to be an almost-NOP in
AArch64 and a branch in AArch
For prepending some board specific header area to U-Boot images we
were so far including a header file with a macro definition containing
the actual header specification.
This works fine if there are just a few statements and if there is only
one alternative.
However adding more complex code quickl
The ENABLE_ARM_SOC_BOOT0_HOOK option is a generic option shared with
other boards. To allow alternative code to be inserted, we create
another, now function specific config symbol on top of it to simplify
later additions. No functional change at this time.
Signed-off-by: Andre Przywara
---
board
The boot0 hook we have so far is applied _after_ the initial branch
to the "reset" entry point. An upcoming change requires even this
branch to be changed, so we apply the hook macro at the earliest
point, and have the branch in the hook file as well.
This is no functional change at this point, jus
tiny-printf does not know about the "l" modifier so far, which breaks
the crash dump on AArch64, because it uses %lx to print the registers.
Add an easy way of handling longs correctly.
Signed-off-by: Andre Przywara
---
lib/tiny-printf.c | 43 +--
1 file c
The UL() macro is pretty useful in sharing constants between assembly
and C files while still being able to specify a type for C.
Move the macro from an armv8 specific header into a common header file
to be able to use it by arm code (for instance) as well.
Signed-off-by: Andre Przywara
---
arch
The sunxi DRAM setup code needs an sdelay() implementation, which
wasn't defined for armv8 so far.
Shamelessly copy the armv7 version and adjust it to work in AArch64.
Signed-off-by: Andre Przywara
---
arch/arm/cpu/armv8/cpu.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/ar
Since entry_point and load_addr are addresses, they should be
represented as longs to cover the whole address space and to avoid
warning when compiling the SPL in 64-bit.
Also adjust debug prints to add the 'l' specifier, where needed.
Signed-off-by: Andre Przywara
---
arch/arm/cpu/armv7/omap-co
For boards that call s_init() when the SPL runs, we are expected to
setup an early stack before calling this C function.
Implement the proper AArch64 version of this based on the ARMv7 code.
This allows sunxi boards to setup the basic peripherals even on with a
64-bit SPL.
Signed-off-by: Andre Prz
The predominantely 32-bit ARM targets try to compile the SPL in Thumb
mode to reduce code size.
The 64-bit AArch64 instruction set does not know an alternative, concise
encoding, so the Thumb build option should only be set for 32-bit
targets.
Likewise -marm machine options are only valid for ARMv7
Hi,
this series introduces SPL support for the Allwinner A64 SoC.
In contrast to the previous RFC this one includes support for both
AArch64 and AArch32 SPL builds.
Still the FIT support is missing, which means the functionality is
limited. Due to the missing ARM Trusted Firmware (ATF) in this fir
Somehow an int returning function without a return statement sneaked
in, fix it.
Also fix some whitespace damage on the way.
Signed-off-by: Andre Przywara
---
drivers/mtd/spi/sunxi_spi_spl.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi/sunxi_spi_spl.c b/d
These days many Allwinner SoCs use clock_sun6i.c, although out of them
only the (original sun6i) A31 has a second MBUS clock register.
Also setting up the PRCM PLL_CTLR1 register to provide the proper voltage
seems to be an A31-only feature as well.
So restrict the initialization to this SoC only t
On Sat, Nov 19, 2016 at 9:34 AM, Jagan Teki wrote:
> Dual flash code in spi are usually take the spi controller
> to work with dual connected flash devices. Usually these
> dual connection operation's are referred to flash controller
> protocol rather with spi controller protocol, these are still
Hi Tom,
On Sat, Nov 19, 2016 at 6:27 AM, Tom Rini wrote:
> On Fri, Nov 18, 2016 at 04:46:03PM +0530, Jagan Teki wrote:
>
>> Hi Tom,
>>
>> Please pull this PR.
>>
>> thanks!
>> Jagan.
>>
>> The following changes since commit c2cbd164ea5b5f564fcf03447c7bf9ec4a9f5699:
>>
>> Merge branch 'master' o
Hi, Simon,
Thank you for your reply.
In order to activate pin control function using "pinctrl-0" property, the
device driver itself has to be aware of the pin control existence, right?
So if I put such property under SPI controller, the SPI controller driver
has to handle call to the pin control d
Use net device priv to pass usb ether priv and use it in
net device ops callback.
Signed-off-by: Mugunthan V N
Reviewed-by: Simon Glass
---
drivers/usb/gadget/ether.c | 46 +-
1 file changed, 21 insertions(+), 25 deletions(-)
diff --git a/drivers/usb
Adopt usb ether gadget and rndis driver to adopt driver model
Signed-off-by: Mugunthan V N
---
drivers/usb/gadget/Kconfig | 4 ++
drivers/usb/gadget/ether.c | 153 ++---
drivers/usb/gadget/rndis.c | 13 +++-
drivers/usb/gadget/rndis.h | 19 --
incl
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