On Fri, Aug 8, 2014 at 7:41 AM, Tim Harvey wrote:
> Two patches to add Intel i210 support to the e1000 driver.
>
> Marek Vasut (2):
> e1000: Implement dcache support
> e1000: add i210 support
>
> drivers/net/e1000.c | 266
> ++--
> drivers/net/
On Thu, Aug 7, 2014 at 10:49 PM, Tim Harvey wrote:
> Many of the Gateworks Ventana boards have a PLX PCIe switch where GPIO
> on the switch is used as the PERST# of the downstream ports. In the Linux
> kernel there is a PCI fixup that asserts these properly when the upstream
> port is enumerated.
Benoît,
On Wed, Aug 20, 2014 at 12:47 PM, Benoît Thébaudeau
wrote:
> On Wed, Aug 20, 2014 at 9:21 AM, Christian Riesch
> wrote:
>> On Tue, Aug 19, 2014 at 8:35 PM, Benoît Thébaudeau
>> wrote:
>>> Commit 41623c9 'arm: move exception handling out of start.S files' missed
>>> some
>>> linker scri
The GW5520 has an IMX6Q SoC with 512MB of DDR3, 256MB of NAND flash as well as:
* 2x MiniPCIe sockets
* 2x USB host sockets
* 2x i210 GigE
* HDMI out
* digital I/O expansion
Signed-off-by: Tim Harvey
---
board/gateworks/gw_ventana/eeprom.c | 3 ++
board/gateworks/gw_ventana/gsc.c
The IMX6 MMDC calibration registers depend on propagation delay and capacitive
loading between the SoC's MMDC and the DDR3 chips. On the Ventana boards the
board layout varies little in trace-lengths such that propagation delays are
irrelevant thus we can simply things by using calibration values o
Signed-off-by: Tim Harvey
---
board/gateworks/gw_ventana/gw_ventana.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c
b/board/gateworks/gw_ventana/gw_ventana.c
index 2928ac1..2610e0a 100644
--- a/board/gateworks/gw_ventana/gw_venta
Hi Fabio,
On 20.08.2014 23:24, Fabio Estevam wrote:
From: Fabio Estevam
mx6solox has a requirement for 64 bytes alignment for RX DMA transfer.
Adjust it accordingly.
Signed-off-by: Fabio Estevam
---
Changes since v1:
- Avoid too many ifdef's by providing a dma_rx_align() funtion as suggeste
On Wed, Aug 20, 2014 at 5:38 PM, Nikita Kiryanov wrote:
> Add support for M25PE16 and M25PX16
>
> Cc: Jagannadha Sutradharudu Teki
> Cc: Marek Vasut
> Acked-by: Marek Vasut
> Signed-off-by: Nikita Kiryanov
> ---
> Changes in V4:
> - No changes.
>
> Changes in V3:
> - No changes
It's easier to Cc Simon on patches related to Patman or Buildman.
Signed-off-by: Masahiro Yamada
Cc: Simon Glass
---
doc/git-mailrc | 2 ++
1 file changed, 2 insertions(+)
diff --git a/doc/git-mailrc b/doc/git-mailrc
index 70405f2..0fba100 100644
--- a/doc/git-mailrc
+++ b/doc/git-mailrc
@@ -
On Wed, Aug 20, 2014 at 5:38 PM, Nikita Kiryanov wrote:
> Currently, CONFIG_SPL_SPI_* #defines are used for controlling SPI boot in
> SPL. These #defines do not allow the user to select SPI mode for the SPI flash
> (there's no CONFIG_SPL_SPI_MODE, so the SPI mode is hardcoded in
> spi_spl_load.c),
"buildman [options]" is displayed by default.
Append the rest of help messages to parser.usage
instead of replacing it.
Signed-off-by: Masahiro Yamada
---
tools/buildman/buildman.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/buildman/buildman.py b/tools/buildman/
"patman [options]" is displayed by default.
Append the rest of help messages to parser.usage
instead of replacing it.
Signed-off-by: Masahiro Yamada
---
tools/patman/patman.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/patman/patman.py b/tools/patman/patman.py
in
Hello Lukasz,
In the dfu spez [1] chapter 4.2.1 the following fields are specified:
bDeviceClass = 00h (Description: „see interface“), currently set in
U-Boot to 2.
bDeviceSubClass = 00h (Description: „see interface“), currently set in
U-Boot to 2.
bcdUSB = h (Description: USB specificatio
On Thursday, August 21, 2014 at 06:11:16 AM, Ye Li wrote:
> The TDAR bit is set when the descriptors are all out from TX ring, but the
> descriptor properly is in transmitting not READY.
I don't quite understand this, can you please rephrase ?
> These are two signals,
> and in Ic simulation, we f
Hi Simon,
I noticed a minor issue of Patman by chance.
For example, git log is as follows:
commit da5ee79915c54bf9ac5b1a82a7241a88ff214e4e
Author: Masahiro Yamada
Date: Thu Aug 21 13:14:31 2014 +0900
foo: test
Blah Blah
Signed-off-by: Masahiro Yamada
Suggested-by
The TDAR bit is set when the descriptors are all out from TX ring, but the
descriptor properly is in transmitting not READY. These are two signals, and
in Ic simulation, we found the TDAR always clear prior than the READY bit of
last BD.
In mx6solox, we use a latest version of FEC IP. It looks
Hi Simon,
On Wed, 20 Aug 2014 13:13:13 -0600
Simon Glass wrote:
> > +def output_is_new():
> > +"""Check if the boards.cfg file is up to date.
> > +
> > +Returns:
> > + True if the boards.cfg file exists and is newer than any of
> > + *_defconfig, MAINTAINERS and Kconfig*. Fal
Hi Simon,
On Wed, 20 Aug 2014 13:10:52 -0600
Simon Glass wrote:
> I try to put an _ before private members to indicate that they should
> not be used outside the class. But It is not particularly important -
> just thought I'd mention it.
I will try my best to keep this in mind
when I send t
On Wednesday, August 20, 2014 at 11:34:30 PM, Otavio Salvador wrote:
> On Wed, Aug 20, 2014 at 6:24 PM, Fabio Estevam wrote:
> > From: Fabio Estevam
> >
> > Do not indicate an error when the buffer ready flag (FEC_TBD_READY) is
> > set.
> >
> > Without this change, mx6solox is not capable of do
On Wednesday, August 20, 2014 at 11:24:36 PM, Fabio Estevam wrote:
> From: Fabio Estevam
>
> Do not indicate an error when the buffer ready flag (FEC_TBD_READY) is set.
>
> Without this change, mx6solox is not capable of doing TFTP transfers.
>
> Succesfully tested on mx25, mx28, mx51, mx53, mx
On Wednesday, August 20, 2014 at 11:24:35 PM, Fabio Estevam wrote:
> From: Fabio Estevam
>
> mx6solox has a requirement for 64 bytes alignment for RX DMA transfer.
>
> Adjust it accordingly.
>
> Signed-off-by: Fabio Estevam
> ---
> Changes since v1:
> - Avoid too many ifdef's by providing a dm
Hi Fabio,
I feel the name "ARCH_DMA_MINALIGN_MX6SX" is not good here. Because the 64
bytes alignment is only required by the DMA engine in FEC controller, not a
ARCH DMA value.
Best regards,
Ye Li
On 8/21/2014 5:24 AM, Fabio Estevam wrote:
> From: Fabio Estevam
>
> mx6solox has a requirem
Hi Simon.
Thanks for your review!
I have posted v3 (only comments updates).
And some comments below:
On Wed, 20 Aug 2014 12:43:22 -0600
Simon Glass wrote:
> > +
> > + sed -n -e 's/^CONFIG_\(SPL\|TPL\)=y$/\1/p' $KCONFIG_CONFIG | \
> > +
Commit 51148790 added scripts/multiconfig.py written in Python 2
to adjust Kconfig for U-Boot.
It has been hard for Python 3 users because Python 2 and Python 3
are not compatible with each other.
We are not happy about adding a new host tool dependency
(in this case, Python version dependency) f
On Wed, Aug 20, 2014 at 12:29:57PM -0700, York Sun wrote:
> Tom,
>
> The following changes since commit 6d1966e1236838c8c59d58459901283a0e72:
>
> env_fat.c: Make sure our buffer is cache aligned (2014-08-09 11:26:34 -0400)
>
> are available in the git repository at:
>
> git://git.denx.
Hi Simon,
I found 'Commit-notes:' is not working correctly.
It seems a bit fatal. Could you fix it asap, please?
I bisected and the first bad commit is:
commit cda2a611520e679495e7d2cf8e436b0df9afc675
patman: Move the 'git log' command into a function
How to repeat the bug
-
Hi Bryan,
On 20 August 2014 11:24, Bryan Wu wrote:
> Hi Simon, Tom and Stephen,
>
> Could you guys review this patch which solved the issue York reported?
>
Sorry, busy week, will get to it soon though.
Regards,
Simon
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On Wed, Aug 20, 2014 at 6:24 PM, Fabio Estevam wrote:
> From: Fabio Estevam
>
> Do not indicate an error when the buffer ready flag (FEC_TBD_READY) is set.
>
> Without this change, mx6solox is not capable of doing TFTP transfers.
>
> Succesfully tested on mx25, mx28, mx51, mx53, mx6q, mx6sl and m
From: Fabio Estevam
Do not indicate an error when the buffer ready flag (FEC_TBD_READY) is set.
Without this change, mx6solox is not capable of doing TFTP transfers.
Succesfully tested on mx25, mx28, mx51, mx53, mx6q, mx6sl and mx6sx.
Signed-off-by: Fabio Estevam
---
Changes since v1:
- None
From: Fabio Estevam
mx6solox has a requirement for 64 bytes alignment for RX DMA transfer.
Adjust it accordingly.
Signed-off-by: Fabio Estevam
---
Changes since v1:
- Avoid too many ifdef's by providing a dma_rx_align() funtion as suggested
by Otavio
drivers/net/fec_mxc.c | 17 ++
On Wed, Aug 20, 2014 at 6:11 PM, Otavio Salvador
wrote:
>> Not sure I understood your suggestion. Care to provide an example?
>
> static int _rx_alignment()
> {
> #ifdef SX
> static int v = ??;
> #else
> static int v = ??;
> #endif
>
> return v;
Understood it now. Will do like this i
On Wed, Aug 20, 2014 at 5:48 PM, Fabio Estevam wrote:
> On Wed, Aug 20, 2014 at 4:38 PM, Otavio Salvador
> wrote:
>> On Wed, Aug 20, 2014 at 4:01 PM, Fabio Estevam wrote:
>>> From: Fabio Estevam
>>>
>>> mx6solox has a requirement for 64 bytes alignment for RX DMA transfer.
>>>
>>> Adjust it acc
Hi,
If one wants to have support for usb console (instead of serial) for u-boot
using a specific USB host controller like the Cypress 7C63xxx family what is
the correct approach?
Is usbtty.c I need to start looking into, with all the necessary chip specific
changes that need to be added, or is
There's no need to use loff_t to specify in-memory offset; size_t is
smaller and is guaranteed to be sufficient to represent any memory
object size.
Signed-off-by: Max Filippov
---
drivers/net/ethoc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethoc.c b/d
From: Chris Zankel
The 'ethoc' device could also be configured to have a private memory
region instead of having access to the main memory. In that case,
the packets must be copied into (transmit) or out of (receive) that
memory.
This behavior is configured by defining CONFIG_SYS_ETHOC_BUFFER_AD
From: Chris Zankel
The Xtensa processor architecture is a configurable, extensible,
and synthesizable 32-bit RISC processor core provided by Cadence.
This is the first part of the basic architecture port with changes to
common files. The 'arch/xtensa' directory, and boards and additional
drivers
Hello,
I'm getting some troubles booting FreeBSD on Banana Pi.
I wrote simple script that creates bootable SD card image for FreeBSD OS.
#!/bin/bash
cd /root/banana
rm /root/banana/banana.img
truncate -s 940M banana.img
mdconfig -f banana.img -u0
gpart create -s mbr md0
gpart add -b 1m -s 64m -t
Introduce MDIO communication routines. Scan MDIO bus at reset to find
attached PHYs and see if they support gigabit speeds. If they do check
their gigabit control register: if gigabit autonegotiation is enabled
clear it and reset the PHY.
This allows using OpenCores 10/100 MAC with gigabit PHY con
series is also available in the following git tree:
git://github.com/jcmvbkbc/u-boot-xtensa.git tags/xtensa-for-mainline-20140820
The port has been done mainly by Chris Zankel. I've been maintaining it
internally for some time now and I'll maintain it upstream.
Chris Zankel (5):
From: Chris Zankel
The Xtensa processor architecture is a configurable, extensible,
and synthesizable 32-bit RISC processor core provided by Tensilica, inc.
This is the second part of the basic architecture port, adding the
'arch/xtensa' directory and a readme file.
Signed-off-by: Chris Zankel
From: Chris Zankel
Signed-off-by: Chris Zankel
Signed-off-by: Max Filippov
---
arch/xtensa/include/asm/arch-dc232b/core.h| 422 ++
arch/xtensa/include/asm/arch-dc232b/tie-asm.h | 120
arch/xtensa/include/asm/arch-dc232b/tie.h | 129
3 files cha
From: Chris Zankel
The 'xtfpga' board is actually a set of FPGA evaluation boards that
can be configured to run an Xtensa processor.
- Avnet Xilinx LX60
- Avnet Xilinx LX110
- Avnet Xilinx LX200
- Xilinx ML605
- Xilinx KC705
These boards share the same components (open-ethernet, ns16550 se
xtensa linker script cannot be preprocessed with -ansi option specified,
so xtensa needs a way to override it.
Signed-off-by: Max Filippov
---
Makefile | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Makefile b/Makefile
index 666d291..344492f 100644
--- a/Makefile
+++ b/Mak
On Wed, Aug 20, 2014 at 4:38 PM, Otavio Salvador
wrote:
> On Wed, Aug 20, 2014 at 4:01 PM, Fabio Estevam wrote:
>> From: Fabio Estevam
>>
>> mx6solox has a requirement for 64 bytes alignment for RX DMA transfer.
>>
>> Adjust it accordingly.
>>
>> Signed-off-by: Fabio Estevam
>
> I'd use a stati
Hi Vasili,
On 20.08.14 18:10, Vasili Galka wrote:
> Hi Andreas,
>
> I'm trying to verify the correct build of all AVR32 boards. What is
> the recommended toolchain to use?
it depends, at least you should use a avr32-linux toolchain. The
avr32-elf one builds u-boot fine but has some runtime flaws
Signed-off-by: Roger Meier
Cc: Masahiro Yamada
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Simon Glass
---
Changes for v2:
- remove boards.cfg within make distclean instead of mrproper
- use mrproper instead of distclean within MAKEALL
Changes for v3:
- use @rm instead of rm as suggested by M
On 08/19/2014 06:40 AM, Valentin Longchamp wrote:
> There is the requirement on the chassis's backplane that when the clocks
> have been enabled, they then should not disappear.
>
> Resetting the Zarlink clocking chips at unit reset violates this
> requirement because the backplane clocks are not
On 08/13/2014 01:24 AM, Valentin Longchamp wrote:
> When u-boot initializes the RAM (early in boot) it looks for the "pram"
> env variable to know which is area it cannot use. If the "pram" env variable
> is not found, the default CONFIG_PRAM value is used.
>
> This value used to be 0 (no protecti
On 08/13/2014 03:19 AM, shh@gmail.com wrote:
> From: Shaohui Xie
>
> XFI is supported on T4QDS-XFI board, which removed slot3, and four LANEs
> of serdes2 are routed to a SFP+ cages, which to house fiber cable or
> direct attach cable(copper), the copper cable is used to emulate the
> 10GBASE
On Wed, Aug 20, 2014 at 4:01 PM, Fabio Estevam wrote:
> From: Fabio Estevam
>
> mx6solox has a requirement for 64 bytes alignment for RX DMA transfer.
>
> Adjust it accordingly.
>
> Signed-off-by: Fabio Estevam
I'd use a static method to return the value, so you avoid some of #ifdef
--
Otavio
On 07/23/2014 06:03 AM, Vijay Rai wrote:
> This Patch updates error print for QE which should be easily understood
>
> Signed-off-by: Vijay Rai
> ---
Applied to u-boot-mpc85xx master branch, awaiting for upstream.
York
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On 07/01/2014 11:14 PM, Shaveta Leekha wrote:
> If hwconfig does not contains "en_cpc" then by default all cpcs are enabled
> If this config is defined then only those individual cpcs which are defined
> in the subargument of "en_cpc" will be enabled e.g en_cpc:cpc1,cpc2; (this
> will enable cpc1 a
Tom,
The following changes since commit 6d1966e1236838c8c59d58459901283a0e72:
env_fat.c: Make sure our buffer is cache aligned (2014-08-09 11:26:34 -0400)
are available in the git repository at:
git://git.denx.de/u-boot-mpc85xx.git master
for you to fetch changes up to f38391793f1a5c62
On 07/23/2014 02:27 AM, yuantian.t...@freescale.com wrote:
> From: Tang Yuantian
>
> Add deep sleep support in SPI/SD boot. The destination address
> second stage uboot image is loaded to is changed because
> currently this address will be used by kernel which means
> we can't reserve it for resu
On 07/23/2014 02:27 AM, yuantian.t...@freescale.com wrote:
> From: Tang Yuantian
>
> bootflag as a parameter is passed to board_init_f().
> But it is not actually used in this function.
> Make it effective by assigned it to gd->flags.
>
> Signed-off-by: Tang Yuantian
> ---
Applied to u-boot-mp
On 03/18/2014 07:47 PM, Dongsheng Wang wrote:
> From: Jason Jin
>
> T1042 has internal display interface unit (DIU) for driving video.
> T1042RDB supports video mode via
> -LCD using TI enconder
> -HDMI type interface via HDMI encoder
>
> Chrontel, CH7301C encoder which is I2C programmable is us
On 03/18/2014 07:47 PM, Dongsheng Wang wrote:
> From: Wang Dongsheng
>
> The ch7301 encoder not only used in t1040qds platform, so we split
> it for t1042rdb and LSx platform.
>
> Signed-off-by: Wang Dongsheng
> ---
> V2: No Change
Applied to u-boot-mpc85xx master branch, awaiting for upstream
On 08/18/2014 02:00 AM, Thierry Reding wrote:
From: Thierry Reding
To work around potential issues with explicit cache maintenance of the
RX and TX descriptor rings, allocate them from a pool of uncached memory
if the architecture supports it.
diff --git a/drivers/net/rtl8169.c b/drivers/net
On 08/18/2014 02:00 AM, Thierry Reding wrote:
From: Thierry Reding
RX and TX descriptor rings should be aligned to 256 byte boundaries. Use
the DEFINE_ALIGN_BUFFER() macro to define the buffers so that they don't
have to be manually aligned later on. Also make sure that the buffers do
align to
On 08/18/2014 02:00 AM, Thierry Reding wrote:
From: Thierry Reding
Some boards, most notably those with a PCIe ethernet NIC, require this
to avoid cache coherency problems. Since the option adds very little
code and overhead enable it across all Tegra generations. Other drivers
may also start s
On 08/18/2014 02:00 AM, Thierry Reding wrote:
From: Thierry Reding
Implement an API that can be used by drivers to allocate memory from a
poll that is mapped uncached. This is useful if drivers would otherwise
s/poll/pool/
need to do extensive cache maintenance (or explicitly maintaining th
On 20 August 2014 05:47, Masahiro Yamada wrote:
> I guess some developers are already getting sick of this tool
> because it takes a few minites to generate the boards.cfg
> on reasonable computers.
>
> This commit makes it about 4 times faster.
> You might not be satisfied at all, but better than
On 08/18/2014 02:00 AM, Thierry Reding wrote:
From: Thierry Reding
size is always non-negative, so it should be unsigned, whereas the
address and size can be larger than 32 bit on 64-bit architectures.
Change the mmu_set_region_dcache_behaviour() to use these types in
anticipation of making the
On 20 August 2014 05:47, Masahiro Yamada wrote:
> It looks silly to regenerate the boards.cfg even when it is
> already up to date.
>
> The tool should exit with doing nothing if the boards.cfg is newer
> than any of defconfig, Kconfig and MAINTAINERS files.
>
> Specify -f (--force) option to get
On 08/18/2014 02:00 AM, Thierry Reding wrote:
From: Thierry Reding
This series attempts to fix a long-standing problem in the rtl8169 driver
(though the same problem may exist in other drivers as well). Let me first
explain what exactly the issue is:
The rtl8169 driver provides a set of RX and
HI Masahiro,
On 20 August 2014 05:47, Masahiro Yamada wrote:
> This tool deletes the incomplete boards.cfg
> if it encounters an error or is is terminated by the user.
>
> I notice some problems even though they rarely happen.
>
> [1] The boards.cfg is removed if the program is terminated
> durin
On 20 August 2014 05:47, Masahiro Yamada wrote:
> When an error occurs or the program is terminated by the user
> on the way, the destructer __del__ of class Slot is invoked and
> the work directories are removed.
>
> We have to make sure there are no subprocesses (in this case,
> "make O= ...") u
On 20 August 2014 05:47, Masahiro Yamada wrote:
> The tools/genboardscfg.py expects all the Kconfig and defconfig are
> written correctly. Imagine someone accidentally has broken a board.
> Error-out just for one broken board is annoying for the other
> developers. Let the tool skip insane board
On 20 August 2014 05:47, Masahiro Yamada wrote:
> tools/genboardscfg.py expects all the boards have MAINTAINERS.
> If someone adds a new board but misses to add its MAINTAINERS file,
> tools/genboardscfg.py fails to generate the boards.cfg file.
> It is annoying for the other developers.
>
> This
On 08/18/2014 01:16 AM, Thierry Reding wrote:
From: Thierry Reding
Add support for the PCIe controller found on some generations of Tegra.
Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has 3 root
ports with a total of 6 lanes and Tegra124 has 2 root ports with a total
of 5 lanes.
On 20 August 2014 05:47, Masahiro Yamada wrote:
> Kconfig in U-Boot creates a temporary file configs/.tmp_defconfig
> during processing "make _defconfig". The temporary file
> might be left over for some reasons.
>
> Just in case, tools/genboardscfg.py should make sure to
> not read such garbage
From: Fabio Estevam
mx6solox has a requirement for 64 bytes alignment for RX DMA transfer.
Adjust it accordingly.
Signed-off-by: Fabio Estevam
---
drivers/net/fec_mxc.c | 21 ++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/n
From: Fabio Estevam
Do not indicate an error when the buffer ready flag (FEC_TBD_READY) is set.
Without this change, mx6solox is not capable of doing TFTP transfers.
Succesfully tested on mx25, mx28, mx51, mx53, mx6q, mx6sl and mx6sx.
Signed-off-by: Fabio Estevam
---
drivers/net/fec_mxc.c |
Hi Masahiro,
On 20 August 2014 05:47, Masahiro Yamada wrote:
>
> This series depends on the following prerequisites
>
> http://patchwork.ozlabs.org/patch/380316/
> http://patchwork.ozlabs.org/patch/376222/
>
>
>
> Masahiro Yamada (7):
> tools/genboardscfg.py: ignore defconfigs starting with a d
On 08/18/2014 01:16 AM, Thierry Reding wrote:
From: Thierry Reding
The Jetson TK1 has an ethernet NIC connected to the PCIe bus and routes
the second root port to a miniPCIe slot. Enable the PCIe controller and
the network driver to allow the device to boot over the network.
diff --git a/arc
On 08/18/2014 01:16 AM, Thierry Reding wrote:
From: Thierry Reding
The Jetson TK1 has an ethernet NIC connected to the PCIe bus and routes
the second root port to a miniPCIe slot. Enable the PCIe controller and
diff --git a/arch/arm/dts/tegra124-jetson-tk1.dts
b/arch/arm/dts/tegra124-jetson
On 08/18/2014 01:16 AM, Thierry Reding wrote:
From: Thierry Reding
Add the device tree node for the PCIe controller found on Tegra124 SoCs.
This matches what's proposed for the kernel, so,
Acked-by: Stephen Warren
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On 08/18/2014 01:16 AM, Thierry Reding wrote:
From: Thierry Reding
Add a device tree node for the GIC v2 found on the Cortex-A15 CPU
complex of Tegra124. U-Boot doesn't use this but subsequent patches will
add device tree nodes that reference it by phandle.
Matches the kernel, so,
Acked-by: S
Hi Masahiro,
On 16 August 2014 19:56, Masahiro Yamada wrote:
>
> Commit 51148790 added scripts/multiconfig.py written in Python 2
> to adjust Kconfig for U-Boot.
>
> The problem is that Python 2 and Python 3 are not compatible
> with each other and some users are using Python 3.
>
> We are not ha
On 08/18/2014 01:16 AM, Thierry Reding wrote:
From: Thierry Reding
The Beaver has an ethernet NIC connected to the PCIe bus. Enable the
PCIe controller and the network device driver so that the device can
boot over the network.
In addition the board has a mini-PCIe expansion slot.
diff --gi
On 08/18/2014 01:16 AM, Thierry Reding wrote:
From: Thierry Reding
Add the device tree node for the PCIe controller found on Tegra30 SoCs.
diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi
+ pcie-controller {
+ compatible = "nvidia,tegra30-pcie";
+
On 08/18/2014 01:16 AM, Thierry Reding wrote:
From: Thierry Reding
The TrimSlice has an ethernet NIC connected to the PCIe bus. Enable the
PCIe controller and the network driver so that the device can boot over
the network.
diff --git a/arch/arm/dts/tegra20-trimslice.dts
b/arch/arm/dts/tegr
On 08/18/2014 01:16 AM, Thierry Reding wrote:
From: Thierry Reding
Add the device tree node for the PCIe controller found on Tegra20 SoCs.
This matches the kernel, so
Acked-by: Stephen Warren
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On 08/18/2014 01:16 AM, Thierry Reding wrote:
From: Thierry Reding
Add the PCIe and SATA lane configuration to the Jetson TK1 device tree,
so that the XUSB pad controller can be appropriately configured.
Aside from the differing #address-cells at the top-level of the DT, this
matches what's
On 08/18/2014 01:16 AM, Thierry Reding wrote:
From: Thierry Reding
The XUSB pad controller is used for pinmuxing of the XUSB, PCIe and SATA
lanes.
Aside from the differing #address-cells at the top-level of the DT, this
matches what's been proposed for the Linux kernel, so,
Acked-by: Steph
On 08/18/2014 01:16 AM, Thierry Reding wrote:
From: Thierry Reding
This controller was introduced on Tegra114 to handle XUSB pads. On
Tegra124 it is also used for PCIe and SATA pin muxing and PHY control.
Only the Tegra124 PCIe and SATA functionality is currently implemented,
with weak symbols
On 08/18/2014 01:16 AM, Thierry Reding wrote:
From: Thierry Reding
Implement the powergate API that allows various power partitions to be
power up and down.
diff --git a/arch/arm/cpu/tegra-common/powergate.c
b/arch/arm/cpu/tegra-common/powergate.c
+static int tegra_powergate_set(enum teg
On 08/18/2014 01:16 AM, Thierry Reding wrote:
From: Thierry Reding
This reset is required for PCIe and the corresponding ID therefore needs
to be defined.
It might be worth mentioning in the commit description why this patch
does different things for each SoC; namely that some SoCs already d
On 08/18/2014 01:16 AM, Thierry Reding wrote:
From: Thierry Reding
This function is required by PCIe and SATA. This patch implements it on
Tegra20, Tegra30 and Tegra124. It isn't implemented for Tegra114 because
it doesn't support PCIe or SATA.
I see no issue with the structure of the code so
On 08/14/2014 08:59 PM, Simon Glass wrote:
> Buildman has been around for a little over a year and is used by a fair
> number of U-Boot developers. However quite a few people still use MAKEALL.
>
> Buildman was intended to replace MAKEALL, so perhaps now is a good time to
> start that process.
>
On 08/18/2014 07:55 PM, Alison Wang wrote:
> From: Wang Huan
>
> This patch adds the TWR_LCD_RGB card/HDMI options and the common
> configuration for DCU on LS1021ATWR board.
>
> Signed-off-by: Alison Wang
> ---
> Change log:
> v5: Change the patch order.
> v4: Add commit messages.
> v3: New
Hi Simon, Tom and Stephen,
Could you guys review this patch which solved the issue York reported?
Thanks,
-Bryan
On Fri, Aug 15, 2014 at 4:51 PM, Bryan Wu wrote:
> Commit b3dd64f5d537 "bootm: use genimg_get_kernel_addr()" introduced
> a bug for booting FIT image. It's because calling fit_parse_
On 08/18/2014 07:55 PM, Alison Wang wrote:
> From: Jingchang Lu
>
> On vybrid, lpuart's registers are 8-bit. On LS102xA, lpuart's registers
> are 32-bit. This patch adds the support for 32-bit registers on
> LS102xA.
>
> Signed-off-by: Jingchang Lu
> Signed-off-by: Yuan Yao
> ---
> Change log:
On 19 August 2014 02:22, Thierry Reding wrote:
> From: Thierry Reding
>
> When creating build directories also create parents as necessary. This
> fixes a failure when building a hierarchical branch (i.e. foo/bar).
>
> Signed-off-by: Thierry Reding
Acked-by: Simon Glass
___
Albert,
Please pull u-boot-tegra/master into ARM/master. Thanks!
./MAKEALL -s tegra AOK, checkpatch.pl is OK, and ./MAKEALL -a arm only
shows failures that were already present in ARM/master.
The following changes since commit 1899fac925eda817e12234aef3d01d354788662e:
Merge branch 'u-boot-sun
Hi Andreas,
I'm trying to verify the correct build of all AVR32 boards. What is
the recommended toolchain to use?
I tried the one that comes with Ubuntu:
sudo apt-get install gcc-avr binutils-avr gdb-avr avr-libc avrdude
But it does not work, I get the following build errors:
Building atngw100
On Wed, Aug 20, 2014 at 09:34:13AM +0200, Lukasz Majewski wrote:
> Hi Felipe,
>
> > On Tue, Aug 19, 2014 at 09:08:00PM +0530, Kishon Vijay Abraham I
> > wrote:
> > >
> > >
> > > On Monday 18 August 2014 08:26 PM, Lukasz Majewski wrote:
> > > > Hi Kishon,
> > > >
> > > >>> Explicity set the max
Hi Albert,
please pull from u-boot-imx, thanks !
The following changes since commit 1899fac925eda817e12234aef3d01d354788662e:
Merge branch 'u-boot-sunxi/master' into 'u-boot-arm/master'
(2014-08-09 16:48:34 +0200)
are available in the git repository at:
git://www.denx.de/git/u-boot-imx.gi
Hi Thierry,
On 20 August 2014 00:36, Thierry Reding wrote:
> On Tue, Aug 19, 2014 at 03:28:09PM -0600, Simon Glass wrote:
>> Hi Thierry,
>>
>> On 19 August 2014 07:12, Thierry Reding wrote:
>> > On Tue, Aug 19, 2014 at 06:55:18AM -0600, Simon Glass wrote:
>> >> On 19 August 2014 05:35, Thierry R
2014-08-19 20:01 GMT+09:00 Stefan Roese :
>
> Please use SPDX license identifiers instead. Please fix this globally.
>
Thanks!
I have sent a follow up patch.
http://patchwork.ozlabs.org/patch/381530/
--
Best Regards
Masahiro Yamada
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