svn commit: r303439 - head/sys/modules/dtrace/dtrace

Author: br Date: Thu Jul 28 13:18:10 2016 New Revision: 303439 URL: https://svnweb.freebsd.org/changeset/base/303439 Log: Build DTrace assym.o with -msoft-float flag for RISC-V so we have correct flag in ELF file. Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Modified: head/sys/modul

svn commit: r303440 - in head/sys/modules: i2c/iicbb uart

Author: br Date: Thu Jul 28 13:21:45 2016 New Revision: 303440 URL: https://svnweb.freebsd.org/changeset/base/303440 Log: Build ofw_bus_if.h for modules for RISC-V. Modified: head/sys/modules/i2c/iicbb/Makefile head/sys/modules/uart/Makefile Modified: head/sys/modules/i2c/iicbb/Makefile ==

svn commit: r303453 - in head: share/mk sys/conf

Author: br Date: Thu Jul 28 17:18:02 2016 New Revision: 303453 URL: https://svnweb.freebsd.org/changeset/base/303453 Log: Normalise the CWARNFLAGS inter-word spacing: remove all leading and trailing space, and convert multiple consecutive spaces to single space. This helps to keep build

svn commit: r303479 - head/sys/cddl/dev/fbt/riscv

Author: br Date: Fri Jul 29 12:29:17 2016 New Revision: 303479 URL: https://svnweb.freebsd.org/changeset/base/303479 Log: Remove unused variables. Modified: head/sys/cddl/dev/fbt/riscv/fbt_isa.c Modified: head/sys/cddl/dev/fbt/riscv/fbt_isa.c =

svn commit: r303480 - in head/sys/modules/dtrace: . dtraceall

Author: br Date: Fri Jul 29 12:30:33 2016 New Revision: 303480 URL: https://svnweb.freebsd.org/changeset/base/303480 Log: Include FBT to modules build on RISC-V. Modified: head/sys/modules/dtrace/Makefile head/sys/modules/dtrace/dtraceall/dtraceall.c Modified: head/sys/modules/dtrace/Makef

svn commit: r303660 - in head/sys: boot/fdt/dts/riscv cddl/contrib/opensolaris/uts/common/sys cddl/dev/dtrace/riscv conf riscv/conf riscv/htif riscv/include riscv/riscv

(r303660) @@ -1,5 +1,5 @@ /*- - * Copyright (c) 2015 Ruslan Bukin + * Copyright (c) 2015-2016 Ruslan Bukin * All rights reserved. * * Portions of this software were developed by SRI International and the @@ -37,8 +37,8 @@ /dts-v1/; / { - model = "UC Berkeley Spike Simu

svn commit: r303908 - in head/sys: boot/fdt/dts/riscv conf riscv/conf riscv/htif riscv/include riscv/riscv

ALL 10 #defineEXCP_MACHINE_ECALL 11 #defineEXCP_INTR (1ul << 63) -#defineEXCP_INTR_SOFTWARE 0 -#defineEXCP_INTR_TIMER 1 -#defineEXCP_INTR_HTIF 2 #define

svn commit: r303911 - in head: share/mk sys/modules/dtrace/dtrace

Author: br Date: Wed Aug 10 13:32:27 2016 New Revision: 303911 URL: https://svnweb.freebsd.org/changeset/base/303911 Log: Remove extra -msoft-float flags settings. This helps to build firmware modules. Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Modified: head/share/mk/bsd.cpu.mk

svn commit: r303915 - head/sys/tools

Author: br Date: Wed Aug 10 13:49:17 2016 New Revision: 303915 URL: https://svnweb.freebsd.org/changeset/base/303915 Log: Consider CROSS_BINUTILS_PREFIX environment variable so we use correct objdump. Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Modified: head/sys/tools/embed_mfs.sh

svn commit: r303959 - in head: share/mk sys/modules/dtrace/dtrace

Author: br Date: Thu Aug 11 13:42:31 2016 New Revision: 303959 URL: https://svnweb.freebsd.org/changeset/base/303959 Log: Revert r303911 "Remove extra -msoft-float flags settings." This was not properly tested. Modified: head/share/mk/bsd.cpu.mk head/sys/modules/dtrace/dtrace/Makefile Mo

svn commit: r294227 - in head/lib: libc libc/gen libc/riscv libc/riscv/gen libc/riscv/sys libc/xdr libstand

}/riscv/Symbol.map Added: head/lib/libc/riscv/SYS.h == --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/lib/libc/riscv/SYS.h Sun Jan 17 15:21:23 2016(r294227) @@ -0,0 +1,68 @@ +/*- + * Co

svn commit: r294262 - head/lib/libc

Author: br Date: Mon Jan 18 09:36:10 2016 New Revision: 294262 URL: https://svnweb.freebsd.org/changeset/base/294262 Log: Fix compilation on MIPS (typo introduced in r294227). Modified: head/lib/libc/Makefile Modified: head/lib/libc/Makefile ==

svn commit: r294279 - head/sys/sys

Author: br Date: Mon Jan 18 16:54:26 2016 New Revision: 294279 URL: https://svnweb.freebsd.org/changeset/base/294279 Log: Add RISC-V relocation types. Reviewed by: emaste Modified: head/sys/sys/elf_common.h Modified: head/sys/sys/elf_common.h ===

svn commit: r294282 - head/sys/riscv/include

Author: br Date: Mon Jan 18 17:49:32 2016 New Revision: 294282 URL: https://svnweb.freebsd.org/changeset/base/294282 Log: Correct RISC-V exception types. Modified: head/sys/riscv/include/riscvreg.h Modified: head/sys/riscv/include/riscvreg.h ==

svn commit: r294571 - in head/usr.bin/xlint: arch/riscv lint1

Author: br Date: Fri Jan 22 16:32:22 2016 New Revision: 294571 URL: https://svnweb.freebsd.org/changeset/base/294571 Log: Add support for RISC-V ISA. Reviewed by: andrew Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Differential Revision:https://reviews.freebsd.org/D5014 Add

svn commit: r294573 - in head/contrib/jemalloc/include/jemalloc: . internal

Author: br Date: Fri Jan 22 16:37:26 2016 New Revision: 294573 URL: https://svnweb.freebsd.org/changeset/base/294573 Log: Add configuration for RISC-V ISA. Reviewed by: emaste Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Differential Revision:https://reviews.freebsd.org/D502

svn commit: r294574 - in head/contrib/llvm/projects/libunwind: include src

Author: br Date: Fri Jan 22 16:42:06 2016 New Revision: 294574 URL: https://svnweb.freebsd.org/changeset/base/294574 Log: Add stubs for RISC-V ISA so libunwind can be compiled. Reviewed by: emaste Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Differential Revision:https://rev

svn commit: r294577 - in head/contrib/compiler-rt/lib: builtins sanitizer_common

Author: br Date: Fri Jan 22 16:59:06 2016 New Revision: 294577 URL: https://svnweb.freebsd.org/changeset/base/294577 Log: Add support for RISC-V ISA. Reviewed by: emaste Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Differential Revision:https://reviews.freebsd.org/D5021 Mod

svn commit: r294623 - head/libexec/rtld-elf/riscv

Author: br Date: Sat Jan 23 11:46:52 2016 New Revision: 294623 URL: https://svnweb.freebsd.org/changeset/base/294623 Log: Follow r293066 adding a generalized exec hook for RISC-V as well. Modified: head/libexec/rtld-elf/riscv/rtld_machdep.h Modified: head/libexec/rtld-elf/riscv/rtld_machdep.

svn commit: r294632 - head/sys/dev/sound/pci

== --- head/sys/dev/sound/pci/hdspe.h Sat Jan 23 12:56:28 2016 (r294631) +++ head/sys/dev/sound/pci/hdspe.h Sat Jan 23 13:34:55 2016 (r294632) @@ -1,5 +1,5 @@ /*- - * Copyright (c) 2012 Ruslan Bukin

svn commit: r294634 - head/contrib/gcc/config/riscv64

Author: br Date: Sat Jan 23 15:33:11 2016 New Revision: 294634 URL: https://svnweb.freebsd.org/changeset/base/294634 Log: Add a minimal gcc config for RISC-V. This is required to build csu. Reviewed by: andrew Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Differential Revision:

svn commit: r294662 - head/lib/libproc

Author: br Date: Sun Jan 24 12:10:29 2016 New Revision: 294662 URL: https://svnweb.freebsd.org/changeset/base/294662 Log: Add support for RISC-V ISA. Reviewed by: andrew Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Differential Revision:https://reviews.freebsd.org/D5040 Mod

svn commit: r294664 - head/contrib/elftoolchain/libelf

Author: br Date: Sun Jan 24 15:12:49 2016 New Revision: 294664 URL: https://svnweb.freebsd.org/changeset/base/294664 Log: Add config for RISC-V ISA. Reviewed by: emaste Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Differential Revision:https://reviews.freebsd.org/D5046 Modi

svn commit: r294665 - head/usr.bin/ldd

Author: br Date: Sun Jan 24 15:15:57 2016 New Revision: 294665 URL: https://svnweb.freebsd.org/changeset/base/294665 Log: We don't support a.out executables on RISC-V. Reviewed by: emaste Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Differential Revision:https://reviews.free

svn commit: r294713 - head/cddl/lib

Author: br Date: Mon Jan 25 10:18:41 2016 New Revision: 294713 URL: https://svnweb.freebsd.org/changeset/base/294713 Log: We don't support libdtrace for RISC-V yet. Modified: head/cddl/lib/Makefile Modified: head/cddl/lib/Makefile =

svn commit: r294714 - head/lib

Author: br Date: Mon Jan 25 10:23:36 2016 New Revision: 294714 URL: https://svnweb.freebsd.org/changeset/base/294714 Log: Do build libproc and librtld_db for RISC-V as well. Modified: head/lib/Makefile Modified: head/lib/Makefile ==

svn commit: r294717 - head/lib

Author: br Date: Mon Jan 25 10:44:10 2016 New Revision: 294717 URL: https://svnweb.freebsd.org/changeset/base/294717 Log: Style. Modified: head/lib/Makefile Modified: head/lib/Makefile == --- head/lib/Makefile Mon

svn commit: r294736 - head/usr.bin

Author: br Date: Mon Jan 25 16:49:39 2016 New Revision: 294736 URL: https://svnweb.freebsd.org/changeset/base/294736 Log: Disable gprof and users on RISC-V, they don't build. Modified: head/usr.bin/Makefile Modified: head/usr.bin/Makefile =

svn commit: r294823 - head/secure/lib/libcrypto

Author: br Date: Tue Jan 26 14:17:39 2016 New Revision: 294823 URL: https://svnweb.freebsd.org/changeset/base/294823 Log: Add the openssl header for RISC-V. Copied from aarch64 as we can't generate it yet. Added: head/secure/lib/libcrypto/opensslconf-riscv.h (contents, props changed) Add

svn commit: r294831 - head/usr.sbin

Author: br Date: Tue Jan 26 14:34:40 2016 New Revision: 294831 URL: https://svnweb.freebsd.org/changeset/base/294831 Log: Remove uathload from build due to issue with GCC 5.2.0: "ld: --relax and -r may not be used together." Requires fixing ld command line arguments and testing. Modified:

svn commit: r294833 - head/lib/msun/riscv

Author: br Date: Tue Jan 26 14:40:41 2016 New Revision: 294833 URL: https://svnweb.freebsd.org/changeset/base/294833 Log: Add fenv.c for RISC-V. Copied from MIPS. Added: head/lib/msun/riscv/fenv.c (contents, props changed) Added: head/lib/msun/riscv/fenv.c =

svn commit: r294834 - head/gnu/lib/libgcc

Author: br Date: Tue Jan 26 14:45:21 2016 New Revision: 294834 URL: https://svnweb.freebsd.org/changeset/base/294834 Log: Make libgcc compilable on RISC-V. Modified: head/gnu/lib/libgcc/Makefile Modified: head/gnu/lib/libgcc/Makefile ==

svn commit: r294908 - head/lib/libthread_db/arch/riscv

is newly added) +++ head/lib/libthread_db/arch/riscv/libpthread_md.cWed Jan 27 10:34:07 2016(r294908) @@ -0,0 +1,104 @@ +/*- + * Copyright (c) 2015 Ruslan Bukin + * All rights reserved. + * + * Portions of this software were developed by SRI International and the + * University of

Re: svn commit: r294893 - head/lib/libdpv

I get this with GCC 5.2.0: /home/rb743/dev/freebsd-riscv/lib/libdpv/dialog_util.c:270:23: error: zero-length gnu_printf format string [-Werror=for mat-zero-length] sprintf(dargv[n++], ""); Ruslan On Wed, Jan 27, 2016 at 06:21:35AM +, Devin Teske wrote: > Author: dteske > Date: Wed Jan 27

svn commit: r294912 - head/lib/libthr/arch/riscv/include

, because file is newly added) +++ head/lib/libthr/arch/riscv/include/pthread_md.h Wed Jan 27 14:10:50 2016(r294912) @@ -0,0 +1,92 @@ +/*- + * Copyright (c) 2005 David Xu + * Copyright (c) 2015 Ruslan Bukin + * All rights reserved. + * + * Portions of this software were developed by SRI

svn commit: r295041 - in head/sys: boot/fdt/dts/riscv boot/ficl/riscv cddl/compat/opensolaris/sys cddl/contrib/opensolaris/uts/common/sys conf dev/hwpmc riscv/conf riscv/htif riscv/riscv sys

:00:00 1970 (empty, because file is newly added) +++ head/sys/boot/fdt/dts/riscv/spike.dts Fri Jan 29 15:12:31 2016 (r295041) @@ -0,0 +1,92 @@ +/*- + * Copyright (c) 2015 Ruslan Bukin + * All rights reserved. + * + * Portions of this software were developed by SRI International and

svn commit: r295250 - in head/sys: arm64/arm64 mips/mips riscv/riscv

Author: br Date: Thu Feb 4 11:52:53 2016 New Revision: 295250 URL: https://svnweb.freebsd.org/changeset/base/295250 Log: Fix build. Modified: head/sys/arm64/arm64/vm_machdep.c head/sys/mips/mips/vm_machdep.c head/sys/riscv/riscv/vm_machdep.c Modified: head/sys/arm64/arm64/vm_machdep.c =

svn commit: r295251 - in head/sys: arm/arm sparc64/sparc64

Author: br Date: Thu Feb 4 12:06:06 2016 New Revision: 295251 URL: https://svnweb.freebsd.org/changeset/base/295251 Log: Fix build. Modified: head/sys/arm/arm/vm_machdep.c head/sys/sparc64/sparc64/vm_machdep.c Modified: head/sys/arm/arm/vm_machdep.c ===

svn commit: r295253 - in head/sys/riscv: include riscv

Author: br Date: Thu Feb 4 12:49:28 2016 New Revision: 295253 URL: https://svnweb.freebsd.org/changeset/base/295253 Log: Reuse gp register for pcpu pointer. gp (global pointer) is used by compiler in userland only, so re-use it for pcpup in kernel, save it on stack on switching out to

svn commit: r295258 - in head/sys/riscv: include riscv

Author: br Date: Thu Feb 4 14:30:46 2016 New Revision: 295258 URL: https://svnweb.freebsd.org/changeset/base/295258 Log: Access pcpup using gp register. Modified: head/sys/riscv/include/asm.h head/sys/riscv/riscv/exception.S head/sys/riscv/riscv/swtch.S Modified: head/sys/riscv/include/

svn commit: r295508 - head/sys/riscv/htif

Author: br Date: Thu Feb 11 11:21:45 2016 New Revision: 295508 URL: https://svnweb.freebsd.org/changeset/base/295508 Log: Stop device enumeration when we see first empty slot. This fixes operation in QEMU and saves some booting time as well. Pointed out by: Sagar Karandikar Spons

svn commit: r295521 - in head/sys: boot/fdt/dts/riscv riscv/conf

) @@ -0,0 +1,92 @@ +/*- + * Copyright (c) 2016 Ruslan Bukin + * All rights reserved. + * + * Portions of this software were developed by SRI International and the + * University of Cambridge Computer Laboratory under DARPA/AFRL contract + * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRAS

Re: svn commit: r295561 - in head: include sys/mips/include sys/powerpc/include sys/sparc64/include sys/sys sys/x86/include

On RISC-V it fails with __uint128_t: struct fpregs { __uint128_t fp_x[32]; how to fix? Ruslan On Fri, Feb 12, 2016 at 07:38:20AM +, Konstantin Belousov wrote: > Author: kib > Date: Fri Feb 12 07:38:19 2016 > New Revision: 295561 > URL: https://svnweb.freebsd.org/changeset/base/2

svn commit: r295564 - head/sys/riscv/include

Author: br Date: Fri Feb 12 14:29:14 2016 New Revision: 295564 URL: https://svnweb.freebsd.org/changeset/base/295564 Log: Use __uint64_t type for floating point registers as compiler don't know about __uint128_t yet. Discussed with: theraven, kib Modified: head/sys/riscv/include/

Re: svn commit: r295561 - in head: include sys/mips/include sys/powerpc/include sys/sparc64/include sys/sys sys/x86/include

On Fri, Feb 12, 2016 at 04:13:53PM +0200, Konstantin Belousov wrote: > On Fri, Feb 12, 2016 at 01:22:04PM +0000, Ruslan Bukin wrote: > > On RISC-V it fails with __uint128_t: > > > > struct fpregs { > > __uint128_t fp_x[32]; > > > > how to fix?

svn commit: r295697 - head/sys/riscv/riscv

Author: br Date: Wed Feb 17 13:43:43 2016 New Revision: 295697 URL: https://svnweb.freebsd.org/changeset/base/295697 Log: Use callee-saved registers to pass args through fork_trampoline(). Modified: head/sys/riscv/riscv/swtch.S head/sys/riscv/riscv/vm_machdep.c Modified: head/sys/riscv/ris

svn commit: r295698 - head/sys/riscv/riscv

Author: br Date: Wed Feb 17 13:49:38 2016 New Revision: 295698 URL: https://svnweb.freebsd.org/changeset/base/295698 Log: Add the implementation of savectx(). Modified: head/sys/riscv/riscv/swtch.S Modified: head/sys/riscv/riscv/swtch.S ===

svn commit: r295699 - head/sys/riscv/riscv

Author: br Date: Wed Feb 17 14:13:25 2016 New Revision: 295699 URL: https://svnweb.freebsd.org/changeset/base/295699 Log: There is no need to pre save tp in cpu_fork(). Discussed with: jhb Modified: head/sys/riscv/riscv/vm_machdep.c Modified: head/sys/riscv/riscv/vm_machdep.c ==

svn commit: r295700 - head/sys/riscv/include

Author: br Date: Wed Feb 17 14:24:25 2016 New Revision: 295700 URL: https://svnweb.freebsd.org/changeset/base/295700 Log: Use better form representing 32 x 128-bit floating-point registers. Suggested by: kib Modified: head/sys/riscv/include/ucontext.h Modified: head/sys/riscv/include/uc

svn commit: r295701 - head/sys/riscv/include

Author: br Date: Wed Feb 17 14:32:03 2016 New Revision: 295701 URL: https://svnweb.freebsd.org/changeset/base/295701 Log: Add the implementation of atomic_swap_32(). Modified: head/sys/riscv/include/atomic.h Modified: head/sys/riscv/include/atomic.h ==

svn commit: r295758 - head/sys/conf

Author: br Date: Thu Feb 18 14:38:37 2016 New Revision: 295758 URL: https://svnweb.freebsd.org/changeset/base/295758 Log: Use medany (Medium/Anywhere) GCC code model for RISC-V. This will allow us to use bigger relocations and all the 64-bit VA space. Modified: head/sys/conf/kern.mk Modi

svn commit: r295761 - in head/sys/riscv: include riscv

Author: br Date: Thu Feb 18 15:28:57 2016 New Revision: 295761 URL: https://svnweb.freebsd.org/changeset/base/295761 Log: Increase kernel and user VA space. This allows us to boot with more than 128MB of physical memory. Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Modified: head/sy

svn commit: r292124 - in head: . etc/etc.riscv lib/csu/riscv lib/libc/riscv lib/libthr/arch/riscv lib/msun/riscv share/mk

} ${CFLAGS} -fPIC -DPIC -S -o ${.TARGET} ${.CURDIR}/crt1.c + sed ${SED_FIX_NOTE} ${.TARGET} + +Scrt1.o: Scrt1.s + ${CC} ${ACFLAGS} -c -o ${.TARGET} Scrt1.s + +.include Added: head/lib/csu/riscv/crt1.c == --- /dev/null 00:00:00 1970 (empty, because file is newly

svn commit: r292407 - in head/sys/riscv: . include

__uint64_t __uintptr_t; +typedef__uint32_t __uint_fast8_t; +typedef__uint32_t __uint_fast16_t; +typedef__uint32_t __uint_fast32_t; +typedef__uint64_t __uint_fast64_t; +typedef__uint8_t __uint_least8_t; +typedef__uint1

svn commit: r292691 - in head/libexec/rtld-elf: . riscv

@@ +/*- + * Copyright (c) 2015 Ruslan Bukin + * All rights reserved. + * + * This software was developed by SRI International and the University of + * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 + * ("CTSRD"), as part of the DARPA CRASH research programme. + * + * Thi

svn commit: r300614 - head/sys/riscv/riscv

Author: br Date: Tue May 24 13:59:13 2016 New Revision: 300614 URL: https://svnweb.freebsd.org/changeset/base/300614 Log: Store the original value of stack pointer to the exception frame (the value we had before supervisor exception occurred). This helps consumers (e.g. DTrace) to not procee

svn commit: r300617 - head/sys/conf

Author: br Date: Tue May 24 16:30:05 2016 New Revision: 300617 URL: https://svnweb.freebsd.org/changeset/base/300617 Log: Set dependencies for genassym.c. This fixes non-parallel build. Modified: head/sys/conf/Makefile.riscv Modified: head/sys/conf/Makefile.riscv ==

svn commit: r300618 - in head: cddl/contrib/opensolaris/lib/libdtrace/common cddl/contrib/opensolaris/lib/libdtrace/riscv cddl/lib cddl/lib/libdtrace cddl/usr.sbin sys/cddl/contrib/opensolaris/uts/...

+ * fields enclosed by brackets "[]" replaced with your own identifying + * information: Portions Copyright [] [name of copyright owner] + * + * CDDL HEADER END + */ +/* + * Copyright 2005 Sun Microsystems, Inc. All rights reserved. + * Use is subject to license terms. + * Copyright 201

svn commit: r300675 - head/contrib/elftoolchain/libdwarf

Author: br Date: Wed May 25 11:58:55 2016 New Revision: 300675 URL: https://svnweb.freebsd.org/changeset/base/300675 Log: Add relocation support for RISC-V. Reviewed by: emaste Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Differential Revision:https://reviews.freebsd.org/D65

svn commit: r300680 - in head: contrib/netbsd-tests/lib/libc/gen contrib/netbsd-tests/lib/libc/sys lib/libc/riscv lib/libc/riscv/sys

Author: br Date: Wed May 25 14:08:21 2016 New Revision: 300680 URL: https://svnweb.freebsd.org/changeset/base/300680 Log: Remove legacy brk and sbrk from RISC-V. Discussed with: andrew Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Deleted: head/lib/libc/riscv/sys/brk.S head/l

svn commit: r300689 - head/lib/libc/riscv/sys

Author: br Date: Wed May 25 16:38:10 2016 New Revision: 300689 URL: https://svnweb.freebsd.org/changeset/base/300689 Log: Do not generate code for sbrk syscall -- sbrk support was removed. Pointed out by: andrew Modified: head/lib/libc/riscv/sys/Makefile.inc Modified: head/lib/lib

svn commit: r300726 - head/sys/riscv/include

Author: br Date: Thu May 26 10:03:30 2016 New Revision: 300726 URL: https://svnweb.freebsd.org/changeset/base/300726 Log: Increase the size and alignment of the setjmp buffer. This is required for future CPU extentions. Reviewed by: brooks Sponsored by: DARPA, AFRL Sponsored by: HEIF

svn commit: r300859 - head/sys/cddl/dev/dtrace/riscv

Author: br Date: Fri May 27 17:58:10 2016 New Revision: 300859 URL: https://svnweb.freebsd.org/changeset/base/300859 Log: Correct the implementation of dtrace_interrupt_disable/enable. Pointed out by: andrew Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Modified: head/sys/cddl/

svn commit: r301120 - head/sys/riscv/conf

Author: br Date: Wed Jun 1 12:19:00 2016 New Revision: 301120 URL: https://svnweb.freebsd.org/changeset/base/301120 Log: * Enable KDTRACE options as we support DTrace now. * Add bpf device to kernel config. Modified: head/sys/riscv/conf/GENERIC Modified: head/sys/riscv/conf/GENERIC ==

svn commit: r301121 - head/sys/modules

Author: br Date: Wed Jun 1 13:43:43 2016 New Revision: 301121 URL: https://svnweb.freebsd.org/changeset/base/301121 Log: Don't build some modules on RISC-V. Submitted by: Yukishige Shibata Modified: head/sys/modules/Makefile Modified: head/sys/modules/Makefile

svn commit: r301123 - head/sys/dev/sym

Author: br Date: Wed Jun 1 14:03:13 2016 New Revision: 301123 URL: https://svnweb.freebsd.org/changeset/base/301123 Log: Add a riscv define. Submitted by: Yukishige Shibata Modified: head/sys/dev/sym/sym_hipd.c Modified: head/sys/dev/sym/sym_hipd.c

svn commit: r301124 - head/sys/conf

Author: br Date: Wed Jun 1 14:05:32 2016 New Revision: 301124 URL: https://svnweb.freebsd.org/changeset/base/301124 Log: Build riscv modules as PIC. Submitted by: Yukishige Shibata Modified: head/sys/conf/kmod.mk Modified: head/sys/conf/kmod.mk

svn commit: r301126 - in head/sys/riscv: conf riscv

riscv/riscv/elf_machdep.c == --- head/sys/riscv/riscv/elf_machdep.c Wed Jun 1 14:11:40 2016 (r301125) +++ head/sys/riscv/riscv/elf_machdep.c Wed Jun 1 14:12:31 2016 (r301126) @@ -1,6 +1,7 @@ /*- * Copyright 1996-1998 John D. Polstra. *

svn commit: r301205 - head/sys/riscv/riscv

== --- head/sys/riscv/riscv/elf_machdep.c Thu Jun 2 14:25:10 2016 (r301204) +++ head/sys/riscv/riscv/elf_machdep.c Thu Jun 2 15:14:40 2016 (r301205) @@ -1,7 +1,7 @@ /*- * Copyright 1996-1998 John D. Polstra. * Copyright (c) 2015 Ruslan Bukin - * Copyright (c) 2016

svn commit: r301621 - head/sys/riscv/include

Author: br Date: Wed Jun 8 13:57:18 2016 New Revision: 301621 URL: https://svnweb.freebsd.org/changeset/base/301621 Log: Remove duplicate define. Modified: head/sys/riscv/include/riscvreg.h Modified: head/sys/riscv/include/riscvreg.h =

svn commit: r297971 - head/lib/libthr/arch/riscv/include

Author: br Date: Thu Apr 14 15:31:05 2016 New Revision: 297971 URL: https://svnweb.freebsd.org/changeset/base/297971 Log: Unmagic the thread pointer offset. Modified: head/lib/libthr/arch/riscv/include/pthread_md.h Modified: head/lib/libthr/arch/riscv/include/pthread_md.h ===

svn commit: r298268 - head/sys/dev/spibus

Author: br Date: Tue Apr 19 14:18:12 2016 New Revision: 298268 URL: https://svnweb.freebsd.org/changeset/base/298268 Log: Add optional chip_select/deselect methods. This is required when we want to keep CS asserted for multiple transfers. Modified: head/sys/dev/spibus/spibus.c head/sys/de

svn commit: r298269 - head/sys/dev/xilinx

Apr 19 14:47:08 2016 (r298269) @@ -0,0 +1,252 @@ +/*- + * Copyright (c) 2016 Ruslan Bukin + * All rights reserved. + * + * Portions of this software were developed by SRI International and the + * University of Cambridge Computer Laboratory under DARPA/AFRL contract + * FA8750-10-C-0237

svn commit: r298273 - head/sys/dev/xilinx

Author: br Date: Tue Apr 19 15:36:18 2016 New Revision: 298273 URL: https://svnweb.freebsd.org/changeset/base/298273 Log: Assert CS for single transfers. Modified: head/sys/dev/xilinx/axi_quad_spi.c Modified: head/sys/dev/xilinx/axi_quad_spi.c

svn commit: r298274 - head/sys/dev/spibus

Author: br Date: Tue Apr 19 15:39:46 2016 New Revision: 298274 URL: https://svnweb.freebsd.org/changeset/base/298274 Log: Revert r298268 (Add optional chip_select/deselect methods). None of supported hardware do require that. Modified: head/sys/dev/spibus/spibus.c head/sys/dev/spibus/spib

Re: svn commit: r298268 - head/sys/dev/spibus

On Tue, Apr 19, 2016 at 08:41:39AM -0600, Ian Lepore wrote: > On Tue, 2016-04-19 at 14:18 +0000, Ruslan Bukin wrote: > > Author: br > > Date: Tue Apr 19 14:18:12 2016 > > New Revision: 298268 > > URL: https://svnweb.freebsd.org/changeset/base/298268 > > > &

Re: svn commit: r298274 - head/sys/dev/spibus

09:40:23AM -0700, Adrian Chadd wrote: > Hm, why'd you do this? did you get it reviewed first? > > I'm about to write a kernel bitbang SPI driver that supports arbitrary > GPIOs, and I was thinking of fleshing this out somewhat. > > > > -adrian > > >

svn commit: r298474 - head/sys/riscv/riscv

Author: br Date: Fri Apr 22 15:04:46 2016 New Revision: 298474 URL: https://svnweb.freebsd.org/changeset/base/298474 Log: Correct the event queue initialization. This fixes operation on Rocket Core. Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Modified: head/sys/riscv/riscv/locore.S

svn commit: r298476 - head/sys/riscv/htif

Author: br Date: Fri Apr 22 15:12:05 2016 New Revision: 298476 URL: https://svnweb.freebsd.org/changeset/base/298476 Log: Add memory barriers (fence instructions) so the data wrotten by hardware to physical address now can be read by VA. This fixes operation on Rocket Core (FPGA). Sp

svn commit: r298477 - in head/sys: conf riscv/riscv

Author: br Date: Fri Apr 22 16:15:58 2016 New Revision: 298477 URL: https://svnweb.freebsd.org/changeset/base/298477 Log: Clear the DDR memory. This should be done by bootloaders, but they have no such feature yet. This fixes operation on Rocket Core and lowRISC. Modified: head/sys/con

Re: svn commit: r298477 - in head/sys: conf riscv/riscv

On Fri, Apr 22, 2016 at 11:31:37PM +0200, Marko Zec wrote: > On Fri, 22 Apr 2016 16:15:59 + > Ruslan Bukin wrote: > > > Author: br > > Date: Fri Apr 22 16:15:58 2016 > > New Revision: 298477 > > URL: https://svnweb.freebsd.org/changeset/base/298477 > &g

svn commit: r298578 - in head/sys: conf riscv/riscv

Author: br Date: Mon Apr 25 13:20:57 2016 New Revision: 298578 URL: https://svnweb.freebsd.org/changeset/base/298578 Log: Revert r298477 ("Clear the DDR memory"). There is no need to clear all the DDR memory (we only need to clear BSS section). I was playing with non-default version of

svn commit: r298579 - head/sys/riscv/riscv

Author: br Date: Mon Apr 25 13:30:37 2016 New Revision: 298579 URL: https://svnweb.freebsd.org/changeset/base/298579 Log: Do not setup machine exception vector. Sounds strange, but both RocketCore and lowRISC do not operate if we set it. All the known implementations (Spike, QEMU, Ro

svn commit: r298580 - in head/sys/riscv: include riscv

Author: br Date: Mon Apr 25 14:47:51 2016 New Revision: 298580 URL: https://svnweb.freebsd.org/changeset/base/298580 Log: o Implement shared pagetables and switch from 4 to 3 levels page memory system. RISC-V ISA has only single page table base register for both kernel and user addresse

svn commit: r298627 - in head/sys: arm/allwinner arm/altera/socfpga arm/amlogic/aml8726 arm/annapurna/alpine arm/arm arm/at91 arm/broadcom/bcm2835 arm/cavium/cns11xx arm/freescale arm/freescale/imx...

Author: br Date: Tue Apr 26 11:53:37 2016 New Revision: 298627 URL: https://svnweb.freebsd.org/changeset/base/298627 Log: Move arm's devmap to some generic place, so it can be used by other architectures. Reviewed by: imp Differential Revision:https://reviews.freebsd.org/D6091

svn commit: r298631 - head/sys/kern

Author: br Date: Tue Apr 26 12:29:47 2016 New Revision: 298631 URL: https://svnweb.freebsd.org/changeset/base/298631 Log: Add support for RISC-V. Modified: head/sys/kern/subr_devmap.c Modified: head/sys/kern/subr_devmap.c ==

svn commit: r298632 - head/sys/dev/uart

Author: br Date: Tue Apr 26 12:31:23 2016 New Revision: 298632 URL: https://svnweb.freebsd.org/changeset/base/298632 Log: Do not include fdt.h on RISC-V. Modified: head/sys/dev/uart/uart_cpu_fdt.c Modified: head/sys/dev/uart/uart_cpu_fdt.c

svn commit: r298633 - head/sys/riscv/riscv

Author: br Date: Tue Apr 26 12:33:25 2016 New Revision: 298633 URL: https://svnweb.freebsd.org/changeset/base/298633 Log: Add the implementation of OF_decode_addr(). Added: head/sys/riscv/riscv/ofw_machdep.c (contents, props changed) Added: head/sys/riscv/riscv/ofw_machdep.c ==

svn commit: r298635 - head/sys/riscv/riscv

/bus_machdep.c Tue Apr 26 12:45:01 2016 (r298635) @@ -1,4 +1,5 @@ /*- + * Copyright (c) 2014 Andrew Turner * Copyright (c) 2015 Ruslan Bukin * All rights reserved. * @@ -42,27 +43,108 @@ __FBSDID("$FreeBSD$"); #include +uint8_t generic_bs_r_1(void *, bus_spac

svn commit: r298636 - in head/sys/riscv: include riscv

Author: br Date: Tue Apr 26 12:56:44 2016 New Revision: 298636 URL: https://svnweb.freebsd.org/changeset/base/298636 Log: Add the non-standard "IO interrupt" vector used by lowRISC. For now they provide UART irq only. Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Modified: head/sys/r

svn commit: r298638 - in head/sys: boot/fdt/dts/riscv conf riscv/conf

newly added) +++ head/sys/boot/fdt/dts/riscv/lowrisc.dts Tue Apr 26 13:22:08 2016 (r298638) @@ -0,0 +1,108 @@ +/*- + * Copyright (c) 2016 Ruslan Bukin + * All rights reserved. + * + * Portions of this software were developed by SRI International and the + * University of Cambridge

svn commit: r298641 - in head/sys/riscv: include riscv

Author: br Date: Tue Apr 26 14:38:18 2016 New Revision: 298641 URL: https://svnweb.freebsd.org/changeset/base/298641 Log: Rework the list of all pmaps: embed the list link into pmap. Modified: head/sys/riscv/include/pmap.h head/sys/riscv/riscv/pmap.c Modified: head/sys/riscv/include/pmap.h

Re: svn commit: r298580 - in head/sys/riscv: include riscv

On Mon, Apr 25, 2016 at 06:50:44PM +0300, Konstantin Belousov wrote: > On Mon, Apr 25, 2016 at 02:47:51PM +0000, Ruslan Bukin wrote: > > +/* An entry in the list of all pmaps */ > > +struct pmap_list_entry { > > + SLIST_ENTRY(pmap_list_entry) pmap_link; >

svn commit: r298651 - head/sys/dev/spibus

Author: br Date: Tue Apr 26 16:02:13 2016 New Revision: 298651 URL: https://svnweb.freebsd.org/changeset/base/298651 Log: Fix the parameter type according to method declaration. This fixes compilation on riscv with GCC 5.2.0 Modified: head/sys/dev/spibus/spibus.c Modified: head/sys/dev/spi

svn commit: r299118 - in head/sys: cddl/contrib/opensolaris/uts/common/sys cddl/dev/dtrace/mips cddl/dev/fbt/mips conf mips/mips

right owner] + * + * CDDL HEADER END + * + * Portions Copyright 2006-2008 John Birrell j...@freebsd.org + * Portions Copyright 2013 Justin Hibbits jhibb...@freebsd.org + * Portions Copyright 2013 Howard Su howar...@freebsd.org + * Portions Copyright 2015-2016 Ruslan Bukin + * + * $FreeBSD$ + */ +

svn commit: r284077 - head/sys/arm/freescale/imx

Author: br Date: Sat Jun 6 14:26:40 2015 New Revision: 284077 URL: https://svnweb.freebsd.org/changeset/base/284077 Log: Include a header required for vtophys(). Modified: head/sys/arm/freescale/imx/imx6_sdma.c Modified: head/sys/arm/freescale/imx/imx6_sdma.c ===

Re: svn commit: r284153 - head/sys/kern

For some reason it hangs for me after 'random' lines on arm64 FreeBSD clang version 3.6.1 (tags/RELEASE_361/final 237755) 20150525 CPU: ARM Cortex-A57 r1p0 IMPLEMENT ME: dtrace_toxic_ranges random: entropy device infrastructure driver random: selecting highest priority adaptor On Mon, Jun 08, 20

Re: svn commit: r284153 - head/sys/kern

On Mon, Jun 08, 2015 at 02:04:45PM -0400, John Baldwin wrote: > On Monday, June 08, 2015 03:46:29 PM Ruslan Bukin wrote: > > For some reason it hangs for me after 'random' lines on arm64 > > Are you using dtrace? It looks like sdt was using the public symbol before >

svn commit: r284213 - head/sys/cddl/dev/dtrace/arm

Author: br Date: Wed Jun 10 09:59:26 2015 New Revision: 284213 URL: https://svnweb.freebsd.org/changeset/base/284213 Log: Don't re-define LOCORE when dtrace is built-in to the kernel. Modified: head/sys/cddl/dev/dtrace/arm/dtrace_asm.S Modified: head/sys/cddl/dev/dtrace/arm/dtrace_asm.S

svn commit: r284218 - in head: lib/libpmc sys/dev/hwpmc sys/sys

Author: br Date: Wed Jun 10 12:42:30 2015 New Revision: 284218 URL: https://svnweb.freebsd.org/changeset/base/284218 Log: o Rework ARMv7 events list using aliases - same way as we have for arm64. o Extend it with Cortex A9-specific events. Modified: head/lib/libpmc/libpmc.c head/sys/dev/h

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