svn commit: r361532 - in head/sys: dev/acpica dev/pci x86/iommu

Author: br Date: Tue May 26 16:40:40 2020 New Revision: 361532 URL: https://svnweb.freebsd.org/changeset/base/361532 Log: Rename dmar_get_dma_tag() to acpi_iommu_get_dma_tag(). This is needed for a new IOMMU controller support. Reviewed by: kib Differential Revision:https://rev

svn commit: r361533 - in head/sys: cddl/dev/dtrace/riscv riscv/riscv

Author: br Date: Tue May 26 16:44:05 2020 New Revision: 361533 URL: https://svnweb.freebsd.org/changeset/base/361533 Log: Fix entering KDB with dtrace-enabled kernel. Reviewed by: markj, jhb Differential Revision:https://reviews.freebsd.org/D24018 Modified: head/sys/cddl/dev/d

svn commit: r361968 - in head/sys: arm64/coresight conf

added) +++ head/sys/arm64/coresight/coresight_cmd.cTue Jun 9 15:56:41 2020 (r361968, copy of r361967, head/sys/arm64/coresight/coresight-cmd.c) @@ -0,0 +1,156 @@ +/*- + * Copyright (c) 2018 Ruslan Bukin + * All rights reserved. + * + * This software was developed by SRI International and

svn commit: r361969 - head/sys/arm64/coresight

Author: br Date: Tue Jun 9 16:06:10 2020 New Revision: 361969 URL: https://svnweb.freebsd.org/changeset/base/361969 Log: Fix style: wrap long lines. Sponsored by: DARPA, AFRL Modified: head/sys/arm64/coresight/coresight.c Modified: head/sys/arm64/coresight/coresight.c =

svn commit: r361974 - in head/sys: arm64/coresight conf

== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/arm64/coresight/coresight_etm4x_acpi.c Tue Jun 9 16:43:16 2020(r361974) @@ -0,0 +1,79 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2020 Ruslan Bukin

svn commit: r361976 - head/sys/dev/acpica

Author: br Date: Tue Jun 9 17:07:42 2020 New Revision: 361976 URL: https://svnweb.freebsd.org/changeset/base/361976 Log: Similar to UART on ThunderX2, the ARM Coresight (ETM component) set ResourceProducer on memory resources: ignore it. Tested on ARM N1SDP board. Sponsored by: DARP

svn commit: r362011 - in head/sys: arm64/coresight conf

(r362011) @@ -1,5 +1,5 @@ /*- - * Copyright (c) 2018 Ruslan Bukin + * Copyright (c) 2018-2020 Ruslan Bukin * All rights reserved. * * This software was developed by BAE Systems, the University of Cambridge @@ -43,9 +43,6 @@ __FBSDID("$FreeBSD$"); #include #include

svn commit: r362012 - head/sys/dev/acpica

Author: br Date: Wed Jun 10 14:39:54 2020 New Revision: 362012 URL: https://svnweb.freebsd.org/changeset/base/362012 Log: All the ARM Coresight interconnect devices set ResourceProducer on memory resources, ignore it. The devices found in the ARM Neoverse N1 System Development Platform

svn commit: r362077 - in head/sys: arm64/coresight conf

/coresight_dynamic_replicator.c) @@ -0,0 +1,172 @@ +/*- + * Copyright (c) 2018 Ruslan Bukin + * All rights reserved. + * + * This software was developed by BAE Systems, the University of Cambridge + * Computer Laboratory, and Memorial University under DARPA/AFRL contract + * FA8650-15-C-7558 ("CADETS&

svn commit: r362099 - in head/sys: arm64/coresight conf

acpi.c Fri Jun 12 13:59:58 2020(r362099) @@ -0,0 +1,79 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2020 Ruslan Bukin + * + * This software was developed by SRI International and the University of + * Cambridge Computer Laboratory (Department of Computer Sc

svn commit: r362109 - in head/sys: arm64/coresight conf

dded: head/sys/arm64/coresight/coresight_replicator.h == --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/arm64/coresight/coresight_replicator.h Fri Jun 12 17:31:38 2020(r362109) @@ -0,0 +1,46 @@ +/*- + * Copyright (c) 2020 Ruslan Bukin + * All

svn commit: r324598 - head/sys/dev/hwpmc

Author: br Date: Fri Oct 13 15:02:29 2017 New Revision: 324598 URL: https://svnweb.freebsd.org/changeset/base/324598 Log: o Support for Kabylake CPU PMCs (fall down to PMC_CPU_INTEL_SKYLAKE). o Fix bugs in events descriptions for Skylake, Skylake Xeon and Haswell. Reviewed by: kib Spon

svn commit: r324959 - in head: lib lib/libpmcstat share/mk usr.sbin/pmcstat

Author: br Date: Tue Oct 24 16:28:00 2017 New Revision: 324959 URL: https://svnweb.freebsd.org/changeset/base/324959 Log: Extract a set of pmcstat functions and interfaces to the new internal library -- libpmcstat. This includes PMC logging module, symbols lookup functions, ELF parsing,

svn commit: r325747 - head/sys/x86/include

Author: br Date: Sun Nov 12 23:13:04 2017 New Revision: 325747 URL: https://svnweb.freebsd.org/changeset/base/325747 Log: Add Intel Processor Trace (PT) MSRs. Sponsored by: DARPA, AFRL Modified: head/sys/x86/include/specialreg.h Modified: head/sys/x86/include/specialreg.h ==

svn commit: r325952 - head/sys/x86/include

Author: br Date: Fri Nov 17 17:54:10 2017 New Revision: 325952 URL: https://svnweb.freebsd.org/changeset/base/325952 Log: Add Intel Processor Trace registers for: - CPUID - Table of Physical Addresses (ToPA). Sponsored by: DARPA, AFRL Modified: head/sys/x86/include/specialreg.h Modi

svn commit: r326092 - head/sys/riscv/riscv

Author: br Date: Wed Nov 22 14:10:58 2017 New Revision: 326092 URL: https://svnweb.freebsd.org/changeset/base/326092 Log: o Invalidate the correct page in pmap_protect(). With this bug fix we don't need to invalidate all the entries. o Remove a call to pmap_invalidate_all(). This was never

svn commit: r357653 - in head/sys/dev: xdma xilinx

Author: br Date: Fri Feb 7 14:36:28 2020 New Revision: 357653 URL: https://svnweb.freebsd.org/changeset/base/357653 Log: Fix xae(4) driver attachement on the Government Furnished Equipment (GFE) riscv cores. GFE cores come with standard DTS file that lacks standard 'dmas =' property, w

svn commit: r357682 - head/sys/dev/xdma

Author: br Date: Sat Feb 8 21:02:20 2020 New Revision: 357682 URL: https://svnweb.freebsd.org/changeset/base/357682 Log: Fix a KASSERT since chained mbufs are accepted by the xdma bounce buffer loader. m_copydata() will copy entire chain to a single buffer. Sponsored by: DARPA, AFRL Mod

svn commit: r357686 - in head/sys: dev/altera/atse dev/flash dev/xdma dev/xilinx mips/ingenic

Author: br Date: Sat Feb 8 23:07:29 2020 New Revision: 357686 URL: https://svnweb.freebsd.org/changeset/base/357686 Log: Enter the network epoch in the xdma interrupt handler if required by a peripheral device driver. Sponsored by: DARPA, AFRL Modified: head/sys/dev/altera/atse/if_ats

svn commit: r357762 - in head/sys: arm64/conf conf dev/pci dev/pci/controller

:09 2020 (r357762) @@ -0,0 +1,350 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019 Andrew Turner + * Copyright (c) 2019 Ruslan Bukin + * + * This software was developed by SRI International and the University of + * Cambridge Computer Laboratory (Department of

svn commit: r335793 - head/sys/riscv/conf

Author: br Date: Fri Jun 29 10:55:42 2018 New Revision: 335793 URL: https://svnweb.freebsd.org/changeset/base/335793 Log: Include UART driver since it is now provided in QEMU. Sponsored by: DARPA, AFRL Modified: head/sys/riscv/conf/GENERIC Modified: head/sys/riscv/conf/GENERIC =

svn commit: r335887 - head/share/mk

Author: br Date: Tue Jul 3 10:51:59 2018 New Revision: 335887 URL: https://svnweb.freebsd.org/changeset/base/335887 Log: Add GCC 8.1.0 compiler warning flags. Sponsored by: DARPA, AFRL Modified: head/share/mk/bsd.sys.mk Modified: head/share/mk/bsd.sys.mk ===

svn commit: r335888 - in head: contrib/blacklist/bin lib/libpjdlog sbin/hastd

Author: br Date: Tue Jul 3 13:53:54 2018 New Revision: 335888 URL: https://svnweb.freebsd.org/changeset/base/335888 Log: o Ensure va_list is declared by including stdarg.h. o Also move printf.h to go after it since it does require declaration of va_list. This fixes build with latest

Re: svn commit: r335887 - head/share/mk

On Tue, Jul 03, 2018 at 10:56:48AM +, Mark Linimon wrote: > On Tue, Jul 03, 2018 at 10:51:59AM +0000, Ruslan Bukin wrote: > > Add GCC 8.1.0 compiler warning flags. > > I'm sorry, but that is a "what" not a "why". > > As someone who

svn commit: r335889 - head/usr.bin/top

Author: br Date: Tue Jul 3 14:32:15 2018 New Revision: 335889 URL: https://svnweb.freebsd.org/changeset/base/335889 Log: Fix build: utf8strvisx() does signed data comparisons, but 'char' type is unsigned in riscv GCC, so use guaranted signed char type. Sponsored by: DARPA, AFRL Modified

Re: svn commit: r335888 - in head: contrib/blacklist/bin lib/libpjdlog sbin/hastd

On Tue, Jul 03, 2018 at 07:57:00AM -0700, John Baldwin wrote: > On 7/3/18 6:53 AM, Ruslan Bukin wrote: > > Author: br > > Date: Tue Jul 3 13:53:54 2018 > > New Revision: 335888 > > URL: https://svnweb.freebsd.org/changeset/base/335888 > > > > Log: > >

svn commit: r335893 - in head: contrib/blacklist/bin lib/libpjdlog sbin/hastd

Author: br Date: Tue Jul 3 15:48:34 2018 New Revision: 335893 URL: https://svnweb.freebsd.org/changeset/base/335893 Log: Revert 335888 ("Ensure va_list is declared by including stdarg.h.") The issue was caused by header pollution brought by GCC 8.1. We now have to remove include-fixed

Re: svn commit: r335888 - in head: contrib/blacklist/bin lib/libpjdlog sbin/hastd

On Tue, Jul 03, 2018 at 08:21:58AM -0700, John Baldwin wrote: > On 7/3/18 8:02 AM, Ruslan Bukin wrote: > > On Tue, Jul 03, 2018 at 07:57:00AM -0700, John Baldwin wrote: > >> On 7/3/18 6:53 AM, Ruslan Bukin wrote: > >>> Author: br > >>> Date: Tue Jul

svn commit: r336455 - head/share/mk

Author: br Date: Wed Jul 18 11:31:15 2018 New Revision: 336455 URL: https://svnweb.freebsd.org/changeset/base/336455 Log: Add a GCC 8.1 warning flag. This is required to build ATF. Sponsored by: DARPA, AFRL Modified: head/share/mk/bsd.sys.mk Modified: head/share/mk/bsd.sys.mk =

svn commit: r336480 - head/share/mk

Author: br Date: Thu Jul 19 12:56:54 2018 New Revision: 336480 URL: https://svnweb.freebsd.org/changeset/base/336480 Log: Add a GCC 7.1.0 no-error warning flag. This is required to build libdevdctl. Note this flag is not required for GCC 8.1.0. Sponsored by: DARPA, AFRL Modified:

svn commit: r336482 - head/share/mk

Author: br Date: Thu Jul 19 13:02:29 2018 New Revision: 336482 URL: https://svnweb.freebsd.org/changeset/base/336482 Log: PROFILE, TESTS and CXX build options are no longer broken for RISC-V. Sponsored by: DARPA, AFRL Modified: head/share/mk/src.opts.mk Modified: head/share/mk/src.opts.

svn commit: r336633 - in head: lib/libc/riscv/gen sys/riscv/include

Author: br Date: Mon Jul 23 09:54:28 2018 New Revision: 336633 URL: https://svnweb.freebsd.org/changeset/base/336633 Log: Fix setjmp for RISC-V: o The correct value for _JB_SIGMASK is 27. o The storage size for double-precision floating point register is 8 bytes. Submitted by: "Jame

svn commit: r336712 - head/sys/riscv/riscv

Author: br Date: Wed Jul 25 15:44:49 2018 New Revision: 336712 URL: https://svnweb.freebsd.org/changeset/base/336712 Log: Remove unused string. Reported by: markj@ Sponsored by: DARPA, AFRL Modified: head/sys/riscv/riscv/swtch.S Modified: head/sys/riscv/riscv/swtch.S

svn commit: r336716 - in head: share/mk stand sys/conf

Author: br Date: Wed Jul 25 16:07:35 2018 New Revision: 336716 URL: https://svnweb.freebsd.org/changeset/base/336716 Log: Disable 'C'-compressed ISA extension. It works excellent, but KDB disassembler and DTrace FBT provider for RISC-V do lack support for it. They currently handle 4-byte

svn commit: r336738 - head/share/mk

Author: br Date: Thu Jul 26 14:15:04 2018 New Revision: 336738 URL: https://svnweb.freebsd.org/changeset/base/336738 Log: Disable OFED for RISC-V: it does not build. Sponsored by: DARPA, AFRL Modified: head/share/mk/src.opts.mk Modified: head/share/mk/src.opts.mk ===

svn commit: r336766 - head/sys/riscv/include

2015-2016 Ruslan Bukin + * Copyright (c) 2015-2018 Ruslan Bukin * All rights reserved. * * Portions of this software were developed by SRI International and the @@ -41,7 +41,7 @@ #include #defineTRAPF_PC(tfp) ((tfp)->tf_ra) -#defineTRAPF_USERMODE(tfp) (((

svn commit: r336900 - head/sys/riscv/conf

Author: br Date: Mon Jul 30 12:22:49 2018 New Revision: 336900 URL: https://svnweb.freebsd.org/changeset/base/336900 Log: Disable VIMAGE on RISC-V. Similar to r326179 ("Temporarily disable VIMAGE on arm64") creation of if_lagg or epair on RISC-V results a kernel panic. Sponsored by:

svn commit: r337125 - head/sys/riscv/riscv

Author: br Date: Thu Aug 2 12:08:52 2018 New Revision: 337125 URL: https://svnweb.freebsd.org/changeset/base/337125 Log: o Correctly set user tls base: consider TP_OFFSET. o Ensure tp (thread pointer) saved before copying the pcb. Sponsored by: DARPA, AFRL Modified: head/sys/riscv/ris

svn commit: r337126 - head/sys/riscv/riscv

Author: br Date: Thu Aug 2 12:12:13 2018 New Revision: 337126 URL: https://svnweb.freebsd.org/changeset/base/337126 Log: o Don't overwrite tp in fork_trampoline(). o Save and restore tp in cpu_switch(). o Restore tp in cpu_throw(). o Save tp in savectx(). This makes libthr tests happ

svn commit: r337127 - head/sys/riscv/riscv

Author: br Date: Thu Aug 2 12:13:52 2018 New Revision: 337127 URL: https://svnweb.freebsd.org/changeset/base/337127 Log: Don't overwrite tp in set_mcontext(). This makes libthr/swapcontext_test:swapcontext1 happy. Sponsored by: DARPA, AFRL Modified: head/sys/riscv/riscv/machdep.c

svn commit: r337128 - head/libexec/rtld-elf/riscv

@@ /*- - * Copyright (c) 2015 Ruslan Bukin + * Copyright (c) 2015-2018 Ruslan Bukin * All rights reserved. * * This software was developed by SRI International and the University of @@ -64,7 +64,7 @@ END(.rtld_start) */ ENTRY(_rtld_bind_start) /* Save the arguments and ra */ - addisp, sp

svn commit: r337129 - head/lib/libthread_db/arch/riscv

Author: br Date: Thu Aug 2 12:24:34 2018 New Revision: 337129 URL: https://svnweb.freebsd.org/changeset/base/337129 Log: Implement pt_fpreg_to_ucontext(), pt_ucontext_to_fpreg(). Sponsored by: DARPA, AFRL Modified: head/lib/libthread_db/arch/riscv/libpthread_md.c Modified: head/lib/lib

svn commit: r337237 - head/tests/sys/geom/class/nop

Author: br Date: Fri Aug 3 12:16:02 2018 New Revision: 337237 URL: https://svnweb.freebsd.org/changeset/base/337237 Log: Increase timeout for nop_test:stripesize. It takes 49s to complete this test in QEMU/RISC-V. Sponsored by: DARPA, AFRL Modified: head/tests/sys/geom/class/nop/no

svn commit: r337238 - head/contrib/netbsd-tests/lib/libc/sys

Author: br Date: Fri Aug 3 12:47:54 2018 New Revision: 337238 URL: https://svnweb.freebsd.org/changeset/base/337238 Log: Replace __riscv__ with __riscv. __riscv__ is not pre-defined anymore by latest version of GNU compiler. Sponsored by: DARPA, AFRL Modified: head/contrib/netbsd-t

svn commit: r337264 - head/lib/libc/sys

Author: br Date: Fri Aug 3 16:05:03 2018 New Revision: 337264 URL: https://svnweb.freebsd.org/changeset/base/337264 Log: MAXLOGNAME changed to 33 in r243023. Update man pages. Sponsored by: DARPA, AFRL Modified: head/lib/libc/sys/getlogin.2 head/lib/libc/sys/getloginclass.2 Modifie

svn commit: r337266 - head/sys/riscv/riscv

@@ /*- - * Copyright (c) 2015 Ruslan Bukin + * Copyright (c) 2015-2018 Ruslan Bukin * All rights reserved. * * Portions of this software were developed by SRI International and the @@ -133,5 +133,8 @@ ENTRY(copyinstr) sd a5, 0(a3) /* done = count */ 4: mv a0, x0

svn commit: r337381 - head/contrib/netbsd-tests/lib/libpthread

Author: br Date: Mon Aug 6 15:55:58 2018 New Revision: 337381 URL: https://svnweb.freebsd.org/changeset/base/337381 Log: Increase timeout for timedmutex_test:mutex2, timedmutex_test:mutex3 tests. Default value is 300. It takes ~310s to complete each of these tests in QEMU/RISC-V.

svn commit: r337459 - in head/sys/riscv: include riscv

Author: br Date: Wed Aug 8 16:08:38 2018 New Revision: 337459 URL: https://svnweb.freebsd.org/changeset/base/337459 Log: Implement uma_small_alloc(), uma_small_free(). Reviewed by: markj Obtained from:arm64 Sponsored by: DARPA, AFRL Differential Revision:https://revi

svn commit: r337712 - head/sys/riscv/include

Author: br Date: Mon Aug 13 16:07:18 2018 New Revision: 337712 URL: https://svnweb.freebsd.org/changeset/base/337712 Log: Add RISC-V instructions encoding. This is the output of $ cat opcodes opcodes-rvc-pseudo opcodes-rvc opcodes-custom | ./parse-opcodes -c It is confirmed by

svn commit: r337763 - head/sys/riscv/riscv

16:03:03 2018 (r337763) @@ -1,5 +1,5 @@ /*- - * Copyright (c) 2016 Ruslan Bukin + * Copyright (c) 2016-2018 Ruslan Bukin * All rights reserved. * * Portions of this software were developed by SRI International and the @@ -41,232 +41,26 @@ __FBSDID("$FreeBSD$"); #include

svn commit: r345581 - head/sys/riscv/riscv

Author: br Date: Wed Mar 27 16:26:03 2019 New Revision: 345581 URL: https://svnweb.freebsd.org/changeset/base/345581 Log: Grab timer frequency from FDT. RISC-V timer has no dedicated DTS node and we have to get timer frequency from cpus node. Tested on Government Furnished Equipment

svn commit: r345796 - head/sys/riscv/riscv

Author: br Date: Tue Apr 2 12:02:35 2019 New Revision: 345796 URL: https://svnweb.freebsd.org/changeset/base/345796 Log: o Grab the number of devices supported by PLIC from FDT. o Fix bug in PLIC_ENABLE macro when irq >= 32. Tested on the real hardware, which is HiFive Unleashed board.

Re: svn commit: r346250 - in head: share/man/man4 share/man/man9 sys/dev/random sys/kern sys/libkern sys/sys

Hi I just got this: UART 16550 configured with options: baud = 115200 | freq = 5000 bbl loader r vv rrr

svn commit: r346633 - head/sys/riscv/riscv

Author: br Date: Wed Apr 24 13:41:46 2019 New Revision: 346633 URL: https://svnweb.freebsd.org/changeset/base/346633 Log: Implement pic_pre_ithread(), pic_post_ithread(). Reviewed by: markj Sponsored by: DARPA, AFRL Differential Revision:https://reviews.freebsd.org/D19819 Modi

svn commit: r346634 - head/sys/dev/cadence

Author: br Date: Wed Apr 24 13:44:30 2019 New Revision: 346634 URL: https://svnweb.freebsd.org/changeset/base/346634 Log: Add support for Cadence network controller found in HiFive Unleashed board. Reviewed by: markj Sponsored by: DARPA, AFRL Differential Revision:https://revie

svn commit: r346896 - in head/sys/dev: altera/atse altera/softdma xdma

Author: br Date: Mon Apr 29 16:27:15 2019 New Revision: 346896 URL: https://svnweb.freebsd.org/changeset/base/346896 Log: o Rewrite softdma_process_tx() of Altera SoftDMA engine driver so it does not require a bounce buffer. The only need for this was to align the buffer address. Impleme

svn commit: r346994 - head/sys/riscv/riscv

Author: br Date: Wed May 1 15:03:12 2019 New Revision: 346994 URL: https://svnweb.freebsd.org/changeset/base/346994 Log: Deactivate IRQ resource by calling to intr_deactivate_irq(). This is the part of INTRNG support that was missed. Sponsored by: DARPA, AFRL Modified: head/sys/riscv/

svn commit: r347225 - in head/sys: conf riscv/include riscv/riscv

Author: br Date: Tue May 7 13:41:43 2019 New Revision: 347225 URL: https://svnweb.freebsd.org/changeset/base/347225 Log: Provide a template for busdma code for RISC-V. RISC-V ISA specifies no cache management instructions so leave cache operations in cpufunc.h as no-op for now. Note

svn commit: r347226 - head/sys/riscv/riscv

Author: br Date: Tue May 7 14:32:17 2019 New Revision: 347226 URL: https://svnweb.freebsd.org/changeset/base/347226 Log: Disable interrupts first and then set spinlock_count to 1. Otherwise interrupt can be generated just after setting spinlock_count and before disabling interrupts. Sp

svn commit: r347337 - head/sys/dev/xdma

-- head/sys/dev/xdma/xdma.cWed May 8 15:20:16 2019(r347336) +++ head/sys/dev/xdma/xdma.cWed May 8 15:22:27 2019(r347337) @@ -1,7 +1,8 @@ /*- - * Copyright (c) 2016-2018 Ruslan Bukin - * All rights reserved. + * SPDX-License-Identifier: BSD-2-Clause * + * Copyright (c) 2

svn commit: r347344 - head/sys/dev/xilinx

file is newly added) +++ head/sys/dev/xilinx/axidma.cWed May 8 15:43:17 2019 (r347344) @@ -0,0 +1,648 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019 Ruslan Bukin + * + * This software was developed by SRI International and the University of + * Cambridge

svn commit: r347342 - in head/sys/dev: mii xilinx

Ruslan Bukin + * + * This software was developed by SRI International and the University of + * Cambridge Computer Laboratory (Department of Computer Science and + * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the + * DARPA SSITH research programme. + * + * Redistri

svn commit: r347351 - in head/sys: conf riscv/conf

Author: br Date: Wed May 8 16:06:54 2019 New Revision: 347351 URL: https://svnweb.freebsd.org/changeset/base/347351 Log: Connect Xilinx AXI drivers and Cadence Ethernet MAC to the RISC-V build. Sponsored by: DARPA, AFRL Modified: head/sys/conf/files.riscv head/sys/riscv/conf/GENERIC

svn commit: r347427 - head/sys/riscv/riscv

Author: br Date: Fri May 10 11:21:57 2019 New Revision: 347427 URL: https://svnweb.freebsd.org/changeset/base/347427 Log: RISC-V ISA does not specify how to manage physical memory attributes (PMA). So do nothing in pmap_page_set_memattr() and don't panic. Reviewed by: markj Sponsored b

svn commit: r347514 - in head/sys/riscv: include riscv

Author: br Date: Sun May 12 16:17:05 2019 New Revision: 347514 URL: https://svnweb.freebsd.org/changeset/base/347514 Log: Add support for HiFive Unleashed -- the board with a multi-core RISC-V SoC from SiFive, Inc. The first core on this SoC (hart 0) is a 64-bit microcontroller. o Pi

svn commit: r316728 - head/sys/riscv/riscv

Author: br Date: Wed Apr 12 10:34:50 2017 New Revision: 316728 URL: https://svnweb.freebsd.org/changeset/base/316728 Log: Provide a NULL pointer to device tree blob so GENERIC kernel can be compiled. We will need to get pointer to DTB from hardware, so mark as TODO. Sponsored by: DARPA,

svn commit: r316729 - head/sys/conf

Author: br Date: Wed Apr 12 10:40:30 2017 New Revision: 316729 URL: https://svnweb.freebsd.org/changeset/base/316729 Log: Disable fformat-extensions for RISC-V target as GCC 6.1 external compiler has no support for that. Sponsored by: DARPA, AFRL Differential Revision:https://re

svn commit: r316730 - head

Author: br Date: Wed Apr 12 10:45:19 2017 New Revision: 316730 URL: https://svnweb.freebsd.org/changeset/base/316730 Log: Include RISC-V target to universe build. Check if RISC-V external toolchain package is installed, otherwise skip build. Reviewed by: emaste Sponsored by: DARPA

svn commit: r317095 - in head/sys: boot/fdt/dts/mips mips/beri mips/conf

0x0 0x7f806000 0x0 0x10 - 0x0 0x7f806080 0x0 0x10 - 0x0 0x7f806100 0x0 0x10>; - interrupts = <0 1 2 3 4>; - hard-interrupt-sources = <64>; - soft-interrupt-sources

Re: svn commit: r316978 - in head: contrib/zstd etc/mtree lib lib/libzstd share/mk usr.bin usr.bin/zstd

This break RISC-V world build: /home/br/obj//riscv.riscv64/usr/home/br/dev/freebsd-head/tmp/usr/lib/libprivatezstd.so: undefined reference to `__bswap si2' /home/br/obj//riscv.riscv64/usr/home/br/dev/freebsd-head/tmp/usr/lib/libprivatezstd.so: undefined reference to `__bswap di2' Here is patch t

svn commit: r317144 - head/contrib/zstd/lib/common

Author: br Date: Wed Apr 19 15:24:33 2017 New Revision: 317144 URL: https://svnweb.freebsd.org/changeset/base/317144 Log: Don't use __builtin_bswap for RISC-V due to undefined reference in compiler. This unbreaks RISC-V world build. Sponsored by: DARPA, AFRL Modified: head/contrib

Re: svn commit: r316978 - in head: contrib/zstd etc/mtree lib lib/libzstd share/mk usr.bin usr.bin/zstd

On Wed, Apr 19, 2017 at 04:53:25PM +0200, Baptiste Daroussin wrote: > On Wed, Apr 19, 2017 at 02:21:06PM +0000, Ruslan Bukin wrote: > > This break RISC-V world build: > > /home/br/obj//riscv.riscv64/usr/home/br/dev/freebsd-head/tmp/usr/lib/libprivatezstd.so: > > undefined

svn commit: r317151 - in head/sys/riscv: include riscv

Author: br Date: Wed Apr 19 17:06:32 2017 New Revision: 317151 URL: https://svnweb.freebsd.org/changeset/base/317151 Log: Follow r317061 "Remove struct vmmeter from struct pcpu" with MD changes for RISC-V. This unbreaks RISC-V build. Sponsored by: DARPA, AFRL Modified: head/sys/ri

svn commit: r317530 - in head/lib/libc/riscv: . sys

Author: br Date: Thu Apr 27 22:40:39 2017 New Revision: 317530 URL: https://svnweb.freebsd.org/changeset/base/317530 Log: Use unconditional jr (jump register) so cerror relocation offset fits. This fixes libc build on riscv64sf. Reviewed by: jhb Sponsored by: DARPA, AFRL Modified:

svn commit: r337767 - head/sys/riscv/include

Author: br Date: Tue Aug 14 16:22:14 2018 New Revision: 337767 URL: https://svnweb.freebsd.org/changeset/base/337767 Log: Remove unused code. Sponsored by: DARPA, AFRL Modified: head/sys/riscv/include/riscvreg.h Modified: head/sys/riscv/include/riscvreg.h ===

svn commit: r337769 - head/sys/mips/malta

Author: br Date: Tue Aug 14 16:26:44 2018 New Revision: 337769 URL: https://svnweb.freebsd.org/changeset/base/337769 Log: Avoid repeated address calculation for malta_ap_boot. Submitted by: "James Clarke" Reviewed by: br, arichardson Sponsored by: DARPA, AFRL Differential Revision:

svn commit: r337771 - head/sys/mips/malta

Author: br Date: Tue Aug 14 16:29:10 2018 New Revision: 337771 URL: https://svnweb.freebsd.org/changeset/base/337771 Log: Query MVPConf0.PVPE for number of CPUs. Rather than hard-coding the number of CPUs to 2, look up the PVPE field in MVPConf0, as the valid VPE numbers are from 0 to PVP

svn commit: r338409 - head/sys/riscv/riscv

Author: br Date: Fri Aug 31 16:15:46 2018 New Revision: 338409 URL: https://svnweb.freebsd.org/changeset/base/338409 Log: Fix an integer overflow while setting the kernel address (MODINFO_ADDR). This eliminates build warning and makes kldstat happy. Approved by: re (marius) Modified:

svn commit: r338444 - in head/sys: cddl/contrib/opensolaris/uts/common/sys cddl/dev/dtrace/riscv cddl/dev/fbt/riscv riscv/conf riscv/include

Copyright 2016 Ruslan Bukin + * Portions Copyright 2016-2018 Ruslan Bukin * * $FreeBSD$ * @@ -42,8 +42,8 @@ __FBSDID("$FreeBSD$"); #include #include #include +#include #include -#include #include #include #include @@ -77,7 +77,6 @@ dtrace_invop(uintptr_t addr, str

svn commit: r338445 - in head: share/mk stand sys/conf

Author: br Date: Mon Sep 3 14:43:16 2018 New Revision: 338445 URL: https://svnweb.freebsd.org/changeset/base/338445 Log: Enable 'C'-compressed ISA extension. This was disabled recently due to lack of support in KDB disassembler and DTrace FBT provider. Support for 'C'-extension to both o

svn commit: r338466 - head/sys/riscv/riscv

Author: br Date: Wed Sep 5 09:53:55 2018 New Revision: 338466 URL: https://svnweb.freebsd.org/changeset/base/338466 Log: Fix bug: compare uaddr to VM_MAXUSER_ADDRESS, not to a tmp value left by SET_FAULT_HANDLER(). Approved by: re (kib) Sponsored by: DARPA, AFRL Modified: head/sys/

svn commit: r338467 - in head/sys/riscv: include riscv

/sys/riscv/include/asm.hWed Sep 5 11:34:58 2018 (r338467) @@ -1,5 +1,5 @@ /*- - * Copyright (c) 2015 Ruslan Bukin + * Copyright (c) 2015-2018 Ruslan Bukin * All rights reserved. * * Portions of this software were developed by SRI International and the @@ -62,5 +62,13

svn commit: r338608 - in head/sys: net sys

Author: br Date: Wed Sep 12 08:05:33 2018 New Revision: 338608 URL: https://svnweb.freebsd.org/changeset/base/338608 Log: Don't mark module data as static on RISC-V. Similar to arm64, riscv compiler uses PC-relative loads/stores, and with static data compiler does not emit relocations.

svn commit: r338609 - head/sys/riscv/riscv

Author: br Date: Wed Sep 12 08:12:34 2018 New Revision: 338609 URL: https://svnweb.freebsd.org/changeset/base/338609 Log: Use elf_relocaddr() to find the address for R_RISCV_RELATIVE relocation. elf_relocaddr() has a hook to handle VIMAGE data addresses. This fixes VIMAGE support for

svn commit: r338610 - head/sys/riscv/conf

Author: br Date: Wed Sep 12 08:13:54 2018 New Revision: 338610 URL: https://svnweb.freebsd.org/changeset/base/338610 Log: Enable VIMAGE support for RISC-V. Approved by: re (gjb) Sponsored by: DARPA, AFRL Modified: head/sys/riscv/conf/GENERIC Modified: head/sys/riscv/conf/GENERIC

svn commit: r339064 - head/usr.sbin/pmc

Author: br Date: Mon Oct 1 16:16:05 2018 New Revision: 339064 URL: https://svnweb.freebsd.org/changeset/base/339064 Log: Fix build with GCC 8.1. GCC 8.1 failed to build LLVM's libc++ when -Wshadow is set, so lower down WARNS flag to 3. This is similar to dtc(1) which uses libc++ and

svn commit: r339330 - in head/sys: conf dev/uart riscv/conf

:00:00 1970 (empty, because file is newly added) +++ head/sys/dev/uart/uart_dev_lowrisc.cFri Oct 12 15:19:41 2018 (r339330) @@ -0,0 +1,393 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2018 Ruslan Bukin + * All rights reserved. + * + * This software was

svn commit: r339332 - head/sys/riscv/riscv

Author: br Date: Fri Oct 12 15:51:41 2018 New Revision: 339332 URL: https://svnweb.freebsd.org/changeset/base/339332 Log: Initialize interrupt priority to 0 on all sources. Without this hardware raises an interrupt regardless of any pending bits set. This fixes operation on RocketChi

svn commit: r339381 - head/sys/riscv/riscv

Author: br Date: Tue Oct 16 16:03:17 2018 New Revision: 339381 URL: https://svnweb.freebsd.org/changeset/base/339381 Log: Invalidate TLB on a local hart. This was missed in r339367 ("Various fixes for TLB management on RISC-V."). This fixes operation on lowRISC. Reviewed by: jhb

svn commit: r339421 - in head/sys: arm/arm arm/conf dts/arm riscv/include riscv/riscv

ap_t, vm_offset_t, pd_entry_t * #definepmap_page_is_mapped(m) (!TAILQ_EMPTY(&(m)->md.pv_list)) +int pmap_fault_fixup(pmap_t, vm_offset_t, vm_prot_t); + #endif /* _KERNEL */ #endif /* !LOCORE */ Modified: head/sys/riscv/include/pte.h =

svn commit: r339422 - in head/sys: arm/arm arm/conf dts/arm riscv/include riscv/riscv

-153,8 +153,6 @@ boolpmap_get_tables(pmap_t, vm_offset_t, pd_entry_t * #definepmap_page_is_mapped(m) (!TAILQ_EMPTY(&(m)->md.pv_list)) -int pmap_fault_fixup(pmap_t, vm_offset_t, vm_prot_t); - #endif /* _KERNEL */ #endif /* !LOCORE */ Modified: head/sys/riscv/inclu

svn commit: r339423 - in head/sys/riscv: include riscv

07 2018 (r339423) @@ -1,6 +1,6 @@ /*- * Copyright (c) 2014 Andrew Turner - * Copyright (c) 2015-2016 Ruslan Bukin + * Copyright (c) 2015-2018 Ruslan Bukin * All rights reserved. * * Portions of this software were developed by SRI International and the @@ -65,7 +65,7 @@ typedef u

Re: svn commit: r339421 - in head/sys: arm/arm arm/conf dts/arm riscv/include riscv/riscv

On Thu, Oct 18, 2018 at 09:13:20AM -0600, Ian Lepore wrote: > On Thu, 2018-10-18 at 15:08 +0000, Ruslan Bukin wrote: > > Author: br > > Date: Thu Oct 18 15:08:14 2018 > > New Revision: 339421 > > URL: https://svnweb.freebsd.org/changeset/base/339421 > &g

svn commit: r339774 - head/sys/riscv/riscv

Author: br Date: Fri Oct 26 12:27:07 2018 New Revision: 339774 URL: https://svnweb.freebsd.org/changeset/base/339774 Log: o Add pmap lock around pmap_fault_fixup() to ensure other thread will not modify l3 pte after we loaded old value and before we stored new value. o Preset A(accessed),

svn commit: r331220 - in head/contrib/processor-trace: . include libipt libipt/include

Author: br Date: Mon Mar 19 18:59:15 2018 New Revision: 331220 URL: https://svnweb.freebsd.org/changeset/base/331220 Log: Import Intel Processor Trace decoder library from vendor/processor-trace/24982c1a6fce48f1e416461d42899805f74fbb26 Sponsored by: DARPA, AFRL Added: head/contrib/proc

svn commit: r331293 - in head: etc/mtree lib lib/libipt share/mk

Author: br Date: Wed Mar 21 14:37:04 2018 New Revision: 331293 URL: https://svnweb.freebsd.org/changeset/base/331293 Log: Add new shared library -- libipt. libipt is the Intel Processor Trace (Intel PT) packets decoder. - Include libipt to amd64 build. - Install libipt headers to /us

svn commit: r305208 - in head/sys: boot/fdt/dts/riscv riscv/riscv

/rocket.dts Thu Sep 1 14:58:11 2016 (r305208) @@ -1,5 +1,5 @@ /*- - * Copyright (c) 2016 Ruslan Bukin + * Copyright (c) 2015-2016 Ruslan Bukin * All rights reserved. * * Portions of this software were developed by SRI International and the @@ -37,8 +37,8 @@ /dts-v1

svn commit: r305541 - head/sys/boot/fdt/dts/riscv

Author: br Date: Wed Sep 7 15:48:44 2016 New Revision: 305541 URL: https://svnweb.freebsd.org/changeset/base/305541 Log: o Update QEMU device tree. QEMU was updated to privileged architecture v1.9 and we now fully support it. Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Modified

svn commit: r305621 - in head/sys/mips: cavium gxemul include mips nlm rmi sibyte

Author: br Date: Thu Sep 8 17:37:13 2016 New Revision: 305621 URL: https://svnweb.freebsd.org/changeset/base/305621 Log: Allow the use of soft-interrupts for sending IPIs. This will be required for SMP support on MIPS Malta platform. Reviewed by: adrian Sponsored by: DARPA, AFRL Spo

svn commit: r305664 - in head/sys: conf mips/malta mips/mips

) +++ head/sys/mips/malta/asm_malta.S Fri Sep 9 14:50:44 2016 (r305664) @@ -0,0 +1,89 @@ +/*- + * Copyright (c) 2016 Ruslan Bukin + * All rights reserved. + * + * Portions of this software were developed by SRI International and the + * University of Cambridge Computer Laboratory under

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