Re: svn commit: r340653 - in head/sys/powerpc: fpu include powerpc

2018-11-19 Thread Justin Hibbits
Well, this is to allow a retry in case the cache wasn't properly flushed already. This came about because the blrl instruction in the GOT was seen as an illegal instruction, and it didn't seem to matter if I synced in pmap_enter(), it would still SIGILL probabilistically. Since this block was alr

Re: svn commit: r340653 - in head/sys/powerpc: fpu include powerpc

2018-11-19 Thread Nathan Whitehorn
Is this reasonable? What if the junk in the cache happened to be a *valid* instruction? Won't this approach result in silent corruption and later failure? -Nathan On 11/19/18 3:54 PM, Justin Hibbits wrote: > Author: jhibbits > Date: Mon Nov 19 23:54:49 2018 > New Revision: 340653 > URL: https://sv

svn commit: r340653 - in head/sys/powerpc: fpu include powerpc

2018-11-19 Thread Justin Hibbits
Author: jhibbits Date: Mon Nov 19 23:54:49 2018 New Revision: 340653 URL: https://svnweb.freebsd.org/changeset/base/340653 Log: powerpc: Sync icache on SIGILL, in case of cache issues The update of jemalloc to 5.1.0 exposed a cache syncing issue on a Freescale e500 base system. There was