CVS commit: src/sys/dtb/arm

2023-05-04 Thread Manuel Bouyer
Module Name:src Committed By: bouyer Date: Thu May 4 13:31:37 UTC 2023 Modified Files: src/sys/dtb/arm: Makefile Log Message: Also build dtb files for CONFIG_SOC_IMX6SX To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/dtb/arm/Makefile Please note tha

CVS commit: src/sys/dtb/arm

2023-05-04 Thread Manuel Bouyer
Module Name:src Committed By: bouyer Date: Thu May 4 13:31:37 UTC 2023 Modified Files: src/sys/dtb/arm: Makefile Log Message: Also build dtb files for CONFIG_SOC_IMX6SX To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/dtb/arm/Makefile Please note tha

CVS commit: src/sys/dtb/arm

2021-11-12 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Fri Nov 12 21:55:17 UTC 2021 Modified Files: src/sys/dtb/arm: Makefile Log Message: Build rockchip dtb files for armv7. To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/dtb/arm/Makefile Please note that dif

CVS commit: src/sys/dtb/arm

2021-11-12 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Fri Nov 12 21:55:17 UTC 2021 Modified Files: src/sys/dtb/arm: Makefile Log Message: Build rockchip dtb files for armv7. To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/dtb/arm/Makefile Please note that dif

CVS commit: src/sys/dtb/arm

2021-11-07 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Sun Nov 7 17:10:23 UTC 2021 Modified Files: src/sys/dtb/arm: Makefile Log Message: CONFIG_ARCH_SOCFPGA has been renamed CONFIG_ARCH_INTEL_SOCFPGA To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/dtb/arm/Mak

CVS commit: src/sys/dtb/arm

2021-11-07 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Sun Nov 7 17:10:23 UTC 2021 Modified Files: src/sys/dtb/arm: Makefile Log Message: CONFIG_ARCH_SOCFPGA has been renamed CONFIG_ARCH_INTEL_SOCFPGA To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/dtb/arm/Mak