Module Name:src
Committed By: imil
Date: Thu Mar 6 09:02:47 UTC 2025
Modified Files:
src/sys/arch/x86/x86: identcpu_subr.c
Log Message:
Test for LAPIC support
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/x86/x86/identcpu_subr.c
Please note
Module Name:src
Committed By: imil
Date: Thu Mar 6 15:35:05 UTC 2025
Modified Files:
src/sys/arch/x86/include: apicvar.h
src/sys/arch/x86/x86: cpu.c identcpu_subr.c lapic.c
Log Message:
Revert VMware-compatible TSC and LAPIC frequency detection.
To generate a di
Module Name:src
Committed By: imil
Date: Thu Mar 6 15:35:05 UTC 2025
Modified Files:
src/sys/arch/x86/include: apicvar.h
src/sys/arch/x86/x86: cpu.c identcpu_subr.c lapic.c
Log Message:
Revert VMware-compatible TSC and LAPIC frequency detection.
To generate a di
Module Name:src
Committed By: imil
Date: Thu Mar 6 09:31:05 UTC 2025
Modified Files:
src/sys/arch/x86/x86: identcpu_subr.c
Log Message:
Allow tsc_freq_vmware_cpuid() for TSC frequency even if there is no LAPIC
support
To generate a diff of this commit:
cvs rdiff -u -r1
Module Name:src
Committed By: imil
Date: Thu Mar 6 09:31:05 UTC 2025
Modified Files:
src/sys/arch/x86/x86: identcpu_subr.c
Log Message:
Allow tsc_freq_vmware_cpuid() for TSC frequency even if there is no LAPIC
support
To generate a diff of this commit:
cvs rdiff -u -r1
Module Name:src
Committed By: imil
Date: Thu Mar 6 09:02:47 UTC 2025
Modified Files:
src/sys/arch/x86/x86: identcpu_subr.c
Log Message:
Test for LAPIC support
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/x86/x86/identcpu_subr.c
Please note
Module Name:src
Committed By: imil
Date: Thu Mar 6 06:31:53 UTC 2025
Modified Files:
src/sys/arch/x86/include: apicvar.h
src/sys/arch/x86/x86: cpu.c identcpu_subr.c lapic.c
Log Message:
Add support for CPUID leaf 0x4010, which enables VMware-compatible TSC
and
Module Name:src
Committed By: imil
Date: Thu Mar 6 06:31:53 UTC 2025
Modified Files:
src/sys/arch/x86/include: apicvar.h
src/sys/arch/x86/x86: cpu.c identcpu_subr.c lapic.c
Log Message:
Add support for CPUID leaf 0x4010, which enables VMware-compatible TSC
and
Module Name:src
Committed By: imil
Date: Mon Feb 24 07:18:02 UTC 2025
Modified Files:
src/sys/arch/x86/isa: clock.c
Log Message:
Check for RTC presence to avoid hang with QEMU microvm and rtc=off
parameter.
Test bits 0-6 of MC146818's Register D, which must be 0 according
Module Name:src
Committed By: imil
Date: Mon Feb 24 07:18:02 UTC 2025
Modified Files:
src/sys/arch/x86/isa: clock.c
Log Message:
Check for RTC presence to avoid hang with QEMU microvm and rtc=off
parameter.
Test bits 0-6 of MC146818's Register D, which must be 0 according
Module Name:src
Committed By: riastradh
Date: Fri Jan 17 10:38:48 UTC 2025
Modified Files:
src/sys/arch/x86/x86: identcpu.c
Log Message:
x86/identcpu.c: Add archive link just in case.
Refill paragraph while here to avoid overlong lines.
To generate a diff of this commit
Module Name:src
Committed By: riastradh
Date: Fri Jan 17 10:38:48 UTC 2025
Modified Files:
src/sys/arch/x86/x86: identcpu.c
Log Message:
x86/identcpu.c: Add archive link just in case.
Refill paragraph while here to avoid overlong lines.
To generate a diff of this commit
Module Name:src
Committed By: riastradh
Date: Tue Jan 14 08:03:40 UTC 2025
Modified Files:
src/sys/arch/x86/pv: pvbus.c
Log Message:
x86/pvbus(4): KNF. No functional change intended.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/x86/pv/pvbus.c
Module Name:src
Committed By: riastradh
Date: Tue Jan 14 08:03:40 UTC 2025
Modified Files:
src/sys/arch/x86/pv: pvbus.c
Log Message:
x86/pvbus(4): KNF. No functional change intended.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/x86/pv/pvbus.c
Module Name:src
Committed By: andvar
Date: Mon Jan 13 18:51:37 UTC 2025
Modified Files:
src/sys/arch/x86/x86: identcpu.c
Log Message:
Remove stepping check for APL30 Errata. Issue also affects newer Apollo Lake
CPUs. Therefore, the stepping check is unnecessary.
Include a
Module Name:src
Committed By: andvar
Date: Mon Jan 13 18:51:37 UTC 2025
Modified Files:
src/sys/arch/x86/x86: identcpu.c
Log Message:
Remove stepping check for APL30 Errata. Issue also affects newer Apollo Lake
CPUs. Therefore, the stepping check is unnecessary.
Include a
Module Name:src
Committed By: imil
Date: Mon Jan 13 06:35:38 UTC 2025
Modified Files:
src/sys/arch/x86/x86: mpbios.c
Log Message:
Firecracker and qemu/microvm in MMIO mode don't have ACPI, either
they rely on MP tables, but using it IOAPIC was not detected.
This patch fixe
Module Name:src
Committed By: imil
Date: Mon Jan 13 06:35:38 UTC 2025
Modified Files:
src/sys/arch/x86/x86: mpbios.c
Log Message:
Firecracker and qemu/microvm in MMIO mode don't have ACPI, either
they rely on MP tables, but using it IOAPIC was not detected.
This patch fixe
Module Name:src
Committed By: jakllsch
Date: Tue Jan 7 22:37:13 UTC 2025
Modified Files:
src/sys/arch/x86/isa: rtc.c
Log Message:
Only use FADT Century byte if it targets a valid 146818 NVRAM location.
Should fix PR 57821.
To generate a diff of this commit:
cvs rdiff -
Module Name:src
Committed By: jakllsch
Date: Tue Jan 7 22:37:13 UTC 2025
Modified Files:
src/sys/arch/x86/isa: rtc.c
Log Message:
Only use FADT Century byte if it targets a valid 146818 NVRAM location.
Should fix PR 57821.
To generate a diff of this commit:
cvs rdiff -
Module Name:src
Committed By: hans
Date: Wed Dec 18 18:18:30 UTC 2024
Modified Files:
src/sys/arch/x86/pci: ichlpcib.c
Log Message:
Add support for the Braswell PCU LPC to ichlpcib.
To generate a diff of this commit:
cvs rdiff -u -r1.61 -r1.62 src/sys/arch/x86/pci/ichlpc
Module Name:src
Committed By: hans
Date: Wed Dec 18 18:18:30 UTC 2024
Modified Files:
src/sys/arch/x86/pci: ichlpcib.c
Log Message:
Add support for the Braswell PCU LPC to ichlpcib.
To generate a diff of this commit:
cvs rdiff -u -r1.61 -r1.62 src/sys/arch/x86/pci/ichlpc
Module Name:src
Committed By: martin
Date: Mon Nov 11 17:28:38 UTC 2024
Modified Files:
src/sys/arch/x86/pci: dwiic_pci.c
Log Message:
Add missing include of "acpica.h", pointed out by Jared.
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/x86/
Module Name:src
Committed By: martin
Date: Mon Nov 11 17:28:38 UTC 2024
Modified Files:
src/sys/arch/x86/pci: dwiic_pci.c
Log Message:
Add missing include of "acpica.h", pointed out by Jared.
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/x86/
Module Name:src
Committed By: msaitoh
Date: Sat Oct 19 06:35:10 UTC 2024
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
x86/specialreg.h: Update AMD CPUID definitions.
- Add AMD Hetero Workload Classification.
- Extend the number of UMC PMCs field f
Module Name:src
Committed By: msaitoh
Date: Sat Oct 19 06:35:10 UTC 2024
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
x86/specialreg.h: Update AMD CPUID definitions.
- Add AMD Hetero Workload Classification.
- Extend the number of UMC PMCs field f
Module Name:src
Committed By: msaitoh
Date: Thu Oct 17 14:22:35 UTC 2024
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
x86/specialreg.h: Update AMD CPUID definitions.
Update definitions from the following PPR:
- PPR for AMD Family 19h Model 11h,
Module Name:src
Committed By: msaitoh
Date: Thu Oct 17 14:22:35 UTC 2024
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
x86/specialreg.h: Update AMD CPUID definitions.
Update definitions from the following PPR:
- PPR for AMD Family 19h Model 11h,
Module Name:src
Committed By: msaitoh
Date: Thu Oct 17 14:16:48 UTC 2024
Modified Files:
src/sys/arch/x86/pci: amdzentemp.c
Log Message:
amdzentemp(4): Add some CPU support.
- Zen4 "Siena" (family 1fh mode 0xa0...0xaf)
- Zen5 "Turin Classic" (family 1ah mode 0x0
Module Name:src
Committed By: msaitoh
Date: Thu Oct 17 14:16:48 UTC 2024
Modified Files:
src/sys/arch/x86/pci: amdzentemp.c
Log Message:
amdzentemp(4): Add some CPU support.
- Zen4 "Siena" (family 1fh mode 0xa0...0xaf)
- Zen5 "Turin Classic" (family 1ah mode 0x0
Module Name:src
Committed By: msaitoh
Date: Thu Oct 17 14:02:40 UTC 2024
Modified Files:
src/sys/arch/x86/pci: amdsmn.c
Log Message:
amdsmn(4): Add support AMD family F1Ah model 0xh "Turin".
To generate a diff of this commit:
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/x86/p
Module Name:src
Committed By: msaitoh
Date: Thu Oct 17 14:02:40 UTC 2024
Modified Files:
src/sys/arch/x86/pci: amdsmn.c
Log Message:
amdsmn(4): Add support AMD family F1Ah model 0xh "Turin".
To generate a diff of this commit:
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/x86/p
Module Name:src
Committed By: riastradh
Date: Tue Oct 8 21:09:08 UTC 2024
Modified Files:
src/sys/arch/x86/x86: pmap.c
Log Message:
x86/pmap: Use UVM_KMF_WAITVA to ensure pmap_pdp_alloc never fails.
This is used as the backing page allocator for pmap_pdp_pool, and
pmap_c
Module Name:src
Committed By: riastradh
Date: Tue Oct 8 21:09:08 UTC 2024
Modified Files:
src/sys/arch/x86/x86: pmap.c
Log Message:
x86/pmap: Use UVM_KMF_WAITVA to ensure pmap_pdp_alloc never fails.
This is used as the backing page allocator for pmap_pdp_pool, and
pmap_c
Module Name:src
Committed By: msaitoh
Date: Sun Oct 6 15:36:05 UTC 2024
Modified Files:
src/sys/arch/x86/x86: procfs_machdep.c
Log Message:
Add AMD svsm bit for x86's /proc/cpuinfo
To generate a diff of this commit:
cvs rdiff -u -r1.48 -r1.49 src/sys/arch/x86/x86/procfs
Module Name:src
Committed By: msaitoh
Date: Sun Oct 6 15:36:05 UTC 2024
Modified Files:
src/sys/arch/x86/x86: procfs_machdep.c
Log Message:
Add AMD svsm bit for x86's /proc/cpuinfo
To generate a diff of this commit:
cvs rdiff -u -r1.48 -r1.49 src/sys/arch/x86/x86/procfs
Module Name:src
Committed By: msaitoh
Date: Sun Oct 6 09:32:31 UTC 2024
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
Add some unknown CPUID bits for AMD.
To generate a diff of this commit:
cvs rdiff -u -r1.213 -r1.214 src/sys/arch/x86/include/spec
Module Name:src
Committed By: msaitoh
Date: Sun Oct 6 09:32:31 UTC 2024
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
Add some unknown CPUID bits for AMD.
To generate a diff of this commit:
cvs rdiff -u -r1.213 -r1.214 src/sys/arch/x86/include/spec
Module Name:src
Committed By: msaitoh
Date: Sun Oct 6 08:49:12 UTC 2024
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
Add some CPUID bits for AMD.
To generate a diff of this commit:
cvs rdiff -u -r1.212 -r1.213 src/sys/arch/x86/include/specialreg.h
Module Name:src
Committed By: msaitoh
Date: Sun Oct 6 08:49:12 UTC 2024
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
Add some CPUID bits for AMD.
To generate a diff of this commit:
cvs rdiff -u -r1.212 -r1.213 src/sys/arch/x86/include/specialreg.h
Module Name:src
Committed By: msaitoh
Date: Fri Oct 4 03:04:40 UTC 2024
Modified Files:
src/sys/arch/x86/pci: amdzentemp.c
Log Message:
amdzentemp(4): Add support for CPU family 0x1a model 0x40...0x4f (Zen 5)
To generate a diff of this commit:
cvs rdiff -u -r1.20 -r1.21
Module Name:src
Committed By: msaitoh
Date: Fri Oct 4 03:04:40 UTC 2024
Modified Files:
src/sys/arch/x86/pci: amdzentemp.c
Log Message:
amdzentemp(4): Add support for CPU family 0x1a model 0x40...0x4f (Zen 5)
To generate a diff of this commit:
cvs rdiff -u -r1.20 -r1.21
Module Name:src
Committed By: riastradh
Date: Thu Oct 3 12:29:07 UTC 2024
Modified Files:
src/sys/arch/x86/x86: tsc.c
Log Message:
x86/tsc.c: Fix comment indentation.
No functional change intended.
To generate a diff of this commit:
cvs rdiff -u -r1.60 -r1.61 src/sys/a
Module Name:src
Committed By: riastradh
Date: Thu Oct 3 12:29:07 UTC 2024
Modified Files:
src/sys/arch/x86/x86: tsc.c
Log Message:
x86/tsc.c: Fix comment indentation.
No functional change intended.
To generate a diff of this commit:
cvs rdiff -u -r1.60 -r1.61 src/sys/a
Module Name:src
Committed By: bouyer
Date: Mon Sep 30 17:00:10 UTC 2024
Modified Files:
src/sys/arch/x86/x86: mpacpi.c
Log Message:
Remove check (x2apic->LocalApicId <= 0xff) in mpacpi_config_cpu(),
the ACPI spec mentions this for compatibility with "legacy OSes" but
doens
Module Name:src
Committed By: bouyer
Date: Mon Sep 30 17:00:10 UTC 2024
Modified Files:
src/sys/arch/x86/x86: mpacpi.c
Log Message:
Remove check (x2apic->LocalApicId <= 0xff) in mpacpi_config_cpu(),
the ACPI spec mentions this for compatibility with "legacy OSes" but
doens
On Wed, Sep 11, 2024 at 05:17:45 +, matthew green wrote:
> Module Name: src
> Committed By: mrg
> Date: Wed Sep 11 05:17:45 UTC 2024
>
> Modified Files:
> src/sys/arch/x86/x86: intr.c
>
> Log Message:
> apply some more diagnostic checks for x86 interrupts
How does this mix wi
Module Name:src
Committed By: mrg
Date: Wed Sep 11 05:17:45 UTC 2024
Modified Files:
src/sys/arch/x86/x86: intr.c
Log Message:
apply some more diagnostic checks for x86 interrupts
convert intr_biglock_wrapper() into a slight less complete
intr_wrapper(), and move the kern
Module Name:src
Committed By: mrg
Date: Wed Sep 11 05:17:45 UTC 2024
Modified Files:
src/sys/arch/x86/x86: intr.c
Log Message:
apply some more diagnostic checks for x86 interrupts
convert intr_biglock_wrapper() into a slight less complete
intr_wrapper(), and move the kern
Module Name:src
Committed By: riastradh
Date: Thu Aug 1 11:18:54 UTC 2024
Modified Files:
src/sys/arch/x86/x86: cpu_rng.c
Log Message:
x86/cpu_rng.c: Archive more links.
Why do major hardware manufacturers consistently seem to think links
should just stop working after a
Module Name:src
Committed By: riastradh
Date: Thu Aug 1 11:18:54 UTC 2024
Modified Files:
src/sys/arch/x86/x86: cpu_rng.c
Log Message:
x86/cpu_rng.c: Archive more links.
Why do major hardware manufacturers consistently seem to think links
should just stop working after a
Module Name:src
Committed By: riastradh
Date: Wed Jul 31 22:44:49 UTC 2024
Modified Files:
src/sys/arch/x86/x86: cpu_rng.c
Log Message:
x86/cpu_rng.c: Add reference for Intel's hardware design.
Not normative, unverifiable, possibly outdated -- but still a useful
descripti
Module Name:src
Committed By: riastradh
Date: Wed Jul 31 22:44:49 UTC 2024
Modified Files:
src/sys/arch/x86/x86: cpu_rng.c
Log Message:
x86/cpu_rng.c: Add reference for Intel's hardware design.
Not normative, unverifiable, possibly outdated -- but still a useful
descripti
Module Name:src
Committed By: gutteridge
Date: Mon Jul 15 01:57:23 UTC 2024
Modified Files:
src/sys/arch/x86/x86: coretemp.c
Log Message:
coretemp.c: drop redundant condition (NFCI)
Checking for a processor model upper limit has no point inside a block
that is already lim
Module Name:src
Committed By: gutteridge
Date: Mon Jul 15 01:57:23 UTC 2024
Modified Files:
src/sys/arch/x86/x86: coretemp.c
Log Message:
coretemp.c: drop redundant condition (NFCI)
Checking for a processor model upper limit has no point inside a block
that is already lim
Module Name:src
Committed By: andvar
Date: Mon Jul 1 19:40:03 UTC 2024
Modified Files:
src/sys/arch/x86/include: specialreg.h
src/sys/arch/x86/x86: identcpu.c
Log Message:
Disable the VIA Alternate Instructions according the VIA documentation:
* C7 and above do no
Module Name:src
Committed By: andvar
Date: Mon Jul 1 19:40:03 UTC 2024
Modified Files:
src/sys/arch/x86/include: specialreg.h
src/sys/arch/x86/x86: identcpu.c
Log Message:
Disable the VIA Alternate Instructions according the VIA documentation:
* C7 and above do no
Module Name:src
Committed By: andvar
Date: Sun Jun 30 15:49:56 UTC 2024
Modified Files:
src/sys/arch/x86/x86: identcpu.c
Log Message:
Move determination of the largest VIA CPU extended function value
to the intended place where the checks are performed.
Currently the valu
Module Name:src
Committed By: andvar
Date: Sun Jun 30 15:49:56 UTC 2024
Modified Files:
src/sys/arch/x86/x86: identcpu.c
Log Message:
Move determination of the largest VIA CPU extended function value
to the intended place where the checks are performed.
Currently the valu
Module Name:src
Committed By: riastradh
Date: Fri Jun 21 17:24:08 UTC 2024
Modified Files:
src/sys/arch/x86/x86: fpu.c
Log Message:
x86/fpu.c: Nix trailing whitespace.
No functional change intended.
To generate a diff of this commit:
cvs rdiff -u -r1.88 -r1.89 src/sys/a
Module Name:src
Committed By: riastradh
Date: Fri Jun 21 17:24:08 UTC 2024
Modified Files:
src/sys/arch/x86/x86: fpu.c
Log Message:
x86/fpu.c: Nix trailing whitespace.
No functional change intended.
To generate a diff of this commit:
cvs rdiff -u -r1.88 -r1.89 src/sys/a
Module Name:src
Committed By: riastradh
Date: Sun Jun 9 20:07:33 UTC 2024
Modified Files:
src/sys/arch/x86/x86: cpu_rng.c
Log Message:
x86/cpu_rng: Fix false alarm rate of CPU RNG health test.
Lower it from 1/2^32 (about one in four billion) to 1/2^256
(approximately not
Module Name:src
Committed By: riastradh
Date: Sun Jun 9 20:07:33 UTC 2024
Modified Files:
src/sys/arch/x86/x86: cpu_rng.c
Log Message:
x86/cpu_rng: Fix false alarm rate of CPU RNG health test.
Lower it from 1/2^32 (about one in four billion) to 1/2^256
(approximately not
Module Name:src
Committed By: riastradh
Date: Tue Jun 4 21:42:58 UTC 2024
Modified Files:
src/sys/arch/x86/x86: bus_dma.c
Log Message:
x86: Teach bus_dmamem_map about BUS_DMA_PREFETCHABLE.
PR port-amd64/58308
To generate a diff of this commit:
cvs rdiff -u -r1.90 -r1.9
Module Name:src
Committed By: riastradh
Date: Tue Jun 4 21:42:58 UTC 2024
Modified Files:
src/sys/arch/x86/x86: bus_dma.c
Log Message:
x86: Teach bus_dmamem_map about BUS_DMA_PREFETCHABLE.
PR port-amd64/58308
To generate a diff of this commit:
cvs rdiff -u -r1.90 -r1.9
Module Name:src
Committed By: manu
Date: Fri May 17 00:37:14 UTC 2024
Modified Files:
src/sys/arch/x86/x86: fpu.c
Log Message:
iWorkaround panic: fpudna from userland
i386 Xen PV domU get spurious fpudna traps from userland. Older eager FPU
contact switching code took car
Module Name:src
Committed By: manu
Date: Fri May 17 00:37:14 UTC 2024
Modified Files:
src/sys/arch/x86/x86: fpu.c
Log Message:
iWorkaround panic: fpudna from userland
i386 Xen PV domU get spurious fpudna traps from userland. Older eager FPU
contact switching code took car
Module Name:src
Committed By: msaitoh
Date: Sun May 12 23:41:10 UTC 2024
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
s/RPMQUERY/RMPQUERY/
To generate a diff of this commit:
cvs rdiff -u -r1.210 -r1.211 src/sys/arch/x86/include/specialreg.h
Please
Module Name:src
Committed By: msaitoh
Date: Sun May 12 23:41:10 UTC 2024
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
s/RPMQUERY/RMPQUERY/
To generate a diff of this commit:
cvs rdiff -u -r1.210 -r1.211 src/sys/arch/x86/include/specialreg.h
Please
Module Name:src
Committed By: andvar
Date: Mon Apr 29 21:29:48 UTC 2024
Modified Files:
src/sys/arch/x86/pci: dwiic_pci.c
Log Message:
Make dwiic_pci compile without ACPI option.
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/x86/pci/dwiic_pci.
Module Name:src
Committed By: andvar
Date: Mon Apr 29 21:29:48 UTC 2024
Modified Files:
src/sys/arch/x86/pci: dwiic_pci.c
Log Message:
Make dwiic_pci compile without ACPI option.
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/x86/pci/dwiic_pci.
Module Name:src
Committed By: andvar
Date: Mon Apr 22 23:07:47 UTC 2024
Modified Files:
src/sys/arch/x86/x86: cpu.c
Log Message:
Surround full mp_cpu_start() method with NLAPIC > 0 guard.
Initialization is based on x86_ipi* functions, which are implemented only
when lapic
Module Name:src
Committed By: andvar
Date: Mon Apr 22 23:07:47 UTC 2024
Modified Files:
src/sys/arch/x86/x86: cpu.c
Log Message:
Surround full mp_cpu_start() method with NLAPIC > 0 guard.
Initialization is based on x86_ipi* functions, which are implemented only
when lapic
Module Name:src
Committed By: andvar
Date: Mon Apr 22 22:29:29 UTC 2024
Modified Files:
src/sys/arch/x86/x86: intr.c
Log Message:
Add opt_pci.h include to fix NO_PCI_MSI_MSIX build.
(Path from Paolo Pisati in current_users@)
While here:
Simplify mp_cpu_start() ifdefs. MUL
Module Name:src
Committed By: andvar
Date: Mon Apr 22 22:29:29 UTC 2024
Modified Files:
src/sys/arch/x86/x86: intr.c
Log Message:
Add opt_pci.h include to fix NO_PCI_MSI_MSIX build.
(Path from Paolo Pisati in current_users@)
While here:
Simplify mp_cpu_start() ifdefs. MUL
Module Name:src
Committed By: andvar
Date: Sat Apr 13 09:12:09 UTC 2024
Modified Files:
src/sys/arch/x86/x86: viac7temp.c
Log Message:
viac7temp(4): define module metadata using MODULE() macro and implement
viac7temp_modcmd() to handle module load/unload events.
Fixes PR
Module Name:src
Committed By: andvar
Date: Sat Apr 13 09:12:09 UTC 2024
Modified Files:
src/sys/arch/x86/x86: viac7temp.c
Log Message:
viac7temp(4): define module metadata using MODULE() macro and implement
viac7temp_modcmd() to handle module load/unload events.
Fixes PR
Module Name:src
Committed By: gutteridge
Date: Tue Mar 12 02:26:16 UTC 2024
Modified Files:
src/sys/arch/x86/x86: coretemp.c
Log Message:
coretemp.c: don't accept impossibly low TjMax values
r. 1.39 introduced a regression where instead of applying a reasonable
default ma
Module Name:src
Committed By: gutteridge
Date: Tue Mar 12 02:26:16 UTC 2024
Modified Files:
src/sys/arch/x86/x86: coretemp.c
Log Message:
coretemp.c: don't accept impossibly low TjMax values
r. 1.39 introduced a regression where instead of applying a reasonable
default ma
Module Name:src
Committed By: gutteridge
Date: Thu Feb 29 01:59:12 UTC 2024
Modified Files:
src/sys/arch/x86/x86: coretemp.c
Log Message:
coretemp.c: fix grammar in a warning message
(I get several of these warnings on boot on a particular machine. Now,
it also seems that
Module Name:src
Committed By: gutteridge
Date: Thu Feb 29 01:59:12 UTC 2024
Modified Files:
src/sys/arch/x86/x86: coretemp.c
Log Message:
coretemp.c: fix grammar in a warning message
(I get several of these warnings on boot on a particular machine. Now,
it also seems that
Module Name:src
Committed By: andvar
Date: Sun Feb 25 18:27:54 UTC 2024
Modified Files:
src/sys/arch/x86/x86: lapic.c
Log Message:
s/asynchronious/asynchronous/ in comment.
To generate a diff of this commit:
cvs rdiff -u -r1.89 -r1.90 src/sys/arch/x86/x86/lapic.c
Please
Module Name:src
Committed By: andvar
Date: Sun Feb 25 18:27:54 UTC 2024
Modified Files:
src/sys/arch/x86/x86: lapic.c
Log Message:
s/asynchronious/asynchronous/ in comment.
To generate a diff of this commit:
cvs rdiff -u -r1.89 -r1.90 src/sys/arch/x86/x86/lapic.c
Please
Module Name:src
Committed By: mrg
Date: Mon Feb 19 20:10:09 UTC 2024
Modified Files:
src/sys/arch/x86/x86: tsc.c
Log Message:
remove unintended printf() in previous. (thx dh)
To generate a diff of this commit:
cvs rdiff -u -r1.59 -r1.60 src/sys/arch/x86/x86/tsc.c
Pleas
Module Name:src
Committed By: mrg
Date: Mon Feb 19 20:10:09 UTC 2024
Modified Files:
src/sys/arch/x86/x86: tsc.c
Log Message:
remove unintended printf() in previous. (thx dh)
To generate a diff of this commit:
cvs rdiff -u -r1.59 -r1.60 src/sys/arch/x86/x86/tsc.c
Pleas
Module Name:src
Committed By: mrg
Date: Mon Feb 19 09:22:31 UTC 2024
Modified Files:
src/sys/arch/x86/x86: tsc.c
Log Message:
make TSC get a quality of -100 on AMD Family 15h and 16h
this should "fix" PR#56322 and is known as AMD errata
"778: Processor Core Time Stamp Cou
Module Name:src
Committed By: mrg
Date: Mon Feb 19 09:22:31 UTC 2024
Modified Files:
src/sys/arch/x86/x86: tsc.c
Log Message:
make TSC get a quality of -100 on AMD Family 15h and 16h
this should "fix" PR#56322 and is known as AMD errata
"778: Processor Core Time Stamp Cou
Module Name:src
Committed By: christos
Date: Tue Jan 2 19:28:25 UTC 2024
Modified Files:
src/sys/arch/x86/include: ieee.h
Log Message:
use sized types
To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/x86/include/ieee.h
Please note that diffs a
Module Name:src
Committed By: christos
Date: Tue Jan 2 19:28:25 UTC 2024
Modified Files:
src/sys/arch/x86/include: ieee.h
Log Message:
use sized types
To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/x86/include/ieee.h
Please note that diffs a
Module Name:src
Committed By: mlelstv
Date: Wed Nov 29 11:40:37 UTC 2023
Modified Files:
src/sys/arch/x86/x86: intr.c
Log Message:
Fix use-after-free (source->is_type) when detecting unsharable
interrupts. Doesn't solve the interrupt conflict itself, but
avoids a panic.
Module Name:src
Committed By: gutteridge
Date: Tue Nov 21 23:22:23 UTC 2023
Modified Files:
src/sys/arch/x86/pci: pci_machdep.c pci_msi_machdep.c
Log Message:
pci_machdep.c & pci_msi_machdep.c: comment fixes
Correct spelling and grammar in some comments.
To generate a d
Module Name:src
Committed By: gutteridge
Date: Tue Nov 21 23:22:23 UTC 2023
Modified Files:
src/sys/arch/x86/pci: pci_machdep.c pci_msi_machdep.c
Log Message:
pci_machdep.c & pci_msi_machdep.c: comment fixes
Correct spelling and grammar in some comments.
To generate a d
Module Name:src
Committed By: mrg
Date: Fri Oct 27 06:31:49 UTC 2023
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
add MSR stuff for AMD errata 1474.
To generate a diff of this commit:
cvs rdiff -u -r1.208 -r1.209 src/sys/arch/x86/include/specialreg
Module Name:src
Committed By: mrg
Date: Fri Oct 27 06:31:49 UTC 2023
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
add MSR stuff for AMD errata 1474.
To generate a diff of this commit:
cvs rdiff -u -r1.208 -r1.209 src/sys/arch/x86/include/specialreg
Module Name:src
Committed By: mrg
Date: Fri Oct 27 05:45:00 UTC 2023
Modified Files:
src/sys/arch/x86/x86: errata.c
Log Message:
x86: handle AMD errata 1474: A CPU core may hang after about 1044 days
from the new comment:
* This requires disabling CC6 power level, which
Module Name:src
Committed By: mrg
Date: Fri Oct 27 05:45:00 UTC 2023
Modified Files:
src/sys/arch/x86/x86: errata.c
Log Message:
x86: handle AMD errata 1474: A CPU core may hang after about 1044 days
from the new comment:
* This requires disabling CC6 power level, which
Module Name:src
Committed By: mrg
Date: Fri Oct 27 03:06:04 UTC 2023
Modified Files:
src/sys/arch/x86/x86: errata.c
Log Message:
x86: add names for errata that don't have actual numbers
zenbleed is reported as "erratum 65535" currently, this adds a name
for it, and enable
Module Name:src
Committed By: mrg
Date: Fri Oct 27 03:06:04 UTC 2023
Modified Files:
src/sys/arch/x86/x86: errata.c
Log Message:
x86: add names for errata that don't have actual numbers
zenbleed is reported as "erratum 65535" currently, this adds a name
for it, and enable
Module Name:src
Committed By: bouyer
Date: Thu Oct 19 14:59:46 UTC 2023
Modified Files:
src/sys/arch/x86/acpi: acpi_wakeup.c
src/sys/arch/x86/x86: genfb_machdep.c
Log Message:
Move definition of acpi_md_vesa_modenum to acpi_wakeup.c; allows building
kernels without
Module Name:src
Committed By: bouyer
Date: Thu Oct 19 14:59:46 UTC 2023
Modified Files:
src/sys/arch/x86/acpi: acpi_wakeup.c
src/sys/arch/x86/x86: genfb_machdep.c
Log Message:
Move definition of acpi_md_vesa_modenum to acpi_wakeup.c; allows building
kernels without
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