Module Name:src
Committed By: simonb
Date: Tue Nov 8 13:47:09 UTC 2022
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
Parentheses police.
To generate a diff of this commit:
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/riscv/include/sysreg.h
Please note th
Module Name:src
Committed By: simonb
Date: Tue Nov 8 13:47:09 UTC 2022
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
Parentheses police.
To generate a diff of this commit:
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/riscv/include/sysreg.h
Please note th
Module Name:src
Committed By: simonb
Date: Tue Nov 8 13:35:32 UTC 2022
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
Add cause register trap types, and some macros to access cause register
fields.
To generate a diff of this commit:
cvs rdiff -u -r1.1
Module Name:src
Committed By: simonb
Date: Tue Nov 8 13:35:32 UTC 2022
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
Add cause register trap types, and some macros to access cause register
fields.
To generate a diff of this commit:
cvs rdiff -u -r1.1
Module Name:src
Committed By: simonb
Date: Tue Nov 8 13:34:18 UTC 2022
Modified Files:
src/sys/arch/riscv/include: types.h
Log Message:
Add a #define for XLEN, the RISC-V native base integer ISA width.
To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.15 src/sy
Module Name:src
Committed By: simonb
Date: Tue Nov 8 13:34:18 UTC 2022
Modified Files:
src/sys/arch/riscv/include: types.h
Log Message:
Add a #define for XLEN, the RISC-V native base integer ISA width.
To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.15 src/sy
Module Name:src
Committed By: simonb
Date: Tue Nov 8 13:04:49 UTC 2022
Modified Files:
src/sys/arch/mips/include: mipsNN.h
Log Message:
Fix tyop in __BITS for the MIPSNN_MTI_CFG7_PREF_MASK macro.
To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/sys/arch
Module Name:src
Committed By: simonb
Date: Tue Nov 8 13:04:49 UTC 2022
Modified Files:
src/sys/arch/mips/include: mipsNN.h
Log Message:
Fix tyop in __BITS for the MIPSNN_MTI_CFG7_PREF_MASK macro.
To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/sys/arch
Module Name:src
Committed By: skrll
Date: Tue Nov 8 12:48:28 UTC 2022
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
whitepsace nit
To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/riscv/include/sysreg.h
Please note that dif
Module Name:src
Committed By: skrll
Date: Tue Nov 8 12:48:28 UTC 2022
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
whitepsace nit
To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/riscv/include/sysreg.h
Please note that dif
Module Name:src
Committed By: nia
Date: Tue Nov 8 09:30:11 UTC 2022
Modified Files:
src/doc: CHANGES
Log Message:
doc: various changes from various developers for late october
To generate a diff of this commit:
cvs rdiff -u -r1.2928 -r1.2929 src/doc/CHANGES
Please note
Module Name:src
Committed By: nia
Date: Tue Nov 8 09:30:11 UTC 2022
Modified Files:
src/doc: CHANGES
Log Message:
doc: various changes from various developers for late october
To generate a diff of this commit:
cvs rdiff -u -r1.2928 -r1.2929 src/doc/CHANGES
Please note
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