CVS commit: src/sys/arch/arm/footbridge

Module Name:src Committed By: skrll Date: Fri Aug 13 11:40:43 UTC 2021 Modified Files: src/sys/arch/arm/footbridge: footbridge.c footbridge_clock.c footbridge_com.c footbridge_com_io.c footbridge_intr.h footbridge_io.c footbridge_irqhandler.c footbri

CVS commit: src

Module Name:src Committed By: andvar Date: Fri Aug 13 20:19:14 UTC 2021 Modified Files: src/tests/sys/uvm: t_uvm_physseg.c src/usr.sbin/syslogd: syslogd.c Log Message: s/bacause/because/ To generate a diff of this commit: cvs rdiff -u -r1.8 -r1.9 src/tests/sys/uv

CVS commit: src/sys/arch/alpha/alpha

Module Name:src Committed By: andvar Date: Fri Aug 13 20:19:45 UTC 2021 Modified Files: src/sys/arch/alpha/alpha: pmap.c Log Message: fix multiple typos in comments. To generate a diff of this commit: cvs rdiff -u -r1.300 -r1.301 src/sys/arch/alpha/alpha/pmap.c Please n

CVS commit: src/sys

Module Name:src Committed By: andvar Date: Fri Aug 13 20:26:07 UTC 2021 Modified Files: src/sys/arch/amd64/amd64: locore.S src/sys/arch/i386/i386: locore.S src/sys/dev/marvell: mvxpsec.c src/sys/dev/pci: if_bnx.c Log Message: s/struture/structure/ s

CVS commit: src

Module Name:src Committed By: andvar Date: Fri Aug 13 20:47:55 UTC 2021 Modified Files: src/common/lib/libc/arch/sparc64/string: memset.S src/sbin/ifconfig: ieee80211.c src/sys/arch/mips/ralink: ralink_reg.h src/sys/arch/powerpc/include: reg.h

CVS commit: src/sys/dev/marvell

Module Name:src Committed By: andvar Date: Fri Aug 13 21:04:44 UTC 2021 Modified Files: src/sys/dev/marvell: if_mvxpe.c Log Message: s/fame/frame in mvxpe_mib_def with assumption that it was not intentional typo. To generate a diff of this commit: cvs rdiff -u -r1.34 -r1