On Fri, 18 Apr 2014, Georg Icking-Konert wrote:
> Hello Maarten,
>
> so far I observed it only for the ADC result register (ADC_DR) for read,
> and timer 3 compare register (TIM3_CCR) for write. The way I realized
> was simple: the ADC the result was skewed, and the TIM3 period was
> wrong. How
hello again,
here some details:
ADC_DR read:
- procedure: toggle GPIO, wait 1ms, measure ADC at connected GPIO, display IO
state and ADC result on LCD
- code snipped (correct order);
uint16_t a,b, result;
a = (uint16_t) (ADC_DR.bytel);
b = ((uint16_t) (ADC_DR.byteh)) << 8;
Hello Maarten,
so far I observed it only for the ADC result register (ADC_DR) for read, and
timer 3 compare register (TIM3_CCR) for write. The way I realized was simple:
the ADC the result was skewed, and the TIM3 period was wrong. However, I didn’t
dig deeper after I found out that changing th
