Pass RISCVCPUConfig as disassemble_info.target_info to support disas
of conflict instructions related to specific extensions.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
---
disas/riscv.c | 10 +++---
target/riscv/cpu.c | 1 +
2 files
Support disas for Z*inx instructions only when Zfinx extension is supported.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
---
disas/riscv.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/disas/riscv.c b/disas
Use pointer to pass more information of target to disasembler,
such as pass cpu.cfg related information in following commits.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
---
include/disas/dis-asm.h | 2 +-
1 file changed, 1 insertion(+), 1
Barboza)
Weiwei Li (8):
disas: Change type of disassemble_info.target_info to pointer
target/riscv: Split RISCVCPUConfig declarations from cpu.h into
cpu_cfg.h
target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info
disas/riscv.c: Support disas for Zcm* extensions
disas
Remove redundant parenthese and fix multi-line comments.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
---
disas/riscv.c | 219 +-
1 file changed, 110 insertions(+), 109 deletions(-)
diff --git a
Split RISCVCPUConfig declarations to prepare for passing it to disas.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu.h | 114 +-
target/riscv/cpu_cfg.h | 136 +
2 files changed, 137
Currently decomp_rv32 and decomp_rv64 value in opcode_data for vector
instructions are the same op index as their own. And they have no
functional decomp_data. So they have no functional difference from just
leaving them as zero.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by
current pc if exception is triggered.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvi.c.inc | 23 ---
target/riscv/insn_trans/trans_rvzce.c.inc | 4 ++--
target/riscv
Reduce reliance on absolute values by using true pc difference for
gen_pc_plus_diff() to prepare for PC-relative translation.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/insn_trans/trans_rvi.c.inc | 6 ++
target/riscv/insn_trans/trans_rvzce.c.inc | 2
pc_succ_insn is no longer useful after the introduce of cur_insn_len
and all pc related value use diff value instead of absolute value.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/translate.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a
Add a base pc_save for PC-relative translation(CF_PCREL).
Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb.
Use gen_pc_plus_diff to get the pc-relative address.
Enable CF_PCREL in System mode.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu.c
Reduce reliance on absolute values(by passing pc difference) to
prepare for PC-relative translation.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/insn_trans/trans_privileged.c.inc | 2 +-
target/riscv/insn_trans/trans_rvi.c.inc| 6 +++---
target/riscv
Reduce reliance on absolute value to prepare for PC-relative translation.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/insn_trans/trans_rvi.c.inc | 4 ++--
target/riscv/translate.c| 8 +---
2 files changed, 7 insertions(+), 5 deletions(-)
diff
Use cur_insn_len to store the length of the current instruction to
prepare for PC-relative translation.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/translate.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/riscv/translate.c b/target
And support of PC-relative translation is the precondition to support
pointer mask for instruction.
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-pcrel-upstream-v2
v2:
* rebase on upstream and add pc-relative translation for Zc* instructions
Weiwei Li (7):
target/
riscv_refresh_dynamic_csr_xml().
Regards,
Weiwei Li
char *dyn_csr_xml;
char *dyn_vreg_xml;
@@ -781,6 +782,7 @@ void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
void riscv_cpu_register_gdb_regs_for_features
cpu);
+
There is an assert in riscv_refresh_dynamic_csr_xml():
+if (!cpu->dyn_csr_xml) {
+g_assert_not_reached();
+}
So I think riscv_refresh_dynamic_csr_xml() can only be called when
cpu->dyn_csr_xml is true here.
Regards,
Weiwei Li
riscv_cpu_set_aia_ireg_rmw_fn(en
(patch 3~6) out of this patchset
Weiwei Li (2):
target/riscv: Fix pointer mask transformation for vector address
target/riscv: Update cur_pmmask/base when xl changes
target/riscv/csr.c | 9 -
target/riscv/vector_helper.c | 2 +-
2 files changed, 9 insertions(+), 2 deletions
actual_address = (requested_address & ~mpmmask) | mpmbase.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: LIU Zhiwei
---
target/riscv/vector_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/r
write_mstatus() can only change current xl when in debug mode.
And we need update cur_pmmask/base in this case.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: LIU Zhiwei
---
target/riscv/csr.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a
On 2023/5/24 09:59, Tommy Wu wrote:
Hi Weiwei Li,
`dyn_csr_base_reg` will be used in `riscv_refresh_dynamic_csr_xml`
We can initialize this variable when the cpu is realized.
I didn't find this initialization in following code.
And used this variable in `riscv_refresh_dynamic_cs
On 2023/5/24 09:51, Tommy Wu wrote:
Hi Weiwei Li,
Yes, you're right, `riscv_refresh_dynamic_csr_xml()` can only be
called when
cpu->dyn_csr_xml isn't a NULL pointer here.
The cpu->dyn_csr_xml will be set when the cpu is realized.
Yeah, It will be set only when Zicsr is
On 2023/5/24 13:35, Tommy Wu wrote:
Hi WeiWei Li,
When the CPU is realizing, it will call `riscv_gen_dynamic_csr_xml`
for the first time with the correct `base_reg` value.
code flow :
riscv_cpu_realize
→ riscv_cpu_register_gdb_regs_for_features
→ riscv_gen_dynamic_csr_xml
The
pc_succ_insn is no longer useful after the introduce of cur_insn_len
and all pc related value use diff value instead of absolute value.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/translate.c | 7
Reduce reliance on absolute value to prepare for PC-relative translation.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvi.c.inc | 4 ++--
target/riscv/translate.c| 8
current pc if exception is triggered.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvi.c.inc | 23 ---
target/riscv/insn_trans/trans_rvzce.c.inc | 4 ++--
target/riscv
Reduce reliance on absolute values by using true pc difference for
gen_pc_plus_diff() to prepare for PC-relative translation.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvi.c.inc | 6
Add a base pc_save for PC-relative translation(CF_PCREL).
Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb.
Use gen_pc_plus_diff to get the pc-relative address.
Enable CF_PCREL in System mode.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard
Use cur_insn_len to store the length of the current instruction to
prepare for PC-relative translation.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/translate.c | 4 +++-
1 file changed, 3 insertions(+), 1
or Zc* instructions
Weiwei Li (7):
target/riscv: Fix target address to update badaddr
target/riscv: Introduce cur_insn_len into DisasContext
target/riscv: Change gen_goto_tb to work on displacements
target/riscv: Change gen_set_pc_imm to gen_update_pc
target/riscv: Use true diff for gen_pc_plus
Reduce reliance on absolute values(by passing pc difference) to
prepare for PC-relative translation.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_privileged.c.inc | 2 +-
target/riscv
MPV and GVA bits are added by hypervisor extension to mstatus
and mstatush (if MXLEN=32).
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/csr.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index
This patchset tries to fix some problems in the fields of mstatus, such as make
MPV only work when MPP != PRM.
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-mpv-upstream
Weiwei Li (4):
target/riscv: Make MPV only work when MPP != PRV_M
target/riscv: Remove check
Upon MRET or explicit memory access with MPRV=1, MPV should be ignored
when MPP=PRV_M.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu_helper.c | 3 ++-
target/riscv/op_helper.c | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/riscv
SXL is initialized as env->misa_mxl which is also the mxl value.
So we can just remain it unchanged to keep it read-only.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/csr.c | 4
1 file changed, 4 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/cs
Normally, MPRV can be set to 1 only in M mode (It will be cleared
when returning to lower-privilege mode by MRET/SRET).
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv
Use CPURISCVState as argument directly in riscv_cpu_update_mip and
riscv_timer_write_timecmp, since type converts from CPURISCVState to
RISCVCPU in many caller of them and then back to CPURISCVState in them.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu.c
Use env_archcpu() to get RISCVCPU pointer from env directly.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/pmu.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
index b8e56d2b7b..a200741083 100644
Use riscv_cpu_cfg(env) instead of env_archcpu().cfg.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu_helper.c | 9 -
target/riscv/csr.c| 40 ---
target/riscv/gdbstub.c| 4 ++--
3 files changed, 18 insertions
Remove RISCVCPU argument, and get cfg infomation from CPURISCVState
directly.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/csr.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 53143f4d9a
riscv_csrrw_check, and get cfg infomation from
CPURISCVState directly
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-cleanup-upstream
Weiwei Li (4):
target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig
target/riscv: Simplify getting RISCVCPU pointer from env
- add xperm4 and xperm8 instructions
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/bitmanip_helper.c | 27 +
target/riscv/helper.h | 2 ++
target/riscv/insn32.decode | 4
target/riscv/insn_trans
- add sha512sum0r, sha512sig0l, sha512sum1r, sha512sig1l, sha512sig0h and
sha512sig1h instructions
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/crypto_helper.c| 57
target/riscv/helper.h | 7
v2:
* optimize implementation for brev8, xperm, zip, unzip
* use aes related sbox array from crypto/aes.h
* move sm4_sbox to crypto/sm4.c, and share it with target/arm
Weiwei Li (14):
target/riscv: rvk: add cfg properties for zbk* and zk*
target/riscv: rvk: add support for zbkb extension
targ
- reuse partial instructions of zbc extension, update extension check for them
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
---
target/riscv/insn32.decode | 3 ++-
target/riscv/insn_trans/trans_rvb.c.inc | 4 ++--
2 files changed, 4
- add sha256sig0, sha256sig1, sha256sum0 and sha256sum1 instructions
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/crypto_helper.c| 31 +
target/riscv/helper.h | 5 +++
target/riscv/insn32.decode
- add aes64dsm, aes64ds, aes64im, aes64es, aes64esm, aes64ks2, aes64ks1i
instructions
Co-authored-by: Ruibo Lu
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/crypto_helper.c| 136
target/riscv/helper.h
- share it between target/arm and target/riscv
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
---
crypto/meson.build | 1 +
crypto/sm4.c | 49 ++
include
- add aes32esmi, aes32esi, aes32dsmi and aes32dsi instructions
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/crypto_helper.c| 139
target/riscv/helper.h | 6 +
target/riscv/insn32
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Acked-by: Alistair Francis
---
target/riscv/cpu.c | 23 +++
target/riscv/cpu.h | 13 +
2 files changed, 36 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b0a40b83e7..d30534ead5
- add sm3p0, sm3p1, sm4ed and sm4ks instructions
Co-authored-by: Ruibo Lu
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/crypto_helper.c| 49 +
target/riscv/helper.h | 6 +++
target/riscv/insn32.decode | 6
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d30534ead5..64bc776072 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv
Co-authored-by: Ruibo Lu
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
disas/riscv.c | 170 ++
1 file changed, 170 insertions(+)
diff --git a/disas/riscv.c b/disas/riscv.c
index 03c8dc9961..44a2c16a0b 100644
- reuse partial instructions of zbb extension, update extension check for them
- add brev8, pack, packh, packw, unzip, zip instructions
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Acked-by: Alistair Francis
---
target/riscv/bitmanip_helper.c | 53 +++
target
- add sha512sum0, sha512sig0, sha512sum1 and sha512sig1 instructions
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/crypto_helper.c| 31 ++
target/riscv/helper.h | 5 +++
target/riscv/insn32.decode
- add SEED CSR
- add USEED, SSEED fields for MSECCFG CSR
Co-authored-by: Ruibo Lu
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu_bits.h | 9 ++
target/riscv/csr.c | 64 +
target/riscv
Thanks for your comments.
在 2022/2/28 上午2:47, Richard Henderson 写道:
On 2/27/22 04:25, Weiwei Li wrote:
+static void gen_packh(TCGv ret, TCGv src1, TCGv src2)
+{
+ TCGv t = tcg_temp_new();
+
+ tcg_gen_ext8u_tl(t, src2);
+ tcg_gen_deposit_tl(ret, src1, t, 8, TARGET_LONG_BITS - 8
在 2022/2/28 上午3:05, Richard Henderson 写道:
On 2/27/22 04:25, Weiwei Li wrote:
+#define AES_SHIFROWS_LO(RS1, RS2) ( \
+ (((RS1 >> 24) & 0xFF) << 56) | (((RS2 >> 48) & 0xFF) << 48) | \
+ (((RS2 >> 8) & 0xFF) << 40) | (((RS1 >> 3
在 2022/2/28 上午3:13, Richard Henderson 写道:
On 2/27/22 04:25, Weiwei Li wrote:
- add aes64dsm, aes64ds, aes64im, aes64es, aes64esm, aes64ks2,
aes64ks1i instructions
Co-authored-by: Ruibo Lu
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv
在 2022/2/28 上午3:21, Richard Henderson 写道:
On 2/27/22 04:25, Weiwei Li wrote:
- add sha256sig0, sha256sig1, sha256sum0 and sha256sum1 instructions
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/crypto_helper.c | 31
在 2022/2/28 上午3:36, Richard Henderson 写道:
On 2/27/22 04:25, Weiwei Li wrote:
- add sha512sum0r, sha512sig0l, sha512sum1r, sha512sig1l,
sha512sig0h and sha512sig1h instructions
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv
在 2022/2/28 上午3:41, Richard Henderson 写道:
On 2/27/22 04:25, Weiwei Li wrote:
- add sm3p0, sm3p1, sm4ed and sm4ks instructions
Co-authored-by: Ruibo Lu
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/crypto_helper.c | 49 +
target
- reuse partial instructions of zbc extension, update extension check for them
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
---
target/riscv/insn32.decode | 3 ++-
target/riscv/insn_trans/trans_rvb.c.inc | 4 ++--
2 files changed, 4
v4:
* drop "x-" in exposed properties
* delete unrelated changes
v3:
* add extension check for SEED csr access
v2:
* optimize implementation for brev8, xperm, zip, unzip
* use aes related sbox array from crypto/aes.h
* move sm4_sbox to crypto/sm4.c, and share it with target/arm
Weiwei L
- add sha256sig0, sha256sig1, sha256sum0 and sha256sum1 instructions
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/insn32.decode | 5
target/riscv/insn_trans/trans_rvk.c.inc | 37 +
2 files changed
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Acked-by: Alistair Francis
---
target/riscv/cpu.c | 23 +++
target/riscv/cpu.h | 13 +
2 files changed, 36 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ddda4906ff..9e8bbce6f1
- reuse partial instructions of zbb extension, update extension check for them
- add brev8, pack, packh, packw, unzip, zip instructions
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Acked-by: Alistair Francis
---
target/riscv/bitmanip_helper.c | 53 ++
target
- add aes32esmi, aes32esi, aes32dsmi and aes32dsi instructions
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/crypto_helper.c| 105
target/riscv/helper.h | 6 ++
target/riscv/insn32
- add sha512sum0r, sha512sig0l, sha512sum1r, sha512sig1l, sha512sig0h and
sha512sig1h instructions
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/insn32.decode | 6 +++
target/riscv/insn_trans/trans_rvk.c.inc | 63
- add aes64dsm, aes64ds, aes64im, aes64es, aes64esm, aes64ks2, aes64ks1i
instructions
Co-authored-by: Ruibo Lu
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/crypto_helper.c| 169
target/riscv/helper.h
- share it between target/arm and target/riscv
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
crypto/meson.build | 1 +
crypto/sm4.c | 49
- add xperm4 and xperm8 instructions
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
---
target/riscv/bitmanip_helper.c | 27 +
target/riscv/helper.h | 2 ++
target/riscv/insn32.decode | 4
- add sha512sum0, sha512sig0, sha512sum1 and sha512sig1 instructions
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/insn32.decode | 5
target/riscv/insn_trans/trans_rvk.c.inc | 32 +
2 files changed
Co-authored-by: Ruibo Lu
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
disas/riscv.c | 170 ++
1 file changed, 170 insertions(+)
diff --git a/disas/riscv.c b/disas/riscv.c
index 03c8dc9961..44a2c16a0b 100644
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9e8bbce6f1..11a35fb5d6 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv
- add SEED CSR
- add USEED, SSEED fields for MSECCFG CSR
Co-authored-by: Ruibo Lu
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu_bits.h | 9 ++
target/riscv/csr.c | 64 +
target/riscv
- add sm3p0, sm3p1, sm4ed and sm4ks instructions
Co-authored-by: Ruibo Lu
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/crypto_helper.c| 28
target/riscv/helper.h | 3 ++
target/riscv/insn32.decode | 6
在 2022/3/1 上午3:38, Richard Henderson 写道:
On 2/28/22 04:48, Weiwei Li wrote:
+#define GEN_SHA512H_RV32(NAME, OP, NUM1, NUM2, NUM3) \
+static void gen_##NAME(TCGv dest, TCGv src1, TCGv src2) \
+{ \
+ TCGv_i64 t0 = tcg_temp_new_i64(); \
+ TCGv_i64 t1 = tcg_temp_new_i64(); \
+ TCGv_i64
在 2022/3/1 上午4:11, Richard Henderson 写道:
On 2/28/22 04:48, Weiwei Li wrote:
+/* Crypto Extension */
+static RISCVException rmw_seed(CPURISCVState *env, int csrno,
+ target_ulong *ret_value,
+ target_ulong new_value, target_ulong
在 2022/3/1 上午9:44, Weiwei Li 写道:
在 2022/3/1 上午4:11, Richard Henderson 写道:
On 2/28/22 04:48, Weiwei Li wrote:
+/* Crypto Extension */
+static RISCVException rmw_seed(CPURISCVState *env, int csrno,
+ target_ulong *ret_value
- add aes64dsm, aes64ds, aes64im, aes64es, aes64esm, aes64ks2, aes64ks1i
instructions
Co-authored-by: Ruibo Lu
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
---
target/riscv/crypto_helper.c| 169
- reuse partial instructions of zbc extension, update extension check for them
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 3 ++-
target/riscv/insn_trans/trans_rvb.c.inc | 4
- add sha512sum0r, sha512sig0l, sha512sum1r, sha512sig1l, sha512sig0h and
sha512sig1h instructions
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvk.c.inc | 100
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Acked-by: Alistair Francis
---
target/riscv/cpu.c | 23 +++
target/riscv/cpu.h | 13 +
2 files changed, 36 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ddda4906ff..9e8bbce6f1
- add xperm4 and xperm8 instructions
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
---
target/riscv/bitmanip_helper.c | 27 +
target/riscv/helper.h | 2 ++
target/riscv/insn32.decode | 4
- add aes32esmi, aes32esi, aes32dsmi and aes32dsi instructions
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
---
target/riscv/crypto_helper.c| 105
target/riscv/helper.h
- reuse partial instructions of zbb extension, update extension check for them
- add brev8, pack, packh, packw, unzip, zip instructions
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/bitmanip_helper.c
- add sha256sig0, sha256sig1, sha256sum0 and sha256sum1 instructions
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 5 +++
target/riscv/insn_trans/trans_rvk.c.inc | 55
ip
* use aes related sbox array from crypto/aes.h
* move sm4_sbox to crypto/sm4.c, and share it with target/arm
Weiwei Li (14):
target/riscv: rvk: add cfg properties for zbk* and zk*
target/riscv: rvk: add support for zbkb extension
target/riscv: rvk: add support for zbkc extension
target/riscv:
- share it between target/arm and target/riscv
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
crypto/meson.build | 1 +
crypto/sm4.c | 49
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9e8bbce6f1..11a35fb5d6 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv
- add SEED CSR
- add USEED, SSEED fields for MSECCFG CSR
Co-authored-by: Ruibo Lu
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu_bits.h | 9 ++
target/riscv/csr.c | 71 +
target/riscv
- add sm3p0, sm3p1, sm4ed and sm4ks instructions
Co-authored-by: Ruibo Lu
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
---
target/riscv/crypto_helper.c| 28
target/riscv/helper.h | 3 ++
target/riscv/insn32
Co-authored-by: Ruibo Lu
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
disas/riscv.c | 170 ++
1 file changed, 170 insertions(+)
diff --git a/disas/riscv.c b/disas/riscv.c
index 03c8dc9961..44a2c16a0b 100644
- add sha512sum0, sha512sig0, sha512sum1 and sha512sig1 instructions
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 5 +++
target/riscv/insn_trans/trans_rvk.c.inc | 53
在 2022/3/1 下午11:59, Richard Henderson 写道:
On 2/28/22 16:27, Weiwei Li wrote:
在 2022/3/1 上午9:44, Weiwei Li 写道:
在 2022/3/1 上午4:11, Richard Henderson 写道:
On 2/28/22 04:48, Weiwei Li wrote:
+/* Crypto Extension */
+static RISCVException rmw_seed(CPURISCVState *env, int csrno
For csrrs and csrrc, if rs1 specifies a register other than x0, holding
a zero value, the instruction will still attempt to write the unmodified
value back to the csr and will cause side effects
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/csr.c
在 2022/1/28 下午2:09, Alistair Francis 写道:
On Thu, Jan 13, 2022 at 11:52 AM Weiwei Li wrote:
- update extension check REQUIRE_ZFINX_OR_F
- update single float point register read/write
- disable nanbox_s check
Co-authored-by: ardxwe
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang
在 2022/1/28 下午1:40, Alistair Francis 写道:
On Tue, Jan 25, 2022 at 5:47 PM Weiwei Li wrote:
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Anup Patel
Could you please add a commit message to this patch?
Alistair
OK. I'll add it.
Regards,
Weiwei Li
---
t
- add PTE_N bit
- add PTE_N bit check for inner PTE
- update address translation to support 64KiB continuous region (napot_bits = 4)
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Anup Patel
---
target/riscv/cpu.c| 2 ++
target/riscv/cpu_bits.h | 1 +
target
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