[PATCH v6 4/9] target/riscv: add support for Zcd extension

Separate c_fld/c_fsd from fld/fsd to add additional check for c.fld{sp}/c.fsd{sp} which is useful for zcmp/zcmt to reuse their encodings Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn16.decode

[PATCH v6 5/9] target/riscv: add support for Zcb extension

Add encode and trans* functions support for Zcb instructions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn16.decode| 24 ++ target/riscv/insn_trans/trans_rvzce.c.inc | 100

[PATCH v7 1/9] target/riscv: add cfg properties for Zc* extension

Add properties for Zca,Zcb,Zcf,Zcd,Zcmp,Zcmt extension Add check for these properties Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 43 +++ target/riscv/cpu.h

[PATCH v7 5/9] target/riscv: add support for Zcb extension

Add encode and trans* functions support for Zcb instructions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn16.decode| 24 ++ target/riscv/insn_trans/trans_rvzce.c.inc | 100

[PATCH v7 0/9] support subsets of code size reduction extension

fsd{sp} before support of zcmp/zcmt Weiwei Li (9): target/riscv: add cfg properties for Zc* extension target/riscv: add support for Zca extension target/riscv: add support for Zcf extension target/riscv: add support for Zcd extension target/riscv: add support for Zcb extension targ

[PATCH v7 2/9] target/riscv: add support for Zca extension

Modify the check for C extension to Zca (C implies Zca) Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Wilfred Mallawa --- target/riscv/insn_trans/trans_rvi.c.inc | 4 ++-- target/riscv/translate.c

[PATCH v7 6/9] target/riscv: add support for Zcmp extension

Add encode, trans* functions for Zcmp instructions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn16.decode| 18 +++ target/riscv/insn_trans/trans_rvzce.c.inc | 189

[PATCH v7 8/9] target/riscv: expose properties for Zc* extension

Expose zca,zcb,zcf,zcd,zcmp,zcmt properties Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 13 + 1 file changed, 13 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3d06b57416..5f03698b3b 100644

[PATCH v7 3/9] target/riscv: add support for Zcf extension

Separate c_flw/c_fsw from flw/fsw to add check for Zcf extension Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn16.decode | 8 target/riscv/insn_trans/trans_rvf.c.inc | 18

[PATCH v7 4/9] target/riscv: add support for Zcd extension

Separate c_fld/c_fsd from fld/fsd to add additional check for c.fld{sp}/c.fsd{sp} which is useful for zcmp/zcmt to reuse their encodings Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn16.decode

[PATCH v7 7/9] target/riscv: add support for Zcmt extension

Add encode, trans* functions and helper functions support for Zcmt instrutions Add support for jvt csr Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 4 ++ target/riscv

[PATCH v7 9/9] disas/riscv.c: add disasm support for Zc*

Zcmp/Zcmt instructions will override disasm for c.fld*/c.fsd* instructions currently Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Acked-by: Alistair Francis --- disas/riscv.c | 287 +- 1 file changed, 286 insertions(+), 1 deletion

[PATCH v8 5/9] target/riscv: add support for Zcb extension

Add encode and trans* functions support for Zcb instructions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn16.decode| 24 ++ target/riscv/insn_trans/trans_rvzce.c.inc | 100

[PATCH v8 4/9] target/riscv: add support for Zcd extension

Separate c_fld/c_fsd from fld/fsd to add additional check for c.fld{sp}/c.fsd{sp} which is useful for zcmp/zcmt to reuse their encodings Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn16.decode

[PATCH v8 0/9] support subsets of code size reduction extension

eparate c.fld{sp}/fsd{sp} with fld{sp}/fsd{sp} before support of zcmp/zcmt Weiwei Li (9): target/riscv: add cfg properties for Zc* extension target/riscv: add support for Zca extension target/riscv: add support for Zcf extension target/riscv: add support for Zcd extension target/riscv:

[PATCH v8 2/9] target/riscv: add support for Zca extension

Modify the check for C extension to Zca (C implies Zca) Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Wilfred Mallawa --- target/riscv/insn_trans/trans_rvi.c.inc | 4 ++-- target/riscv/translate.c

[PATCH v8 3/9] target/riscv: add support for Zcf extension

Separate c_flw/c_fsw from flw/fsw to add check for Zcf extension Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn16.decode | 8 target/riscv/insn_trans/trans_rvf.c.inc | 18

[PATCH v8 9/9] disas/riscv.c: add disasm support for Zc*

Zcmp/Zcmt instructions will override disasm for c.fld*/c.fsd* instructions currently Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Acked-by: Alistair Francis --- disas/riscv.c | 228 +- 1 file changed, 227 insertions(+), 1 deletion

[PATCH v8 1/9] target/riscv: add cfg properties for Zc* extension

Add properties for Zca,Zcb,Zcf,Zcd,Zcmp,Zcmt extension Add check for these properties Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 43 +++ target/riscv/cpu.h

[PATCH v8 7/9] target/riscv: add support for Zcmt extension

Add encode, trans* functions and helper functions support for Zcmt instrutions Add support for jvt csr Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 4 ++ target/riscv

[PATCH v8 6/9] target/riscv: add support for Zcmp extension

Add encode, trans* functions for Zcmp instructions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn16.decode| 18 +++ target/riscv/insn_trans/trans_rvzce.c.inc | 189

[PATCH v8 8/9] target/riscv: expose properties for Zc* extension

Expose zca,zcb,zcf,zcd,zcmp,zcmt properties Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 13 + 1 file changed, 13 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3d06b57416..5f03698b3b 100644

Re: [PATCH v6 1/5] target/riscv: Add smstateen support

.min_priv_ver = PRIV_VERSION_1_12_0 }, +/* Smstateen extension CSRs */ +[CSR_MSTATEEN0] = { "mstateen0", mstateen, read_mstateen, write_mstateen0, + .min_priv_ver = PRIV_VERSION_1_12_0 }, The new lines have been upd

Re: [PATCH v6 2/5] target/riscv: smstateen check for h/senvcfg

his check into the predicate. By the way, sharing the same function for all related csrs  is easily misunderstood. However, It seems correct. Regards, Weiwei Li +if (ret != RISCV_EXCP_NONE) { +return ret; +} + *val = env->senvcfg; return RISCV_EXCP_NONE; } @@

Re: [PATCH v6 3/5] target/riscv: smstateen check for fcsr

turn false; \ +} \ } \ } while (0) SMSTATEEN_CHECK is for CSR. and REQUIRE_ZFINX_OR_F is for Extension. I think It's better to separate them. By the way, if we want the smallest modification for current code, adding it to REQUIRE_FPU seems better. Regards, Weiwei Li diff --git a/

Re: [PATCH v6 4/5] target/riscv: smstateen check for AIA/IMSIC

tting hstateen0 bit 58 to zero prevents a virtual machine from accessing the hart’s IMSIC the same as setting hstatus.VGEIN = 0" I think  it means "setting hstateen0 bit 58 to zero" and "setting hstatus.VGEIN = 0" have the same function:  " prevents a virtua

Re: [PATCH v6 5/5] target/riscv: smstateen knobs

PROP_BOOL("smstateen", RISCVCPU, cfg.ext_smstateen, false), DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), Reviewed-by: Weiwei Li Regards, Weiwei Li

Re: [PATCH v6 1/5] target/riscv: Add smstateen support

在 2022/7/24 下午11:39, Mayuresh Chitale 写道: On Fri, 2022-07-22 at 08:31 +0800, Weiwei Li wrote: 在 2022/7/21 下午11:31, Mayuresh Chitale 写道: Smstateen extension specifies a mechanism to close the potential covert channels that could cause security issues. This patch adds the CSRs defined in the

Re: [PATCH v6 3/5] target/riscv: smstateen check for fcsr

在 2022/7/24 下午11:49, Mayuresh Chitale 写道: On Fri, 2022-07-22 at 09:42 +0800, Weiwei Li wrote: 在 2022/7/21 下午11:31, Mayuresh Chitale 写道: If smstateen is implemented and sstateen0.fcsr is clear then the floating point operations must return illegal instruction exception. Signed-off-by

Re: [PATCH] target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3~31{h}

在 2022/7/27 上午7:34, Atish Patra 写道: On Wed, Jul 20, 2022 at 9:32 PM Alistair Francis wrote: On Sat, Jul 2, 2022 at 11:42 PM Weiwei Li wrote: - improve the field extract progress This part is already improved with the PMU series. https://www.mail-archive.com/qemu-devel@nongnu.org

Re: [PATCH v11 1/6] target/riscv: Add sscofpmf extension support

T31]= { "mhpmevent31",any, read_mhpmevent, write_mhpmevent }, +[CSR_MHPMEVENT3H]= { "mhpmevent3h",sscofpmf, read_mhpmeventh, +

Re: [PATCH v11 6/6] target/riscv: Remove additional priv version check for mcountinhibit

ycles/instructions */ Reviewed-by: Weiwei Li Regards, Weiwei Li

Re: [PATCH v11 5/6] target/riscv: Update the privilege field for sscofpmf CSRs

mhpmeventh, + .min_priv_ver = PRIV_VERSION_1_12_0 }, Similar to the first commit, it's better to align with the first element "mhpmevent3h" .Otherwise, Reviewed-by: Weiwei Li Regards, Weiwei Li [CSR_MHPMEVENT4H]= { "mhpmevent4h&q

Re: [PATCH v11 2/6] target/riscv: Simplify counter predicate function

ed here. In original logic, RISCV_EXCP_VIRT_INSTRUCTION_FAULT is triggered when !get_field(env->hcounteren, 1 << ctr_index) && get_field(env->mcounteren, 1 << ctr_index) The new logic is RISCV_EXCP_VIRT_INSTRUCTION_FAULT is triggered when !get_field(env->mcounteren, ctr_mask) or !get_field(env->hcounteren, 1 << ctr_index) && get_field(env->mcounteren, 1 << ctr_index) Regards, Weiwei Li } #endif

Re: [PATCH v11 2/6] target/riscv: Simplify counter predicate function

在 2022/7/28 上午5:40, Atish Kumar Patra 写道: On Wed, Jul 27, 2022 at 1:35 AM Weiwei Li <mailto:liwei...@iscas.ac.cn>> wrote: 在 2022/7/27 下午2:49, Atish Patra 写道: > All the hpmcounters and the fixed counters (CY, IR, TM) can be represented > as a unified cou

Re: [PATCH v6 3/5] target/riscv: smstateen check for fcsr

在 2022/7/28 下午2:15, Mayuresh Chitale 写道: On Mon, 2022-07-25 at 15:23 +0800, Weiwei Li wrote: 在 2022/7/24 下午11:49, Mayuresh Chitale 写道: On Fri, 2022-07-22 at 09:42 +0800, Weiwei Li wrote: 在 2022/7/21 下午11:31, Mayuresh Chitale 写道: If smstateen is implemented and sstateen0.fcsr is clear then

Re: [PATCH v6 2/5] target/riscv: smstateen check for h/senvcfg

在 2022/7/28 下午2:41, Mayuresh Chitale 写道: On Fri, 2022-07-22 at 08:45 +0800, Weiwei Li wrote: 在 2022/7/21 下午11:31, Mayuresh Chitale 写道: Accesses to henvcfg, henvcfgh and senvcfg are allowed only if corresponding bit in mstateen0/hstateen0 is enabled. Otherwise an illegal instruction trap is

Re: [PATCH v12 1/6] target/riscv: Add sscofpmf extension support

values for RV32*/ +target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; + I think mhpmeventh_val can be uint32_t directly. Or  use the usual way to implement this type of CSRs: change  the  type of mhpmevent_val to uint64_t and mhpmeventh csr reuse the high part of mhpmeventh_val for R

Re: [PATCH v7 1/4] target/riscv: Add smstateen support

mode, it will always be allowed.  So I think we should add check for current priv  is less than M mode here. Similar to sstateen. Regards, Weiwei Li +return hmode(env, csrno); +} + +static RISCVException hstateen(CPURISCVState *env, int csrno) +{ +return hstateen_pred(env,

Re: [PATCH v7 2/4] target/riscv: smstateen check for h/senvcfg

EXCP_VIRT_INSTRUCTION_FAULT instead if "!(env->sstateen[index] & bit)" here. Regards, Weiwei Li +} + +return RISCV_EXCP_NONE; +} +#endif + static RISCVException fs(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) @@ -1715,6 +1747,13 @@ static RISCV

Re: [PATCH v7 3/4] target/riscv: smstateen check for fcsr

is not existed(that is misa.F is zero and Zfinx is not supported). However, when FCSR is exsited, the final exception should be decided by current privilege level and the stateen related csr values just like the access control of FCSR. Regards, Weiwei Li Signed-off-by: Mayuresh Chitale

Re: [PATCH v7 2/3] target/riscv: Add stimecmp support

77,13 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) set_resetvec(env, cpu->cfg.resetvec); +#ifndef CONFIG_USER_ONLY +if (cpu->cfg.ext_sstc) { +riscv_timer_init(cpu); + } +#endif /* CONFIG_USER_ONLY */ + + multi blink line here. Regards, Weiwei Li /

Re: [PATCH v7 3/3] target/riscv: Add vstimecmp support

ink hcounteren only works for VS mode here. So we should add check for virt  mode is enabled here. +return RISCV_EXCP_NONE; +} It's better to return hmode(env, csrno) instead of RISCV_EXCP_NONE here. Regards, Weiwei Li + +static RISCVException read_vstimecmp(CPURISCVState

[PATCH] target/riscv: Fix priority of csr related check in riscv_csrrw_check

: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/csr.c | 44 +--- 1 file changed, 25 insertions(+), 19 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 0fb042b2fd..d81f466c80 100644 --- a/target/riscv/csr.c +++ b/target/riscv

Re: [PATCH v7 3/3] target/riscv: Add vstimecmp support

在 2022/8/4 上午5:05, Atish Kumar Patra 写道: On Wed, Aug 3, 2022 at 1:49 AM Weiwei Li <mailto:liwei...@iscas.ac.cn>> wrote: 在 2022/8/3 下午4:25, Atish Patra 写道: > vstimecmp CSR allows the guest OS or to program the next guest timer > interrupt directly. Thus, hyper

Re: [PATCH] target/riscv: Fix priority of csr related check in riscv_csrrw_check

在 2022/8/4 上午11:38, Anup Patel 写道: On Wed, Aug 3, 2022 at 6:16 PM Weiwei Li wrote: Normally, riscv_csrrw_check is called when executing Zicsr instructions. And we can only do access control for existed CSRs. So the priority of CSR related check, from highest to lowest, should be as follows

Re: [PATCH v8 3/3] target/riscv: Add vstimecmp support

.min_priv_ver = PRIV_VERSION_1_12_0 }, [CSR_STIMECMPH] = { "stimecmph", sstc, read_stimecmph, write_stimecmph, .min_priv_ver = PRIV_VERSION_1_12_0 }, +[CSR_VSTIMECMP] = { "vstimecmp", sstc_hmode, read_vstimecmp, +

Re: [PATCH v8 3/3] target/riscv: Add vstimecmp support

在 2022/8/9 上午1:20, Atish Kumar Patra 写道: On Sun, Aug 7, 2022 at 6:50 PM Weiwei Li <mailto:liwei...@iscas.ac.cn>> wrote: 在 2022/8/4 上午9:42, Atish Patra 写道: > vstimecmp CSR allows the guest OS or to program the next guest timer > interrupt directly. Thus, hyper

Re: [PATCH v8 3/3] target/riscv: Add vstimecmp support

在 2022/8/10 上午3:34, Atish Kumar Patra 写道: On Tue, Aug 9, 2022 at 12:01 AM Weiwei Li <mailto:liwei...@iscas.ac.cn>> wrote: 在 2022/8/9 上午1:20, Atish Kumar Patra 写道: On Sun, Aug 7, 2022 at 6:50 PM Weiwei Li mailto:liwei...@iscas.ac.cn>> wrote: 在 2022/8/

Re: [PATCH v8 3/3] target/riscv: Add vstimecmp support

在 2022/8/10 下午1:45, Atish Kumar Patra 写道: On Tue, Aug 9, 2022 at 6:33 PM Weiwei Li <mailto:liwei...@iscas.ac.cn>> wrote: 在 2022/8/10 上午3:34, Atish Kumar Patra 写道: On Tue, Aug 9, 2022 at 12:01 AM Weiwei Li mailto:liwei...@iscas.ac.cn>> wrote: 在 2022/8/

Re: [PATCH v9 3/3] target/riscv: Add vstimecmp support

+++ 6 files changed, 118 insertions(+), 6 deletions(-) LGTM. Reviewed-by: Weiwei Li Regards, Weiwei Li diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 4cda2905661e..1fd382b2717f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -312,6 +312,8 @@ struct CPUArchState

Re: [PATCH v2] target/riscv: Fix LMUL check to use VLEN

: configure instructions") Signed-off-by: Rob Bradford --- V2: Switch check to use VLEN and active SEW vs ELEN and minimum SEW --- Reviewed-by: Weiwei Li Weiwei Li target/riscv/vector_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/v

Re: [PATCH 1/3] target/riscv: Add cycle & instret privilege mode filtering properties

fpmf", RISCVCPU, cfg.ext_sscofpmf, false), +DEFINE_PROP_BOOL("smcntrpmf", RISCVCPU, cfg.ext_smcntrpmf, false), Normally, property should be exposed to user at last after the function is implemented. Regards, Weiwei Li DEFINE_PROP_BOOL("Zifence

Re: [PATCH 3/3] target/riscv: Add cycle & instret privilege mode filtering support

_0}, +[CSR_MINSTRETCFGH] = { "minstretcfgh", smcntrpmf, read_minstretcfgh, + write_minstretcfgh, + .min_priv_ver = PRIV_VERSION_1_12_0}, This two CSRs are RV32-only, they cannot directly share the same predicate as MCYCLECFG

Re: [PATCH for-8.2 v5 01/11] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[]

the point that these are more a CPU option than an extension. No functional changes made. Signed-off-by: Daniel Henrique Barboza --- Reviewed-by: Weiwei Li Weiwei Li target/riscv/cpu.c | 33 +++-- 1 file changed, 23 insertions(+), 10 deletions(-) diff --gi

Re: [PATCH for-8.2 v5 03/11] target/riscv/cpu.c: split kvm prop handling to its own helper

dd. The rest of riscv_cpu_add_user_properties() body will then be relieved from having to deal with KVM constraints. Signed-off-by: Daniel Henrique Barboza --- Reviewed-by: Weiwei Li Weiwei Li target/riscv/cpu.c | 65 ++ 1 file changed, 42 insertions(+), 23 deletions(-

Re: [PATCH for-8.2 v5 04/11] target/riscv/cpu.c: del DEFINE_PROP_END_OF_LIST() from riscv_cpu_extensions

to encapsulate more repetitions in macros later on. Signed-off-by: Daniel Henrique Barboza --- Reviewed-by: Weiwei Li Weiwei Li target/riscv/cpu.c | 12 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7f0852a14e..4d

Re: [PATCH for-8.2 v5 08/11] target/riscv/cpu.c: add ADD_UNAVAIL_KVM_PROP_ARRAY() macro

On 2023/7/21 01:19, Daniel Henrique Barboza wrote: Use a macro in riscv_cpu_add_kvm_properties() to eliminate some of its code repetition, similar to what we're already doing with ADD_CPU_QDEV_PROPERTIES_ARRAY(). Signed-off-by: Daniel Henrique Barboza --- Reviewed-by: Weiwei Li Weiw

Re: [PATCH 1/2] target/riscv/cpu.c: add zmmul isa string

ue Barboza --- Reviewed-by: Weiwei Li Weiwei Li target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9339c0241d..d64ac07558 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -88,6 +88,7 @@ static const struct isa_ext_data isa

Re: [PATCH 2/2] target/riscv/cpu.c: add smepmp isa string

On 2023/7/20 21:24, Daniel Henrique Barboza wrote: The cpu->cfg.epmp extension is still experimental, but it already has a 'smepmp' riscv,isa string. Add it. Signed-off-by: Daniel Henrique Barboza --- Reviewed-by: Weiwei Li Weiwei Li target/riscv/cpu.c | 1 + 1 fi

Re: [PATCH] target/riscv: Fix zfa fleq.d and fltq.d

On 2023/7/28 08:39, LIU Zhiwei wrote: Commit a47842d ("riscv: Add support for the Zfa extension") implemented the zfa extension. However, it has some typos for fleq.d and fltq.d. Both of them misused the fltq.s helper function. Signed-off-by: LIU Zhiwei --- Reviewed-by:

Re: [PATCH v6 09/12] target/riscv/cpu.c: limit cfg->vext_spec log message

it's strange to force users to set 'vext_spec' to get rid of this message. Change riscv_cpu_validate_v() to not throw this log message if env->vext_ver is already set. Signed-off-by: Daniel Henrique Barboza --- Reviewed-by: Weiwei Li Weiwei Li target/riscv/cpu.c |

[PATCH v10 0/9] support subsets of virtual memory extension

instead of helper for push/pop v2: * add check for relationship between Zca/Zcf/Zcd with C/F/D based on related discussion in review of Zc* spec * separate c.fld{sp}/fsd{sp} with fld{sp}/fsd{sp} before support of zcmp/zcmt Weiwei Li (9): target/riscv: add cfg properties for Zc* extension

[PATCH v10 9/9] disas/riscv.c: add disasm support for Zc*

Zcmp/Zcmt instructions will override disasm for c.fld*/c.fsd* instructions currently Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Acked-by: Alistair Francis --- disas/riscv.c | 228 +- 1 file changed, 227 insertions(+), 1 deletion

[PATCH v10 4/9] target/riscv: add support for Zcd extension

Separate c_fld/c_fsd from fld/fsd to add additional check for c.fld{sp}/c.fsd{sp} which is useful for zcmp/zcmt to reuse their encodings Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn16.decode

[PATCH v10 7/9] target/riscv: add support for Zcmt extension

Add encode, trans* functions and helper functions support for Zcmt instrutions Add support for jvt csr Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 4 ++ target/riscv

[PATCH v10 8/9] target/riscv: expose properties for Zc* extension

Expose zca,zcb,zcf,zcd,zcmp,zcmt properties Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 13 + 1 file changed, 13 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 39ab7e46d3..6df667805f 100644

[PATCH v10 1/9] target/riscv: add cfg properties for Zc* extension

Add properties for Zca,Zcb,Zcf,Zcd,Zcmp,Zcmt extension Add check for these properties Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 43 +++ target/riscv/cpu.h

[PATCH v10 5/9] target/riscv: add support for Zcb extension

Add encode and trans* functions support for Zcb instructions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn16.decode| 24 ++ target/riscv/insn_trans/trans_rvzce.c.inc | 100

[PATCH v10 2/9] target/riscv: add support for Zca extension

Modify the check for C extension to Zca (C implies Zca) Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Wilfred Mallawa --- target/riscv/insn_trans/trans_rvi.c.inc | 4 ++-- target/riscv/translate.c

[PATCH v10 3/9] target/riscv: add support for Zcf extension

Separate c_flw/c_fsw from flw/fsw to add check for Zcf extension Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn16.decode | 8 target/riscv/insn_trans/trans_rvf.c.inc | 18

[PATCH v10 6/9] target/riscv: add support for Zcmp extension

Add encode, trans* functions for Zcmp instructions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn16.decode| 18 +++ target/riscv/insn_trans/trans_rvzce.c.inc | 189

[PATCH 8/8] target/riscv: Fix lines with over 80 characters

Fix lines with over 80 characters for both code and comments in vector_helper.c, pmp.c and pmu.c. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/pmp.c | 6 ++- target/riscv/pmu.c | 3 +- target/riscv/vector_helper.c | 76

[PATCH 1/8] target/riscv: Remove redundant call to riscv_cpu_virt_enabled

The assignment is done under the condition riscv_cpu_virt_enabled()=true. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu_helper.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index

[PATCH 7/8] target/riscv: Fix format for comments

Fix formats for multi-lines comments. Add spaces around single line comments(after "/*" and before "*/"). Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/arch_dump.c| 3 +- target/riscv/cpu.c | 2 +-

[PATCH 3/8] target/riscv: Remove check on RVH for riscv_cpu_virt_enabled

Since env->virt.VIRT_ONOFF is initialized as false, and will not be set to true when RVH is disabled, so we can just return this bit(false) when RVH is not disabled. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu_helper.c | 4 1 file changed, 4 deleti

[PATCH 6/8] target/riscv: Fix format for indentation

Fix identation problems, and try to use the same indentation strategy in the same file. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/arch_dump.c| 4 +- target/riscv/cpu.c | 4 +- target/riscv/cpu_helper.c | 15

[PATCH 2/8] target/riscv: Remove redundant check on RVH

Check on riscv_cpu_virt_enabled contains the check on RVH. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/op_helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 84ee018f7d..1eecae9547

[PATCH 0/8] target/riscv: Simplification for RVH related check and code style fix

This patchset tries to simplify the RVH related check and fix some code style problems, such as problems for indentation, multi-line comments and lines with over 80 characters. The port is available here: https://github.com/plctlab/plct-qemu/tree/plct-cleanup-upstream Weiwei Li (8): target

[PATCH 5/8] target/riscv: Remove redundant parentheses

Remove redundant parentheses in get_physical_address. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 3862e7b677..de2d4a8c1d

[PATCH 4/8] target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabled

In current implementation, riscv_cpu_set_virt_enabled is only called when RVH is enabled. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu_helper.c | 4 1 file changed, 4 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index

[PATCH v2 07/10] target/riscv: Remove redundant parentheses

Remove redundant parentheses in get_physical_address. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: LIU Zhiwei --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b

[PATCH v2 05/10] target/riscv: Convert env->virt to a bool env->virt_enabled

From: LIU Zhiwei Currently we only use the env->virt to encode the virtual mode enabled status. Let's make it a bool type. Signed-off-by: LIU Zhiwei Reviewed-by: Weiwei Li Message-ID: <20230325145348.1208-1-zhiwei_...@linux.alibaba.com> --- target/riscv/cpu.h| 2 +-

[PATCH v2 02/10] target/riscv: Remove redundant check on RVH

Check on riscv_cpu_virt_enabled contains the check on RVH. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: LIU Zhiwei --- target/riscv/op_helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/riscv/op_helper.c

[PATCH v2 06/10] target/riscv: Remove riscv_cpu_virt_enabled()

Directly use env->virt_enabled instead. Suggested-by: LIU Zhiwei Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu.c| 2 +- target/riscv/cpu.h| 1 - target/riscv/cpu_helper.c | 51 ++- target/riscv/cs

[PATCH v2 10/10] target/riscv: Fix lines with over 80 characters

Fix lines with over 80 characters for both code and comments in vector_helper.c, pmp.c and pmu.c. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: LIU Zhiwei --- target/riscv/pmp.c | 6 ++- target/riscv/pmu.c | 3 +- target/riscv/vector_helper.c | 76

[PATCH v2 08/10] target/riscv: Fix format for indentation

Fix identation problems, and try to use the same indentation strategy in the same file. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: LIU Zhiwei --- target/riscv/arch_dump.c| 4 +- target/riscv/cpu.c | 4 +- target/riscv

[PATCH v2 01/10] target/riscv: Remove redundant call to riscv_cpu_virt_enabled

The assignment is done under the condition riscv_cpu_virt_enabled()=true. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: LIU Zhiwei --- target/riscv/cpu_helper.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target

[PATCH v2 00/10] target/riscv: Simplification for RVH related check and code style fix

bled() in patch 6 (suggested by LIU Zhiwei) * remain the orginal identation for macro name in patch 8 (suggested by LIU Zhiwei) LIU Zhiwei (1): target/riscv: Convert env->virt to a bool env->virt_enabled Weiwei Li (9): target/riscv: Remove redundant call to riscv_cpu_virt_enabled targe

[PATCH v2 04/10] target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabled

In current implementation, riscv_cpu_set_virt_enabled is only called when RVH is enabled. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: LIU Zhiwei --- target/riscv/cpu_helper.c | 5 + 1 file changed, 1 insertion(+), 4 deletions(-) diff

[PATCH v2 03/10] target/riscv: Remove check on RVH for riscv_cpu_virt_enabled

Since env->virt.VIRT_ONOFF is initialized as false, and will not be set to true when RVH is disabled, so we can just return this bit(false) when RVH is not disabled. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: LIU Zhiwei --- target/ri

[PATCH v2 09/10] target/riscv: Fix format for comments

Fix formats for multi-lines comments. Add spaces around single line comments(after "/*" and before "*/"). Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Acked-by: Richard Henderson Reviewed-by: LIU Zhiwei --- target/riscv/arch_dump.c| 3 +-

[PATCH 3/5] target/riscv: Fix pointer mask transformation for vector address

actual_address = (requested_address & ~mpmmask) | mpmbase. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/vector_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 2423af

[PATCH 0/5] target/riscv: Fix pointer mask related support

This patchset tries to fix some problems in current implementation for pointer mask extension, and add support for pointer mask of instruction fetch. The port is available here: https://github.com/plctlab/plct-qemu/tree/plct-pm-fix Weiwei Li (5): target/riscv: Fix effective address for pointer

[PATCH 1/5] target/riscv: Fix effective address for pointer mask

Since pointer mask works on effective address, and the xl works on the generation of effective address, so xl related calculation should be done before pointer mask. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/translate.c | 16 1 file changed, 12

[PATCH 4/5] target/riscv: take xl into consideration for vector address

Sign-extend the vector address when xl = 32. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/vector_helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index a58d82af8c..07477663eb 100644 --- a

[PATCH 2/5] target/riscv: Use sign-extended data address when xl = 32

Currently, the pc use signed-extend(in gen_set_pc*) when xl = 32. And data address should use the same memory address space with it when xl = 32. So we should change their address calculation to use sign-extended address when xl = 32. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang

[PATCH 5/5] target/riscv: Add pointer mask support for instruction fetch

Transform the fetch address before page walk when pointer mask is enabled for instruction fetch. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu.h| 1 + target/riscv/cpu_helper.c | 25 +++-- target/riscv/csr.c| 2 -- 3 files

[PATCH v2 5/5] target/riscv: Add pointer mask support for instruction fetch

Transform the fetch address in cpu_get_tb_cpu_state() when pointer mask for instruction is enabled. Enable PC-relative translation when J is enabled. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu.c| 4 target/riscv/cpu.h| 1 + target/riscv

[PATCH v2 0/5] target/riscv: Fix pointer mask related support

problems * Add patch 4 and 5 to use PC-relative translation for pointer mask for instruction fetch Weiwei Li (5): target/riscv: Fix pointer mask transformation for vector address target/riscv: Update cur_pmmask/base when xl changes target/riscv: Sync cpu_pc before update badaddr target/riscv: Add

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