Public bug reported:
Hi,
since qemu 4.1.0 the TSR bit in mstatus register is supported. But it
does not allow for executing sret in m-mode.
>From the RISC-V specifications:
"When TSR=1, attempts to execute SRET while executing in S-mode will raise an
illegal instruction
exception. When TSR=0, t
Public bug reported:
I am working on a project with custom inter processor interrupts (IPIs) on the
RISC-V virt machine.
After upgrading from version 3.1.0 to 4.1.0 which fixes a related issue
(https://github.com/riscv/riscv-qemu/issues/132) I am able to use the CPU
hotplug feature.
However, i
I created a minimal example from my setup. I'm running a kernel 4.19.57 with a
custom firmware based on bbl (https://github.com/riscv/riscv-pk).
An ioctl device from a kernel module is used to execute the code above in
kernel space.
In the example, the userspace application proceeds after a coup
** Description changed:
I am working on a project with custom inter processor interrupts (IPIs) on
the RISC-V virt machine.
After upgrading from version 3.1.0 to 4.1.0 which fixes a related issue
(https://github.com/riscv/riscv-qemu/issues/132) I am able to use the CPU
hotplug feature.
