** Changed in: qemu
Status: New => Incomplete
** Changed in: qemu
Assignee: (unassigned) => pranith (bobby-prani)
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Title:
Can you post the `configure` command line you used when you try to
compile?
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Title:
Can't compile qemu because of errors in the Xen code
Status
** Changed in: qemu
Status: New => Confirmed
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Title:
qemu on ARM hosts can't boot i386 image
Status in QEMU:
Confirmed
Status in Linaro
Fix has been committed upstream.
** Changed in: qemu
Status: New => Fix Released
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Title:
Unsupported syscalls 370 and 355
Status in QEM
Can you try the latest upstream git version from:
https://github.com/qemu/qemu?
Also can you post your configure command line?
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Title:
Error co
This does not happend anymore with the upstream git. Closing. Please
reopen if you still see this.
** Changed in: qemu
Status: New => Fix Released
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** Changed in: qemu
Status: Fix Committed => Fix Released
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Title:
Cant compile on ubuntu 14.04 x64
Status in QEMU:
Fix Released
Bug d
** Changed in: qemu
Status: New => Fix Released
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Title:
qemu crashes when ctrl-alt-u is pressed
Status in QEMU:
Fix Released
Bug desc
** Changed in: qemu
Status: New => Fix Released
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Title:
qemu-system-i386: -vnc localhost:0,to=99,id=default: Invalid parameter
'to'
St
** Changed in: qemu
Status: New => Fix Released
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Title:
Wrong signal handling in qemu-aarch64.
Status in QEMU:
Fix Released
Bug descr
** Changed in: qemu
Status: New => Fix Released
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Title:
qemu-img conversion to qcow2 hangs with blank image less than 100kiB
Status in Q
** Changed in: qemu
Status: New => Invalid
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Title:
qemu-system-arm hangs at start on OS X
Status in QEMU:
Invalid
Bug description:
** Changed in: qemu
Status: Confirmed => Fix Released
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Title:
Empty password allows access to VNC in libvirt
Status in libvirt:
Unknown
*** This bug is a duplicate of bug 1505062 ***
https://bugs.launchpad.net/bugs/1505062
** This bug has been marked a duplicate of bug 1505062
Regression: QEMU 2.4 on Linux 4.2 fails to init display with SMM enabled
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What is your host processor?
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Title:
loadvm makes Windows 7 x86 guest crash with some CPUs
Status in QEMU:
New
Bug description:
Running qe
OK. I am closing this then. :)
** Changed in: qemu
Status: New => Invalid
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Title:
Can't compile qemu because of errors in the Xen code
** Changed in: qemu
Status: New => Confirmed
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Title:
qemu-2.4.1 fails when compiled against pulseaudio
Status in QEMU:
Confirmed
Bug
** Changed in: qemu
Status: New => Confirmed
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Title:
TCG: mov to segment register is incorrectly emulated for AMD CPUs
Status in QEMU:
** Changed in: qemu
Status: New => Confirmed
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Title:
SIMD instructions translated to scalar host instructions
Status in QEMU:
Confirme
** Changed in: qemu
Status: New => Confirmed
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Title:
Frozen Windows 7 VMs with VGA CVE-2016-3712 fix (2.6.0 and 2.5.1.1)
Status in QEMU:
** Changed in: qemu
Status: New => Invalid
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Title:
/home/qemu-0.12.3/tcg/tcg.c:1367: tcg fatal error
Status in QEMU:
Invalid
Bug descr
** Changed in: qemu
Status: In Progress => Fix Committed
** Changed in: qemu
Assignee: Timothy Pearson (kb9vqf) => pranith (bobby-prani)
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Closing since it seems to be fixed in latest release.
** Changed in: qemu
Status: Incomplete => Fix Released
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Title:
qemu hangs on shutdo
** Changed in: qemu
Status: New => Confirmed
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Title:
QEMU epoll for i386-linux-user on arm host is broken in 2.6
Status in QEMU:
Confi
Please try the latest version. The version you reported is too old.
** Changed in: qemu
Status: New => Invalid
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Title:
Windows 2008 datac
** Changed in: qemu
Status: New => Invalid
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Title:
aarch64-softmmu "bad ram pointer" crash
Status in QEMU:
Invalid
Bug description:
** Changed in: qemu
Status: New => Incomplete
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Title:
qemu live migration failed
Status in QEMU:
Incomplete
Bug description:
qemu l
** Changed in: qemu
Status: Incomplete => Confirmed
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qemu live migration failed
Status in QEMU:
Confirmed
Bug description:
q
** Changed in: qemu
Status: New => Confirmed
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Title:
qemu-system-arm hangs with -icount and -nodefaults
Status in QEMU:
Confirmed
Bug
Questions like this are better directed to the mailing list. Please
email qemu-disc...@nongnu.org and/or qemu-devel@nongnu.org. Thanks!
** Changed in: qemu
Status: New => Invalid
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** Changed in: qemu
Status: New => Confirmed
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Title:
movdqu partial write at page boundary
Status in QEMU:
Confirmed
Bug description:
** Changed in: qemu
Status: Fix Committed => Fix Released
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Title:
Assertion failed with USB pass through with XHCI controller
Status in
Hello,
I am trying to count the number of barrier instructions (dmb) which are being
executed in an multi-threaded ARM executable. I am running the executable using
qemu user mode with the following patch applied.
Basically I created two counters in the ARM cpu state and incrementing them by
gene
Hi Max,
On Wed, Oct 15, 2014 at 9:54 PM, Max Filippov wrote:
> Hi,
>
> On Thu, Oct 16, 2014 at 5:45 AM, Pranith Kumar wrote:
>> Is there something obviously wrong with what I am trying to do? Any help is
>> highly appreciated.
>> --- a/target-arm/translate.c
>
Hi Peter,
On Thu, Oct 16, 2014 at 4:05 AM, Peter Maydell wrote:
> On 16 October 2014 03:45, Pranith Kumar wrote:
>> The problem I am facing is that this seems to be crashing when run with a
>> multi-threaded executable.
>
> This is nothing to do with your changes -- us
On Wed, Oct 15, 2014 at 10:12 PM, Max Filippov wrote:
> On Thu, Oct 16, 2014 at 6:00 AM, Pranith Kumar wrote:
>>>> +tcg_gen_add_i32(cpu_fence_count, cpu_fence_count, 1);
>>>
>>> tcg_gen_addi_i32, as you're adding an immediate.
>>> Enabling
se two are not upstream yet, would be great to see it there.
Thanks!
--
Pranith
Hi Dave,
Commit 334e580a6f97 ("fs: XFS_IOC_FS[SG]SETXATTR to
FS_IOC_FS[SG]ETXATTR promotion") breaks building latest qemu as
follows:
In file included from /usr/include/xfs/xfs.h:58:0,
from /home/pranith/qemu/block/raw-posix.c:96:
/usr/include/xfs/xfs_fs.h:4
ter/examples/x86/cachesim.cpp
Setup instructions: https://github.com/pranith/qsim-setup
--
Pranith
st annotating the code to generate appropriate
callbacks. You find the patches here:
https://github.com/pranith/qemu/commits/aaa8b521187e4ecd1d35914e9b119f9d6eaa8633
I try to rebase once a release comes out. The current version is based
on 2.4, so it is pretty current. I will rebase onto 2.5 in the
think is going to based on top of Alvise's work. I am comfortable in
working with various memory consistency models and have a decent
programming experience.
Please let me know if you have any other suggestions for projects or
any other related advice.
Thanks!
--
Pranith
ig=sig@entry=6) at
../nptl/sysdeps/unix/sysv/linux/raise.c:56
#1 0x722150d8 in __GI_abort () at abort.c:89
#2 0x5572014c in qemu_ram_addr_from_host_nofail
(ptr=0xffc000187863) at /home/pranith/devops/code/qemu/cputlb.c:357
#3 0x557209dd in get_page_addr_code
23.795721] [] el1_irq+0x64/0xc0
[ 23.796131] [] cpu_startup_entry+0x130/0x204
[ 23.796605] [] rest_init+0x78/0x84
[ 23.797028] [] start_kernel+0x3a0/0x3b8
[ 23.797528] rcu_sched kthread starved for 2101 jiffies!
I will try to debug and see where it is hanging.
Thanks!
--
Pranith
icount sleep takes on or off as options. A few places mention sleep=no
which is not accepted. This patch corrects them.
Signed-off-by: Pranith Kumar
---
cpus.c | 4 ++--
qemu-options.hx | 6 +++---
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/cpus.c b/cpus.c
index
icount sleep takes on or off as options. A few places mention sleep=no
which is not accepted. This patch corrects them.
Signed-off-by: Pranith Kumar
---
cpus.c | 4 ++--
qemu-options.hx | 6 +++---
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/cpus.c b/cpus.c
index
Signed-off-by: Pranith Kumar
---
cpus.c | 4 ++--
qemu-options.hx | 6 +++---
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/cpus.c b/cpus.c
index 9592163..bc774e2 100644
--- a/cpus.c
+++ b/cpus.c
@@ -630,7 +630,7 @@ void configure_icount(QemuOpts *opts, Error **errp
o '-d' option because of which monitor dumps
the logs to stderr.
Fix this by opening the log file when '-D' is specified on the command line.
Also fix an ancient comment which does not hold true since changing location and
log level has now been streamlined.
Signed-off-by: Pra
769ee182 in start_thread (arg=0x7fffc3b94700) at
pthread_create.c:312
#18 0x7671b47d in clone () at
../sysdeps/unix/sysv/linux/x86_64/clone.S:111
--
Pranith
ut I understand the
apprehension that might be. I will try to reproduce this with an upstream
virgin QEMU.
Thanks!
--
Pranith
understand why this is
happening?
Thanks!
--
Pranith
on stages and not during later stages:
http://www.spinics.net/lists/gcchelp/msg39798.html
AFAIU, in these later stages, even adding a barrier() as we are doing will
have no effect.
Can you point me to any docs which talk more about this?
Thanks!
--
Pranith
quot;?
I am not sure busybox has sh shell installed or configured properly.
That is what your error message is pointing to atleast.
> starting init :/bin/sh exists but couldn’t execute it
> kernel panic – not syncing no working init found
Thanks!
--
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rdinit=/sbin/init”
>
Can you post the output when you run this command? In particular, does
the /sbin/init exist in the rootfs?
--
Pranith
y passing init= option
> to kernel
>
I don't think this is a qemu problem. From the error message it looks
like init in your busybox root image is not configured properly. I
would focus on finding why the init file is not able to
run(permissions, maybe?).
--
Pranith
stand one barrier(), but having two on both sides seems
unnecessary. I would prefer we clean up and have just one. Although, I
think it is just an annoyance since performance wise there is no
difference. Two consecutive barrier()'s should behave just like one.
Thanks!
--
Pranith
smp_wmb() or smp_rmb() to get
> reordered. In our case it was in thread-pool.c; Kevin Wolf did the
> analysis.
If ordering was crucial for those stores, I think it would have been
better to use atomics on them to enforce ordering.
Also, do you plan to introduce load_acquire/store_release() operations
like done in the linux kernel? They would cleanly map to gcc atomics
and make the ordering requirements explicit.
Thanks!
--
Pranith
Add a missing end brace and update doc to point to the latest access
macro. ACCESS_ONE() is deprecated.
Signed-off-by: Pranith Kumar
---
docs/atomics.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/docs/atomics.txt b/docs/atomics.txt
index ef285e3..bba771e 100644
On Tue, Apr 12, 2016 at 7:42 AM, Marc-André Lureau
wrote:
> Hi
>
> On Mon, Apr 11, 2016 at 7:30 PM, Pranith Kumar wrote:
>> Add a missing end brace and update doc to point to the latest access
>> macro. ACCESS_ONE() is deprecated.
>
> ONE/ONCE
Right, I missed this o
On Tue, Apr 12, 2016 at 5:20 PM, Paolo Bonzini wrote:
> FWIW I'll be mostly offline this week and on vacation starting from the
> next, so it's probably best if you send the patch at the beginning of
> May. It will be fixed _and_ act as a reminder. :)
Sure, I will do so in May.
--
Pranith
Add a missing end brace and update doc to point to the latest access
macro. ACCESS_ONCE() is deprecated.
Signed-off-by: Pranith Kumar
---
docs/atomics.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/docs/atomics.txt b/docs/atomics.txt
index ef285e3..bba771e 100644
ors) is enabled since fences
are not necessary on UP systems.
--
Pranith
eration for now.
Thanks,
--
Pranith
Hi Richard,
Thank you for the helpful comments.
On Wed, May 25, 2016 at 1:35 PM, Richard Henderson wrote:
> On 05/24/2016 10:18 AM, Pranith Kumar wrote:
>> diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
>> index 92be341..93ea42e 100644
>> --- a/tcg/i386/tcg-
ve any armv7 images handy to test the backends.
>
Thanks Richard for fixing this up for other archs. You saved me a ton of work :)
I'll rebase my work on top of this patch series.
Regards,
--
Pranith
nd
>>> docs/atomics.txt. Why don't be consistent and avoid introducing yet
>>> another term for the same thing?
>>>
>> Fair point. Do you think tcg_out_mb() is better then?
>
> Yes, if used together with 'INDEX_op_mb', of course.
>
OK. I'll make the change. Thanks for the feedback!
--
Pranith
I have a version with this fixed. I will post my patches(v3) with this
changed.
Thanks,
--
Pranith
t; A bit of bike-shedding. While there's no common ISA term for "memory
> barrier" (also known as a "membar", "memory fence", etc.), we already
> refer to it as a "memory barrier" (or "mb") in include/qemu/atomic.h and
> docs/atomics.txt. Why don't be consistent and avoid introducing yet
> another term for the same thing?
>
Fair point. Do you think tcg_out_mb() is better then?
Thanks,
--
Pranith
he exclusive lock or wait spinning for it in lock(). So
unlock() should always see cpu_have_exclusive_lock as true. It is a
good place to find locking bugs.
--
Pranith
Signed-off-by: Richard Henderson
Signed-off-by: Pranith Kumar
---
tcg/ppc/tcg-target.inc.c | 8
1 file changed, 8 insertions(+)
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 1039407..45a667f 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
Signed-off-by: Richard Henderson
Signed-off-by: Pranith Kumar
---
tcg/mips/tcg-target.inc.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
index b2a839a..fc9c7fb 100644
--- a/tcg/mips/tcg-target.inc.c
+++ b/tcg/mips/tcg
Hello,
The following series adds fence instruction generation support to
TCG. The current work has been rebased on-top of Richard's patch
series.
This has been tested and confirmed to fix ordering issues on a x86
host with MTTCG enabled ARMv7 guest using KVM unit tests.
Pranith Kuma
We need to generate fence instructions only for SMP MTTCG guests. This
patch enforces that.
Signed-off-by: Pranith Kumar
---
tcg/tcg-op.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index a6f01a7..eeb0d0c 100644
--- a/tcg/tcg-op.c
+++ b
Cc: Aurelien Jarno
Signed-off-by: Richard Henderson
Signed-off-by: Pranith Kumar
---
tcg/ia64/tcg-target.inc.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/tcg/ia64/tcg-target.inc.c b/tcg/ia64/tcg-target.inc.c
index 261861f..88cc560 100644
--- a/tcg/ia64/tcg-target.inc.c
+++ b/tcg
This commit introduces the TCGOpcode for memory barrier instruction.
This opcode takes an argument which is the type of memory barrier
which should be generated.
Signed-off-by: Pranith Kumar
Signed-off-by: Richard Henderson
---
tcg/README| 17 +
tcg/tcg-op.c | 6
Signed-off-by: Pranith Kumar
Signed-off-by: Richard Henderson
---
target-arm/translate.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index c946c0e..e1b16c0 100644
--- a/target-arm/translate.c
+++ b/target-arm
Cc: Andrzej Zaborowski
Cc: Peter Maydell
Signed-off-by: Pranith Kumar
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.inc.c | 12
1 file changed, 12 insertions(+)
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
index a914762..e88d8ce 100644
--- a/tcg/arm
Signed-off-by: Richard Henderson
Signed-off-by: Pranith Kumar
---
target-alpha/translate.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 5b86992..17b68f5 100644
--- a/target-alpha/translate.c
+++ b/target-alpha
Generate mfence instruction on SSE2 enabled processors. For older
processors, generate a 'lock orl $0,0(%esp)' instruction which has
similar ordering semantics.
Signed-off-by: Pranith Kumar
[rth: Check for sse2, fallback to locked memory op otherwise.]
Signed-off-by: Richard Henderso
Added correct email for Sergey in CC.
I apologize for getting Sergey's email wrong. Please drop/correct his
email when replying to the patches in this series otherwise you will
see an email bounce.
On Tue, May 31, 2016 at 2:39 PM, Pranith Kumar wrote:
> Hello,
>
> The followi
Cc: Alexander Graf
Signed-off-by: Richard Henderson
Signed-off-by: Pranith Kumar
---
tcg/s390/tcg-target.inc.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
index e95b04b..b4f14bc 100644
--- a/tcg/s390/tcg-target.inc.c
+++ b
Cc: Blue Swirl
Signed-off-by: Richard Henderson
Signed-off-by: Pranith Kumar
---
tcg/sparc/tcg-target.inc.c | 8
1 file changed, 8 insertions(+)
diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c
index a611885..81f263f 100644
--- a/tcg/sparc/tcg-target.inc.c
+++ b
Cc: Stefan Weil
Signed-off-by: Richard Henderson
Signed-off-by: Pranith Kumar
---
tcg/tci/tcg-target.inc.c | 3 +++
tci.c| 3 +++
2 files changed, 6 insertions(+)
diff --git a/tcg/tci/tcg-target.inc.c b/tcg/tci/tcg-target.inc.c
index 4e91687..a507ceb 100644
--- a/tcg/tci
Cc: Claudio Fontana
Signed-off-by: Richard Henderson
Signed-off-by: Pranith Kumar
---
tcg/aarch64/tcg-target.inc.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index 08efdf4..c361a5c 100644
--- a/tcg/aarch64/tcg
Hi Richard,
Thanks for the review. I will make the changes you pointed out. One point below:
On Tue, May 31, 2016 at 4:24 PM, Richard Henderson wrote:
> On 05/31/2016 11:39 AM, Pranith Kumar wrote:
>> +/* TCGOpmb args */
>> +#define TCG_MB_FULL ((TCGArg)(0))
>>
On Tue, May 31, 2016 at 4:27 PM, Richard Henderson wrote:
> On 05/31/2016 11:39 AM, Pranith Kumar wrote:
>>
>> +case INDEX_op_mb:
>> +tcg_out_mb(s);
>
>
> You need to look at the barrier type and DTRT. In particular, the Linux
> smp_rmb and smp
nd write barriers. But we still
need to generate 'mfence' to prevent store-after-load reordering. I
will refine this in the next version.
Thanks,
--
Pranith
Sergey Fedorov writes:
> On 31/05/16 21:39, Pranith Kumar wrote:
>> diff --git a/tcg/README b/tcg/README
>> index f4a8ac1..cfe79d7 100644
>> --- a/tcg/README
>> +++ b/tcg/README
>> @@ -402,6 +402,23 @@ double-word product T0. The later is return
gnificant difference in performance when compared to plain
dmb+memory instruction sequence. So I would really like to keep the
option of generating acq/rel instructions(by combining barrier and
memory or some other way) open.
Thanks,
--
Pranith
AR_LD_LD
> qemu_ld_i32 x, y, i, m
> mbTCG_BAR_LD_ST
>
> We can then add an optimization pass which folds barriers with no memory
> operations in between, so that duplicates are eliminated.
>
Yes, folding/eliding these barriers in an optimization pass sounds
like a good idea.
Thanks,
--
Pranith
s
> is based on.
>
> The branch can be found at:
>
> https://github.com/stsquad/qemu/tree/mttcg/base-patches-v3
FYI, I tried booting a debian armv7 image with this branch and it
doesn't boot. I'll try to see why it is failing.
Thanks,
--
Pranith.
On Thu, Jun 2, 2016 at 3:37 PM, Sergey Fedorov wrote:
> On 31/05/16 21:39, Pranith Kumar wrote:
>> Signed-off-by: Pranith Kumar
>> Signed-off-by: Richard Henderson
>> ---
>> target-arm/translate.c | 7 +--
>> 1 file changed, 5 insertions(+), 2 deletions
On Mon, Jun 6, 2016 at 11:49 AM, Sergey Fedorov wrote:
> On 06/06/16 18:47, Pranith Kumar wrote:
>> On Mon, Jun 6, 2016 at 11:44 AM, Sergey Fedorov wrote:
>>> On 03/06/16 21:27, Pranith Kumar wrote:
>>>> On Thu, Jun 2, 2016 at 5:18 PM, Richard Henderson
On Mon, Jun 6, 2016 at 11:44 AM, Sergey Fedorov wrote:
> On 03/06/16 21:27, Pranith Kumar wrote:
>> On Thu, Jun 2, 2016 at 5:18 PM, Richard Henderson wrote:
>>>
>>> What if we have tcg_canonicalize_memop (or some such) split off the barriers
>>> into separat
On Mon, Jun 6, 2016 at 12:14 PM, Sergey Fedorov wrote:
> On 06/06/16 18:58, Pranith Kumar wrote:
>> On Mon, Jun 6, 2016 at 11:49 AM, Sergey Fedorov wrote:
>>> On 06/06/16 18:47, Pranith Kumar wrote:
>>>> On Mon, Jun 6, 2016 at 11:44 AM, Sergey Fedorov
>&
On Mon, Jun 6, 2016 at 3:23 PM, Richard Henderson wrote:
> On 06/06/2016 10:11 AM, Pranith Kumar wrote:
>>
>> If I read it correctly TCG_BAR_SYNC is equivalent to OR of all the
>> other four barriers. I am not sure if we can just construct SYNC like
>> this or if we n
Hi Peter,
On Tue, May 10, 2016 at 6:11 AM, Peter Maydell wrote:
> The TCR_EL2 and TCR_EL3 regdefs wer incorrectly using the
> vmsa_tcr_el1_write function for writes. Since these registers don't
> have the A1 bit that TCR_EL1 does, we don't need to do a tlb_flush()
> when they are written. Remove
]
&& addr >> TARGET_VIRT_ADDR_SPACE_BITS == addr >> 63);
Fix it by replacing (addr >> 63) by '1' which is what it evaluates to
since addr is negative.
Signed-off-by: Pranith Kumar
---
target-alpha/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 de
On Thu, Jun 16, 2016 at 3:07 PM, Richard Henderson wrote:
> On 06/16/2016 11:56 AM, Pranith Kumar wrote:
>> Using gcc 6.1 for alpha-linux-user target we see the following build
>> error:
>>
>> /mnt/devops/code/qemu/target-alpha/translate.c: In function ‘in_superpage
Hi Richard,
On Tue, May 31, 2016 at 4:34 PM, Richard Henderson wrote:
> On 05/31/2016 11:39 AM, Pranith Kumar wrote:
>>
>> +/* System instructions. */
>> +DMB_ISH = 0xd5033bbf,
>
> ...
>>
>> +case INDEX_op_mb:
>> +tcg_out
On Thu, Jun 16, 2016 at 8:43 PM, Laurent Vivier wrote:
>
>
> Le 16/06/2016 à 21:15, Pranith Kumar a écrit :
>> On Thu, Jun 16, 2016 at 3:07 PM, Richard Henderson wrote:
>>> On 06/16/2016 11:56 AM, Pranith Kumar wrote:
>>>> Using gcc 6.1 for alpha-linux-us
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