[PATCH v2 1/3] target/ppc: Implement Vector Expand Mask

From: Matheus Ferst Implement the following PowerISA v3.1 instructions: vexpandbm: Vector Expand Byte Mask vexpandhm: Vector Expand Halfword Mask vexpandwm: Vector Expand Word Mask vexpanddm: Vector Expand Doubleword Mask vexpandqm: Vector Expand Quadword Mask Reviewed-by: Richard Henderson

[PATCH v2 0/3] target/ppc: Implement Vector Expand/Extract Mask and Vector Mask

From: Matheus Ferst This is a small patch series just to allow Ubuntu 21.10 to boot with -cpu POWER10. Glibc 2.34 is using vextractbm, so the init is killed by SIGILL without the second patch of this series. The other two insns. are included as they are somewhat close to Vector Extract Mask (at

[PATCH v2 3/3] target/ppc: Implement Vector Mask Move insns

From: Matheus Ferst Implement the following PowerISA v3.1 instructions: mtvsrbm: Move to VSR Byte Mask mtvsrhm: Move to VSR Halfword Mask mtvsrwm: Move to VSR Word Mask mtvsrdm: Move to VSR Doubleword Mask mtvsrqm: Move to VSR Quadword Mask mtvsrbmi: Move to VSR Byte Mask Immediate Suggested-by

[PATCH v2 2/3] target/ppc: Implement Vector Extract Mask

From: Matheus Ferst Implement the following PowerISA v3.1 instructions: vextractbm: Vector Extract Byte Mask vextracthm: Vector Extract Halfword Mask vextractwm: Vector Extract Word Mask vextractdm: Vector Extract Doubleword Mask vextractqm: Vector Extract Quadword Mask Suggested-by: Richard

[PATCH 1/6] target/ppc: Fix gen_priv_exception error value in mfspr/mtspr

", as seen in [1]. [1] https://gitlab.com/qemu-project/qemu/-/issues/588 Fixes: 9b2fadda3e01 ("ppc: Rework generation of priv and inval interrupts") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/588 Reviewed-by: Fabiano Rosas Signed-off-by: Matheus Ferst --- This patch

[PATCH 5/6] target/ppc: fix PMU Group A register read/write exceptions

type and IC value as the error code. Fixes: 565cb1096733 ("target/ppc: add user read/write functions for MMCR0") Signed-off-by: Matheus Ferst --- target/ppc/power8-pmu-regs.c.inc | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/ppc/power8-pmu-regs

[PATCH 2/6] target/ppc: fix exception error value in slbfee

softmmu targets as gen_hvpriv_exception uses the same 'exception' argument (POWERPC_EXCP_HV_EMU) for raise_exception_*, and the powerpc_excp_* methods do not use lower bits of the exception error code when handling POWERPC_EXCP_{INVAL,PRIV}. Reported-by: Laurent Vivier Signed-off-by: Mat

[PATCH 4/6] target/ppc: fix exception error code in helper_{load, store}_dcr

code are ignored by all powerpc_excp_* methods on POWERPC_EXCP_INVAL exceptions. Reported-by: Laurent Vivier Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 2 +- target/ppc/timebase_helper.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target/ppc

[PATCH 3/6] target/ppc: remove mfdcrux and mtdcrux

The only PowerPC implementations with these insns were the 460 and 460F, which had their definitions removed in [1]. [1] 7ff26aa6c657 ("target/ppc: Remove unused PPC 460 and 460F definitions") Signed-off-by: Matheus Ferst --- target/ppc/cpu.h | 6 ++ target/ppc/transl

[PATCH 6/6] target/ppc: fix exception error code in spr_write_excp_vector

4 bits of the error code on POWERPC_EXCP_INVAL exceptions. Also, take the opportunity to replace printf with qemu_log_mask. Signed-off-by: Matheus Ferst --- target/ppc/translate.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/transla

[PATCH 0/6] Fix gen_*_exception error codes

The first patch of this series is the RFC of [1] (hence the r-b in v1). Patches 2~4 follow the other problems that Laurent pointed out, and patches 5-6 fix similar problems that I found. [1] https://lists.gnu.org/archive/html/qemu-ppc/2022-01/msg00400.html Matheus Ferst (6): target/ppc: Fix

[PATCH v4 27/47] target/ppc: Move xxsel to decodetree

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 6 target/ppc/insn64.decode| 24 target/ppc/translate/vsx-impl.c.inc | 20 ++ target/ppc/translate/vsx-ops.c.inc | 43 - 4

[PATCH v5 02/49] target/ppc: moved vector even and odd multiplication to decodetree

Henderson Signed-off-by: Lucas Mateus Castro (alqotel) Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 24 - target/ppc/insn32.decode| 22 + target/ppc/int_helper.c | 20 target/ppc/translate/vmx-impl.

[PATCH v5 08/49] target/ppc: Implement vextsd2q

From: Lucas Coutinho Reviewed-by: Richard Henderson Signed-off-by: Lucas Coutinho Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 1 + target/ppc/translate/vmx-impl.c.inc | 18 ++ 2 files changed, 19 insertions(+) diff --git a/target/ppc/insn32.decode

[PATCH v5 06/49] target/ppc: Implement vmsumudm instruction

From: Víctor Colombo Based on [1] by Lijun Pan , which was never merged into master. [1]: https://lists.gnu.org/archive/html/qemu-ppc/2020-07/msg00419.html Reviewed-by: Richard Henderson Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 1

[PATCH v5 00/49] target/ppc: PowerISA Vector/VSX instruction batch

From: Matheus Ferst This patch series implements 5 missing instructions from PowerISA v3.0 and 58 new instructions from PowerISA v3.1, moving 87 other instructions to decodetree along the way. Patches without review: 4, 24, 26, 27, 34, 35, 38, 40, 44-46 This series can also be found at: https

[PATCH v5 09/49] target/ppc: Move Vector Compare Equal/Not Equal/Greater Than to decodetree

From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 30 -- target/ppc/insn32.decode| 24 target/ppc/int_helper.c | 54 - target/ppc/translate/vmx-impl.c.inc | 89

[PATCH v5 03/49] target/ppc: Moved vector multiply high and low to decodetree

From: "Lucas Mateus Castro (alqotel)" Moved instructions vmulld, vmulhuw, vmulhsw, vmulhud and vmulhsd to decodetree Reviewed-by: Richard Henderson Signed-off-by: Lucas Mateus Castro (alqotel) Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 8

[PATCH v5 01/49] target/ppc: Introduce TRANS*FLAGS macros

From: Luis Pires New macros that add FLAGS and FLAGS2 checking were added for both TRANS and TRANS64. Reviewed-by: Richard Henderson Signed-off-by: Luis Pires [ferst: - TRANS_FLAGS2 instead of TRANS_FLAGS_E - Use the new macros in load/store vector insns ] Signed-off-by: Matheus Ferst

[PATCH v5 10/49] target/ppc: Move Vector Compare Not Equal or Zero to decodetree

From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 9 ++-- target/ppc/insn32.decode| 4 ++ target/ppc/int_helper.c | 50 +- target/ppc/translate/vmx-impl.c.inc | 66

[PATCH v5 04/49] target/ppc: vmulh* instructions without helpers

From: "Lucas Mateus Castro (alqotel)" Changed vmulhuw, vmulhud, vmulhsw, vmulhsd to not use helpers. Signed-off-by: Lucas Mateus Castro (alqotel) Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 4 -- target/ppc/int_helper.c | 35 ---

[PATCH v5 19/49] target/ppc: move vs[lr][a][bhwd] to decodetree

From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 17 target/ppc/translate/vmx-impl.c.inc | 41 +++-- target/ppc/translate/vmx-ops.c.inc | 13 + 3 files changed, 45 insertions

[PATCH v5 13/49] target/ppc: Implement Vector Compare Quadword

From: Matheus Ferst Implement the following PowerISA v3.1 instructions: vcmpsq: Vector Compare Signed Quadword vcmpuq: Vector Compare Unsigned Quadword Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 6 target/ppc/translate/vmx

[PATCH v5 05/49] target/ppc: Implement vmsumcud instruction

From: Víctor Colombo Based on [1] by Lijun Pan , which was never merged into master. [1]: https://lists.gnu.org/archive/html/qemu-ppc/2020-07/msg00419.html Reviewed-by: Richard Henderson Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 4

[PATCH v5 07/49] target/ppc: Move vexts[bhw]2[wd] to decodetree

Doubleword Reviewed-by: Richard Henderson Signed-off-by: Lucas Coutinho Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 5 --- target/ppc/insn32.decode| 8 target/ppc/int_helper.c | 15 target/ppc/translate/vmx-impl.c.inc | 58

[PATCH v5 21/49] target/ppc: implement vsrq

From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 1 + target/ppc/translate/vmx-impl.c.inc | 40 + 2 files changed, 31 insertions(+), 10 deletions(-) diff --git a/target/ppc/insn32.decode b

[PATCH v5 15/49] target/ppc: implement vclrlb

From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 2 ++ target/ppc/translate/vmx-impl.c.inc | 40 + 2 files changed, 42 insertions(+) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32

[PATCH v5 12/49] target/ppc: Implement Vector Compare Greater Than Quadword

From: Matheus Ferst Implement the following PowerISA v3.1 instructions: vcmpgtsq: Vector Compare Greater Than Signed Quadword vcmpgtuq: Vector Compare Greater Than Unsigned Quadword Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 2

[PATCH v5 22/49] target/ppc: implement vsraq

From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 1 + target/ppc/translate/vmx-impl.c.inc | 23 +-- 2 files changed, 18 insertions(+), 6 deletions(-) diff --git a/target/ppc/insn32.decode b/target

[PATCH v5 16/49] target/ppc: implement vclrrb

From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 1 + target/ppc/translate/vmx-impl.c.inc | 32 + 2 files changed, 25 insertions(+), 8 deletions(-) diff --git a/target/ppc/insn32.decode b

[PATCH v5 25/49] target/ppc: implement vrlq

From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 1 + target/ppc/translate/vmx-impl.c.inc | 48 + 2 files changed, 49 insertions(+) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32

[PATCH v5 11/49] target/ppc: Implement Vector Compare Equal Quadword

From: Matheus Ferst Implement the following PowerISA v3.1 instructions: vcmpequq: Vector Compare Equal Quadword Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 1 + target/ppc/translate/vmx-impl.c.inc

[PATCH v5 24/49] target/ppc: move vrl[bhwd]nm/vrl[bhwd]mi to decodetree

From: Matheus Ferst Signed-off-by: Matheus Ferst --- I couldn't figure out how to use tcg_gen_gvec_rotlv here. Since the code is in the fniv implementation, we have TCGv_vec instead of offsets. I'm keeping the masking for now, so the generated code has the desired effect. ---

[PATCH v5 26/49] target/ppc: implement vrlqnm

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 1 + target/ppc/translate/vmx-impl.c.inc | 81 +++-- 2 files changed, 77 insertions(+), 5 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index

[PATCH v5 14/49] target/ppc: implement vstri[bh][lr]

From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 4 target/ppc/insn32.decode| 10 ++ target/ppc/int_helper.c | 28 +++ target/ppc/translate/vmx-impl.c.inc

[PATCH v5 32/49] target/ppc: Implement xxpermx instruction

From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 1 + target/ppc/insn64.decode| 8 target/ppc/int_helper.c | 20 target/ppc/translate/vsx-impl.c.inc | 22

[PATCH v5 27/49] target/ppc: implement vrlqmi

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 1 + target/ppc/translate/vmx-impl.c.inc | 21 + 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 87d482c5d9

[PATCH v5 35/49] target/ppc: Implement xxgenpcv[bhwd]m instruction

From: Matheus Ferst Signed-off-by: Matheus Ferst --- v5: - One helper for each IMM value. --- target/ppc/helper.h | 16 + target/ppc/insn32.decode| 10 target/ppc/int_helper.c | 91 + target/ppc/translate/vsx

[PATCH v5 34/49] target/ppc: Implement xxeval

From: Matheus Ferst Signed-off-by: Matheus Ferst --- v5: - Some equivalent functions implemented with tcg_gen_gvec_* --- target/ppc/helper.h | 1 + target/ppc/insn64.decode| 8 + target/ppc/int_helper.c | 42 ++ target/ppc/translate/vsx

[PATCH v5 17/49] target/ppc: implement vcntmb[bhwd]

From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 8 target/ppc/translate/vmx-impl.c.inc | 32 + 2 files changed, 40 insertions(+) diff --git a/target/ppc/insn32.decode b/target/ppc

[PATCH v5 30/49] target/ppc: move xxperm/xxpermr to decodetree

From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 21 --- target/ppc/helper.h | 2 -- target/ppc/insn32.decode| 5 target/ppc/translate/vsx-impl.c.inc | 42

[PATCH v5 18/49] target/ppc: implement vgnb

From: Matheus Ferst Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 5 ++ target/ppc/translate/vmx-impl.c.inc | 135 2 files changed, 140 insertions(+) diff --git a/target

[PATCH v5 38/49] target/ppc: Implement xvtlsbb instruction

From: Víctor Colombo Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- changes for v5: - unroll for-loop as suggested by Richard Henderson --- target/ppc/insn32.decode| 7 + target/ppc/translate/vsx-impl.c.inc | 40 + 2 files changed

[PATCH v5 31/49] target/ppc: Move xxpermdi to decodetree

From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 4 ++ target/ppc/translate/vsx-impl.c.inc | 71 + target/ppc/translate/vsx-ops.c.inc | 2 - 3 files changed, 36 insertions(+), 41 deletions

[PATCH v5 41/49] target/ppc: Implement xscmp{eq,ge,gt}qp

From: Víctor Colombo Reviewed-by: Richard Henderson Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 3 +++ target/ppc/helper.h | 3 +++ target/ppc/insn32.decode| 3 +++ target/ppc/translate/vsx-impl.c.inc

[PATCH v5 43/49] target/ppc: Move xs{max, min}[cj]dp to use do_helper_XX3

From: Víctor Colombo Also, fixes these instructions not being capitalized. Reviewed-by: Richard Henderson Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 8 target/ppc/helper.h | 8 target/ppc/translate

[PATCH v5 20/49] target/ppc: implement vslq

From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 1 + target/ppc/translate/vmx-impl.c.inc | 40 + 2 files changed, 41 insertions(+) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32

[PATCH v5 47/49] target/ppc: implement plxsd/pstxsd

From: Leandro Lupori Implement instructions plxsd/pstxsd and port lxsd/stxsd to decode tree. Reviewed-by: Richard Henderson Signed-off-by: Leandro Lupori Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 2 ++ target/ppc/insn64.decode| 10 ++ target/ppc

[PATCH v5 36/49] target/ppc: move xs[n]madd[am][ds]p/xs[n]msub[am][ds]p to decodetree

From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 23 ++-- target/ppc/helper.h | 16 - target/ppc/insn32.decode| 22 target/ppc/translate/vsx-impl.c.inc | 56

[PATCH v5 23/49] target/ppc: move vrl[bhwd] to decodetree

From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 5 + target/ppc/translate/vmx-impl.c.inc | 13 + target/ppc/translate/vmx-ops.c.inc | 6 ++ 3 files changed, 12 insertions(+), 12 deletions(-) diff

[PATCH v5 45/49] target/ppc: Implement xs{max,min}cqp

From: Víctor Colombo Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- changes for v5: - Update the helper macro call with the new parameters added to VSX_MAX_MINC --- target/ppc/fpu_helper.c | 2 ++ target/ppc/helper.h | 2 ++ target/ppc/insn32

[PATCH v5 49/49] target/ppc: implement lxvr[bhwd]/stxvr[bhwd]x

Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 8 +++ target/ppc/translate/vsx-impl.c.inc | 35 + 2 files changed, 43 insertions(+) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 1641a31894..ac2d3da9a7 100644 --- a

[PATCH v5 28/49] target/ppc: Move vsel and vperm/vpermr to decodetree

From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 5 +-- target/ppc/insn32.decode| 5 +++ target/ppc/int_helper.c | 13 +- target/ppc/translate/vmx-impl.c.inc | 69

[PATCH v5 46/49] target/ppc: Implement xvcvbf16spn and xvcvspbf16 instructions

From: Víctor Colombo Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 18 + target/ppc/helper.h | 1 + target/ppc/insn32.decode| 11 +++--- target/ppc/translate/vsx-impl.c.inc | 31

[PATCH v5 29/49] target/ppc: Move xxsel to decodetree

From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 6 target/ppc/insn64.decode| 24 target/ppc/translate/vsx-impl.c.inc | 20 ++ target/ppc/translate/vsx-ops.c.inc | 43

[PATCH v5 33/49] tcg/tcg-op-gvec.c: Introduce tcg_gen_gvec_4i

From: Matheus Ferst Following the implementation of tcg_gen_gvec_3i, add a four-vector and immediate operand expansion method. Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- include/tcg/tcg-op-gvec.h | 22 ++ tcg/tcg-op-gvec.c | 146

[PATCH v5 37/49] target/ppc: implement xs[n]maddqp[o]/xs[n]msubqp[o]

From: Matheus Ferst Implement the following PowerISA v3.0 instuctions: xsmaddqp[o]: VSX Scalar Multiply-Add Quad-Precision [using round to Odd] xsmsubqp[o]: VSX Scalar Multiply-Subtract Quad-Precision [using round to Odd] xsnmaddqp[o]: VSX Scalar Negative Multiply-Add Quad-Precision

[PATCH v5 39/49] target/ppc: Remove xscmpnedp instruction

From: Víctor Colombo xscmpnedp was added in ISA v3.0 but removed in v3.0B. This patch removes this instruction as it was not in the final version of v3.0. Signed-off-by: Víctor Colombo Acked-by: Greg Kurz Reviewed-by: Cédric Le Goater Reviewed-by: Richard Henderson Signed-off-by: Matheus

[PATCH v5 40/49] target/ppc: Refactor VSX_SCALAR_CMP_DP

From: Víctor Colombo Refactor VSX_SCALAR_CMP_DP, changing its name to VSX_SCALAR_CMP and prepare the helper to be used for quadword comparisons. Suggested-by: Richard Henderson Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- changes for v5: - Improve refactor as suggested by

[PATCH v5 42/49] target/ppc: Move xscmp{eq,ge,gt}dp to decodetree

From: Víctor Colombo Reviewed-by: Richard Henderson Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 6 +++--- target/ppc/helper.h | 6 +++--- target/ppc/insn32.decode| 3 +++ target/ppc/translate/vsx

[PATCH v5 44/49] target/ppc: Refactor VSX_MAX_MINC helper

From: Víctor Colombo Refactor xs{max,min}cdp VSX_MAX_MINC helper to prepare for xs{max,min}cqp implementation. Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- changes for v5: - use float_flag_invalid_snan as suggested by Richard Henderson --- target/ppc/fpu_helper.c | 41

[PATCH v5 48/49] target/ppc: implement plxssp/pstxssp

From: Leandro Lupori Implement instructions plxssp/pstxssp and port lxssp/stxssp to decode tree. Reviewed-by: Richard Henderson Signed-off-by: Leandro Lupori Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 2 + target/ppc/insn64.decode| 6 ++ target/ppc

[PATCH v2 0/5] tests/tcg/ppc64le: fix the build of TCG tests with Clang

From: Matheus Ferst As the configuration scripts used -mbig and -mlittle, building PPC tests with Clang was silently skipped. With the patch to fix these options[1], "make check-tcg" fails because of build and runtime errors. This patch series tries to fix some of these problems.

[PATCH v2 1/5] tests/tcg/ppc64le: use inline asm instead of __builtin_mtfsf

From: Matheus Ferst LLVM/Clang does not support __builtin_mtfsf. Acked-by: Alex Bennée Signed-off-by: Matheus Ferst --- tests/tcg/ppc64le/mtfsf.c | 19 +-- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/tests/tcg/ppc64le/mtfsf.c b/tests/tcg/ppc64le/mtfsf.c

[PATCH v2 2/5] target/ppc: change xs[n]madd[am]sp to use float64r32_muladd

From: Matheus Ferst Change VSX Scalar Multiply-Add/Subtract Type-A/M Single Precision helpers to use float64r32_muladd. This method should correctly handle all rounding modes, so the workaround for float_round_nearest_even can be dropped. Reviewed-by: Richard Henderson Signed-off-by: Matheus

[RFC PATCH v2 4/5] tests/tcg/ppc64le: emit bcdsub with .long when needed

From: Matheus Ferst Based on GCC docs[1], we use the '-mpower8-vector' flag at config-time to detect the toolchain support to the bcdsub instruction. LLVM/Clang supports this flag since version 3.6[2], but the instruction and related builtins were only added in LLVM 14[3]. In the

[RFC PATCH v2 3/5] tests/tcg/ppc64le: drop __int128 usage in bcdsub

From: Matheus Ferst Using __int128 with inline asm constraints like "v" generates incorrect code when compiling with LLVM/Clang (e.g., only one doubleword of the VSR is loaded). Instead, use a GPR pair to pass the 128-bits value and load the VSR with mtvsrd/xxmrghd. Signed-off-by: Mat

[PATCH v2 5/5] tests/tcg/ppc64le: Use Altivec register names in clobbler list

From: Matheus Ferst LLVM/Clang doesn't know the VSX registers when compiling with -mabi=elfv1. Use only registers >= 32 and list them with their Altivec name. Signed-off-by: Matheus Ferst --- tests/tcg/ppc64le/non_signalling_xscv.c | 16 1 file changed, 8 insertio

[RFC PATCH 1/3] tests/tcg/ppc64le: use inline asm instead of __builtin_mtfsf

From: Matheus Ferst LLVM/Clang does not support __builtin_mtfsf. Signed-off-by: Matheus Ferst --- tests/tcg/ppc64le/mtfsf.c | 19 +-- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/tests/tcg/ppc64le/mtfsf.c b/tests/tcg/ppc64le/mtfsf.c index b3d31f3637

[RFC PATCH 3/3] tests/tcg/ppc64le: Use vector types instead of __int128

From: Matheus Ferst LLVM/Clang doesn't like inline asm with __int128, use a vector type instead. Signed-off-by: Matheus Ferst --- Alternatively, we could pass VSR values in GPR pairs, as we did in tests/tcg/ppc64le/non_signalling_xscv.c --- tests/tcg/ppc64le/bcdsub.c

[RFC PATCH 0/3] tests/tcg/ppc64le: fix the build of TCG tests with Clang

From: Matheus Ferst Based-on: https://lists.gnu.org/archive/html/qemu-devel/2022-01/msg06506.html As the configuration scripts used -mbig and -mlittle, building PPC tests with Clang was silently skipped. With the patch to fix these options[1], "make check-tcg" fails because of build a

[RFC PATCH 2/3] target/ppc: change xs[n]madd[am]sp to use float64r32_muladd

From: Matheus Ferst Change VSX Scalar Multiply-Add/Subtract Type-A/M Single Precision helpers to use float64r32_muladd. This method should correctly handle all rounding modes, so the workaround for float_round_nearest_even can be dropped. Signed-off-by: Matheus Ferst --- target/ppc

[PATCH] configure: fix parameter expansion of --cross-cc-cflags options

From: Matheus Ferst Without this fix, any use of --cross-cc-cflags-* causes a message like: $ ../configure --cross-cc-ppc64le=clang --cross-cc-cflags-ppc64le="-target powerpc64le-unknown-linux-gnu -sysroot ..." ../configure: 1: eval: cross_cc_cflags_--cross-cc-cflags-ppc64le=-target:

[PATCH v2 04/38] target/ppc: vmulh* instructions use gvec

From: "Lucas Mateus Castro (alqotel)" Changed vmulhuw, vmulhud, vmulhsw, vmulhsd to use gvec instructions Signed-off-by: Lucas Mateus Castro (alqotel) Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 8 +- target/ppc/int_helper.c | 8 +-

[PATCH v2 07/38] target/ppc: Move vexts[bhw]2[wd] to decodetree

Doubleword Signed-off-by: Lucas Coutinho Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 5 - target/ppc/insn32.decode| 8 target/ppc/int_helper.c | 15 --- target/ppc/translate/vmx-impl.c.inc | 25

[PATCH v2 05/38] target/ppc: Implement vmsumcud instruction

From: Víctor Colombo Based on [1] by Lijun Pan , which was never merged into master. [1]: https://lists.gnu.org/archive/html/qemu-ppc/2020-07/msg00419.html Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 4 +++ target/ppc/translate/vmx

[PATCH v2 08/38] target/ppc: Implement vextsd2q

From: Lucas Coutinho Signed-off-by: Lucas Coutinho Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 1 + target/ppc/translate/vmx-impl.c.inc | 18 ++ 2 files changed, 19 insertions(+) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode

[PATCH v2 09/38] target/ppc: Move Vector Compare Equal/Not Equal/Greater Than to decodetree

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 30 -- target/ppc/insn32.decode| 24 target/ppc/int_helper.c | 54 - target/ppc/translate/vmx-impl.c.inc | 91

[PATCH v2 06/38] target/ppc: Implement vmsumudm instruction

From: Víctor Colombo Based on [1] by Lijun Pan , which was never merged into master. [1]: https://lists.gnu.org/archive/html/qemu-ppc/2020-07/msg00419.html Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 1 + target/ppc/translate/vmx

[PATCH v2 11/38] target/ppc: Implement Vector Compare Equal Quadword

From: Matheus Ferst Implement the following PowerISA v3.1 instructions: vcmpequq Vector Compare Equal Quadword Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 1 + target/ppc/translate/vmx-impl.c.inc | 43 + 2 files changed, 44 insertions

[PATCH v2 14/38] target/ppc: implement vstri[bh][lr]

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 4 target/ppc/insn32.decode| 10 + target/ppc/int_helper.c | 32 + target/ppc/translate/vmx-impl.c.inc | 24 ++ 4

[PATCH v2 18/38] target/ppc: implement vgnb

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 5 target/ppc/translate/vmx-impl.c.inc | 44 + 2 files changed, 49 insertions(+) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 0a3e39f3e9

[PATCH v2 12/38] target/ppc: Implement Vector Compare Greater Than Quadword

From: Matheus Ferst Implement the following PowerISA v3.1 instructions: vcmpgtsq: Vector Compare Greater Than Signed Quadword vcmpgtuq: Vector Compare Greater Than Unsigned Quadword Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 2 ++ target/ppc/translate/vmx

[PATCH v2 22/38] target/ppc: Move xxpermdi to decodetree

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 4 ++ target/ppc/translate/vsx-impl.c.inc | 71 + target/ppc/translate/vsx-ops.c.inc | 2 - 3 files changed, 36 insertions(+), 41 deletions(-) diff --git a/target/ppc

[PATCH v2 15/38] target/ppc: implement vclrlb

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 2 ++ target/ppc/translate/vmx-impl.c.inc | 56 + 2 files changed, 58 insertions(+) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index ea497ecd80

[PATCH v2 19/38] target/ppc: Move vsel and vperm/vpermr to decodetree

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 5 +-- target/ppc/insn32.decode| 5 +++ target/ppc/int_helper.c | 13 +- target/ppc/translate/vmx-impl.c.inc | 69 ++--- target/ppc/translate/vmx

[PATCH v2 24/38] tcg/tcg-op-gvec.c: Introduce tcg_gen_gvec_4i

From: Matheus Ferst Following the implementation of tcg_gen_gvec_3i, add a four-vector and immediate operand expansion method. Signed-off-by: Matheus Ferst --- include/tcg/tcg-op-gvec.h | 22 ++ tcg/tcg-op-gvec.c | 146 ++ 2 files changed, 168

[PATCH v2 13/38] target/ppc: Implement Vector Compare Quadword

From: Matheus Ferst Implement the following PowerISA v3.1 instructions: vcmpsq: Vector Compare Signed Quadword vcmpuq: Vector Compare Unsigned Quadword Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 6 target/ppc/translate/vmx-impl.c.inc | 45

[PATCH v2 25/38] target/ppc: Implement xxeval

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 1 + target/ppc/insn64.decode| 8 ++ target/ppc/int_helper.c | 42 ++ target/ppc/translate/vsx-impl.c.inc | 121 4 files changed, 172

[PATCH v2 17/38] target/ppc: implement vcntmb[bhwd]

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 8 target/ppc/translate/vmx-impl.c.inc | 32 + 2 files changed, 40 insertions(+) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index bf2f3b1e0b

[PATCH v2 26/38] target/ppc: Implement xxgenpcv[bhwd]m instruction

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 4 ++ target/ppc/insn32.decode| 10 target/ppc/int_helper.c | 84 + target/ppc/translate/vsx-impl.c.inc | 29 ++ 4 files changed, 127

[PATCH v2 16/38] target/ppc: implement vclrrb

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 1 + target/ppc/translate/vmx-impl.c.inc | 43 +++-- 2 files changed, 35 insertions(+), 9 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index

[PATCH v2 20/38] target/ppc: Move xxsel to decodetree

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 6 target/ppc/insn64.decode| 24 target/ppc/translate/vsx-impl.c.inc | 20 ++ target/ppc/translate/vsx-ops.c.inc | 43 - 4

[PATCH v2 27/38] target/ppc: move xs[n]madd[am][ds]p/xs[n]msub[am][ds]p to decodetree

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 23 ++-- target/ppc/helper.h | 16 - target/ppc/insn32.decode| 22 target/ppc/translate/vsx-impl.c.inc | 56 - target

[PATCH v2 21/38] target/ppc: move xxperm/xxpermr to decodetree

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 21 --- target/ppc/helper.h | 2 -- target/ppc/insn32.decode| 5 target/ppc/translate/vsx-impl.c.inc | 42 +++-- target/ppc

[PATCH v2 23/38] target/ppc: Implement xxpermx instruction

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 1 + target/ppc/insn64.decode| 8 target/ppc/int_helper.c | 20 target/ppc/translate/vsx-impl.c.inc | 22 ++ 4 files changed

[PATCH v2 28/38] target/ppc: implement xs[n]maddqp[o]/xs[n]msubqp[o]

From: Matheus Ferst Implement the following PowerISA v3.0 instuctions: xsmaddqp[o]: VSX Scalar Multiply-Add Quad-Precision [using round to Odd] xsmsubqp[o]: VSX Scalar Multiply-Subtract Quad-Precision [using round to Odd] xsnmaddqp[o]: VSX Scalar Negative Multiply-Add Quad-Precision

[PATCH v2 33/38] target/ppc: Implement do_helper_XX3 and move xxperm* to use it

From: Víctor Colombo do_helper_XX3 is a wrapper for instructions that only call its helper. It will be used later to implement instructions like xscmp*dp. Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/translate/vsx-impl.c.inc | 26 +- 1

[PATCH v2 29/38] target/ppc: Implement xvtlsbb instruction

From: Víctor Colombo Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 7 ++ target/ppc/translate/vsx-impl.c.inc | 37 + 2 files changed, 44 insertions(+) diff --git a/target/ppc/insn32.decode b/target/ppc

[PATCH v2 31/38] target/ppc: Refactor VSX_SCALAR_CMP_DP

From: Víctor Colombo Refactor VSX_SCALAR_CMP_DP, changing its name to VSX_SCALAR_CMP and prepare the helper to be used for quadword comparisons. Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 31 ++- 1 file changed, 14

  1   2   3   4   5   6   7   >