On 2023/3/24 13:59, LIU Zhiwei wrote:
Once we mistook the vstart directly from the env->vstart. As env->vstart is not
a constant, we should record it in the tb flags if we want to use
it in translation.
Reported-by: Richard Henderson
Signed-off-by: LIU Zhiwei
---
Reviewed-by: Weiwei Li
We
On 2023/3/24 13:59, LIU Zhiwei wrote:
The pointer masking is the only extension that directly use status.
The vector or float extension uses the status in an indirect way.
Replace the pointer masking extension special status fields with
the general status.
Signed-off-by: LIU Zhiwei
---
tar
On 2023/3/24 14:40, LIU Zhiwei wrote:
When I boot a ubuntu image, QEMU output a "Bad icount read" message and exit.
The reason is that when execute helper_mret or helper_sret, it will
cause a call to icount_get_raw_locked (), which needs set can_do_io flag
on cpustate.
Thus we setting this fla
On 2023/3/24 13:59, LIU Zhiwei wrote:
Reuse the MSTATUS_FS and MSTATUS_VS for the tb flags positions is not a normal
way.
It will make us change the tb flags layout difficult. And even worse, if we
want to keep tb flags for a same extension togather without a hole.
Signed-off-by: LIU Zhiwei
On 2023/3/23 06:19, Daniel Henrique Barboza wrote:
riscv_cpu_disable_priv_spec_isa_exts(), at the end of
riscv_cpu_validate_set_extensions(), will disable cpu->cfg.ext_h and
cpu->cfg.ext_v if priv_ver check fails.
This check can be done in riscv_cpu_validate_misa_ext(). The difference
here is
Ping!
Several updates have been applied to the support of Zc* extensions after
v9 was dropped from the riscv-to-apply.next list.
Any new comments for them?
Regards,
Weiwei Li
On 2023/3/7 16:13, Weiwei Li wrote:
This patchset implements RISC-V Zc* extension v1.0.3-1 version instructions.
S
On 2023/3/23 06:20, Daniel Henrique Barboza wrote:
write_misa() is able to use the same validation workflow
riscv_cpu_realize() uses. But it's still not capable of updating
cpu->cfg misa props yet.
We have no way of blocking future (and current) code from checking
env->misa_ext (via riscv_has_e
On 2022/11/21 07:35, Alistair Francis wrote:
On Sun, Oct 16, 2022 at 11:09 PM Mayuresh Chitale
wrote:
If smstateen is implemented and sstateen0.fcsr is clear then the floating point
operations must return illegal instruction exception or virtual instruction
trap, if relevant.
Signed-off-by:
On 2023/3/23 06:19, Daniel Henrique Barboza wrote:
We can set all RVG related extensions during realize time, before
validate_set_extensions() itself. Put it in a separated function so the
validate function already uses the updated state.
Note that we're setting both cfg->ext_N and env->misa_e
On 2023/3/23 06:20, Daniel Henrique Barboza wrote:
write_misa() must use as much common logic as possible. We want to open
code just the bits that are exclusive to the CSR write operation and TCG
internals.
Rewrite write_misa() to work as follows:
- mask the write using misa_ext_mask to avoid
On 2023/3/24 13:59, LIU Zhiwei wrote:
Virt enabled state is not a constant. So we should put it into tb flags.
Thus we can use it like a constant condition at translation phase.
Reported-by: Richard Henderson
Signed-off-by: LIU Zhiwei
---
Reviewed-by: Weiwei Li
Weiwei L
target/riscv/c
On 2023/3/23 06:20, Daniel Henrique Barboza wrote:
Similar to what we did with riscv_cpu_validate_misa_ext(), let's read
all MISA bits from a misa_ext val instead of reading from the cpu->cfg
object.
This will allow write_misa() to use riscv_cpu_validate_extensions().
Signed-off-by: Daniel He
On 2023/3/23 06:19, Daniel Henrique Barboza wrote:
The 'G' bit in misa_ext is a virtual extension that enables a set of
extensions (i, m, a, f, d, icsr and ifencei). We're already have code to
handle it but no bit definition. Add it.
Add RVG to set_misa() in rv64_thead_c906_cpu_init() and remo
On 2023/3/25 22:23, LIU Zhiwei wrote:
On 2023/3/24 20:38, Weiwei Li wrote:
Fix identation problems, and try to use the same indentation strategy
in the same file.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/arch_dump.c | 4 +-
target/riscv/cpu
On 2023/3/25 18:54, Richard Henderson wrote:
From: LIU Zhiwei
The pointer masking is the only extension that directly use status.
The vector or float extension uses the status in an indirect way.
Replace the pointer masking extension special status fields with
the general status.
Reviewed-b
On 2023/3/25 18:54, Richard Henderson wrote:
This builds on Fei and Zhiwei's SUM and TB_FLAGS changes.
* Reclaim 5 TB_FLAGS bits, since we nearly ran out.
* Using cpu_mmu_index(env, true) is insufficient to implement
HLVX properly. While that chooses the correct mmu_idx, it
do
On 2023/3/25 22:53, LIU Zhiwei wrote:
Currently we only use the env->virt to encode the virtual mode enabled
status. Let's make it a bool type.
Signed-off-by: LIU Zhiwei
---
I'm not quite sure the original reason to use a int for virt.
However, this change is acceptable to me.
Reviewed-by
On 2023/3/25 18:54, Richard Henderson wrote:
Merge with mstatus_{fs,vs}. We might perform a redundant
assignment to one or the other field, but it's a trivial
and saves 4 bits from TB_FLAGS.
Signed-off-by: Richard Henderson
---
target/riscv/cpu.h| 16 +++-
target/riscv
On 2023/3/27 16:00, Christoph Muellner wrote:
From: Christoph Müllner
This patch introduces the RISC-V Zfa extension, which introduces
additional floating-point extensions:
* fli (load-immediate) with pre-defined immediates
* fminm/fmaxm (like fmin/fmax but with different NaN behaviour)
* fro
On 2023/3/28 02:04, Richard Henderson wrote:
On 3/27/23 03:00, Weiwei Li wrote:
@@ -1248,6 +1265,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr
address, int size,
qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx
%d\n",
__func__, address, access_typ
On 2023/3/28 10:20, LIU Zhiwei wrote:
On 2023/3/27 18:00, Weiwei Li wrote:
Since pointer mask works on effective address, and the xl works on the
generation of effective address, so xl related calculation should be
done
before pointer mask.
Incorrect. It has been done.
When updating the
On 2023/3/28 10:14, LIU Zhiwei wrote:
On 2023/3/27 18:00, Weiwei Li wrote:
Currently, the pc use signed-extend(in gen_set_pc*) when xl = 32. And
data address should use the same memory address space with it when
xl = 32. So we should change their address calculation to use sign-extended
addre
On 2023/3/28 10:31, LIU Zhiwei wrote:
On 2023/3/28 9:55, liweiwei wrote:
On 2023/3/28 02:04, Richard Henderson wrote:
On 3/27/23 03:00, Weiwei Li wrote:
@@ -1248,6 +1265,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr
address, int size,
qemu_log_mask(CPU_LOG_MMU, "
On 2023/3/28 11:18, Richard Henderson wrote:
On 3/27/23 19:48, liweiwei wrote:
On 2023/3/28 10:20, LIU Zhiwei wrote:
On 2023/3/27 18:00, Weiwei Li wrote:
Since pointer mask works on effective address, and the xl works on the
generation of effective address, so xl related calculation should
On 2023/3/28 11:31, Richard Henderson wrote:
On 3/27/23 18:55, liweiwei wrote:
On 2023/3/28 02:04, Richard Henderson wrote:
On 3/27/23 03:00, Weiwei Li wrote:
@@ -1248,6 +1265,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr
address, int size,
qemu_log_mask(CPU_LOG_MMU, "
On 2023/3/28 15:25, LIU Zhiwei wrote:
On 2023/3/28 11:33, liweiwei wrote:
On 2023/3/28 11:18, Richard Henderson wrote:
On 3/27/23 19:48, liweiwei wrote:
On 2023/3/28 10:20, LIU Zhiwei wrote:
On 2023/3/27 18:00, Weiwei Li wrote:
Since pointer mask works on effective address, and the xl
On 2023/3/28 06:49, Daniel Henrique Barboza wrote:
The code that disables extensions if there's a priv version mismatch
uses cpu->cfg.ext_N properties to do its job.
We're aiming to not rely on cpu->cfg.ext_N props for MISA bits. Split
the MISA related verifications in a new function, removing
On 2023/3/29 01:35, Daniel Henrique Barboza wrote:
We have 4 config settings being done in riscv_cpu_init(): ext_ifencei,
ext_icsr, mmu and pmp. This is also the constructor of the "riscv-cpu"
device, which happens to be the parent device of every RISC-V cpu.
The result is that these 4 configs
On 2023/3/29 01:35, Daniel Henrique Barboza wrote:
write_misa() must use as much common logic as possible. We want to open
code just the bits that are exclusive to the CSR write operation and TCG
internals.
Our validation is done with riscv_cpu_validate_set_extensions(), but we
need a small tw
On 2023/3/29 00:54, Irina Ryapolova wrote:
According to specification:
For Sv39x4, address bits of the guest physical address 63:41 must all be zeros,
or else a
guest-page-fault exception occurs.
Likewise for Sv48x4 and Sv57x4.
For Sv48x4 address bits 63:50 must all be zeros, or else a guest-
On 2023/3/29 23:33, Richard Henderson wrote:
On 3/28/23 20:23, Weiwei Li wrote:
We should sync cpu_pc before storing it into badaddr when mis-aligned
exception is triggered.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/insn_trans/trans_rvi.c.inc | 1 +
target/ri
On 2023/3/30 00:27, Richard Henderson wrote:
On 3/28/23 20:23, Weiwei Li wrote:
static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
{
- gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next);
+ assert(ctx->pc_save != -1);
+ if (tb_cflags(ctx->base.tb) & CF_PCREL) {
+ TCG
On 2023/3/30 00:36, Richard Henderson wrote:
On 3/28/23 20:23, Weiwei Li wrote:
Transform the fetch address in cpu_get_tb_cpu_state() when pointer
mask for instruction is enabled.
Enable PC-relative translation when J is enabled.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
t
On 2023/3/30 01:28, Daniel Henrique Barboza wrote:
We don't have MISA extensions in isa_edata_arr[] anymore. Remove the
redundant 'multi_letter' field from isa_ext_data.
Suggested-by: Weiwei Li
Signed-off-by: Daniel Henrique Barboza
---
Reviewed-by: Weiwei Li
Weiwei Li
target/riscv/cpu
On 2023/4/1 12:51, Richard Henderson wrote:
Assign pc and use store_release to assign tb.
Fixes: 2dd5b7a1b91 ("accel/tcg: Move jmp-cache `CF_PCREL` checks to caller")
Reported-by: Weiwei Li
Signed-off-by: Richard Henderson
---
accel/tcg/cpu-exec.c | 17 +
1 file changed, 1
On 2023/4/1 20:39, Weiwei Li wrote:
This patchset tries to fix some problem in current implementation for pointer
mask, and add support for pointer mask of instruction fetch.
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-pm-fix-v5
v2:
* drop some error patchs
* A
On 2023/4/2 08:34, LIU Zhiwei wrote:
On 2023/4/1 20:49, Weiwei Li wrote:
Add a base save_pc For
pc_save for
PC-relative translation(CF_PCREL).
Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb.
Sync pc before it's used or updated from tb related pc:
real_pc = (old)env
On 2023/4/2 21:17, LIU Zhiwei wrote:
On 2023/4/2 16:17, liweiwei wrote:
On 2023/4/2 08:34, LIU Zhiwei wrote:
On 2023/4/1 20:49, Weiwei Li wrote:
Add a base save_pc For
pc_save for
PC-relative translation(CF_PCREL).
Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb
On 2023/4/3 02:00, Richard Henderson wrote:
On 4/2/23 06:17, LIU Zhiwei wrote:
Why set pc_save here? IMHO, pc_save is a constant.
pc_save is a value which is strictly related to the value of env->pc.
real_pc = (old)env->pc + target_pc(from tb) - ctx->pc_save
In this formula, the meaning o
On 2023/4/2 21:53, liweiwei wrote:
On 2023/4/2 21:17, LIU Zhiwei wrote:
On 2023/4/2 16:17, liweiwei wrote:
On 2023/4/2 08:34, LIU Zhiwei wrote:
On 2023/4/1 20:49, Weiwei Li wrote:
Add a base save_pc For
pc_save for
PC-relative translation(CF_PCREL).
Diable the directly sync pc from
On 2023/4/3 16:09, Philippe Mathieu-Daudé wrote:
On 1/4/23 06:51, Richard Henderson wrote:
From: Weiwei Li
CPUs often set CF_PCREL in tcg_cflags before qemu_init_vcpu(), in which
tcg_cflags will be overwrited by tcg_cpu_init_cflags().
The description makes sense, but I couldn't reproduce u
On 2023/4/4 09:58, LIU Zhiwei wrote:
On 2023/4/1 20:49, Weiwei Li wrote:
Add a base save_pc For PC-relative translation(CF_PCREL).
Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb.
Sync pc before it's used or updated from tb related pc:
real_pc = (old)env->pc + target_
On 2023/4/4 11:06, LIU Zhiwei wrote:
On 2023/4/4 10:06, Weiwei Li wrote:
Compute the target address before storing it into badaddr
when mis-aligned exception is triggered.
Use a target_pc temp to store the target address to avoid
the confusing operation that udpate target address into
cpu_pc
On 2023/4/4 11:12, LIU Zhiwei wrote:
On 2023/4/4 10:06, Weiwei Li wrote:
Add a base pc_save for PC-relative translation(CF_PCREL).
Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb.
We can get pc-relative address from following formula:
real_pc = (old)env->pc + diff, whe
On 2023/4/4 15:07, LIU Zhiwei wrote:
On 2023/4/4 11:46, liweiwei wrote:
On 2023/4/4 11:12, LIU Zhiwei wrote:
On 2023/4/4 10:06, Weiwei Li wrote:
Add a base pc_save for PC-relative translation(CF_PCREL).
Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb.
We can get pc
On 2023/4/4 21:56, Richard Henderson wrote:
On 4/3/23 19:06, Weiwei Li wrote:
static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
{
- gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next);
+ TCGv target_pc = dest_gpr(ctx, a->rd);
+ gen_pc_plus_diff(target_pc, ctx, a->imm + ctx-
On 2023/4/4 22:57, Richard Henderson wrote:
On 4/4/23 07:33, liweiwei wrote:
If we want to hide all of them in gen_pc_plus_diff, then we need
calculate the diff for pc_succ_insn or introduce a new API for it,
since we need get the successor pc in many instructions.
And the logic for
On 2023/4/4 23:27, Richard Henderson wrote:
On 4/4/23 08:14, liweiwei wrote:
On 2023/4/4 22:57, Richard Henderson wrote:
On 4/4/23 07:33, liweiwei wrote:
If we want to hide all of them in gen_pc_plus_diff, then we need
calculate the diff for pc_succ_insn or introduce a new API for it
On 2023/4/6 08:43, Alistair Francis wrote:
On Thu, Mar 30, 2023 at 11:59 PM Weiwei Li wrote:
The MPP will be set to the least-privileged supported mode (U if
U-mode is implemented, else M).
I don't think this is right, the spec in section 8.6.4 says this:
Sorry, I didn't find this section i
On 2023/4/6 08:36, Alistair Francis wrote:
On Wed, Apr 5, 2023 at 7:58 PM Weiwei Li wrote:
Add signature and signature-granularity properties in spike to specify the
target
signatrue file and the line size for signature data.
Recgonize the signature section between begin_signature and end_s
On 2023/4/6 09:26, Alistair Francis wrote:
On Thu, Mar 30, 2023 at 11:59 PM Weiwei Li wrote:
mstatus.MPP field is a WARL field, so we remain it unchanged if an
Only since version 1.11 of the priv spec and we do still support priv 1.10.
I think it's ok to make this change for all priv versio
On 2023/4/6 09:46, Alistair Francis wrote:
On Thu, Apr 6, 2023 at 10:56 AM liweiwei wrote:
On 2023/4/6 08:43, Alistair Francis wrote:
On Thu, Mar 30, 2023 at 11:59 PM Weiwei Li wrote:
The MPP will be set to the least-privileged supported mode (U if
U-mode is implemented, else M).
I
On 2023/4/6 10:24, Alistair Francis wrote:
On Thu, Apr 6, 2023 at 12:14 PM liweiwei wrote:
On 2023/4/6 09:46, Alistair Francis wrote:
On Thu, Apr 6, 2023 at 10:56 AM liweiwei wrote:
On 2023/4/6 08:43, Alistair Francis wrote:
On Thu, Mar 30, 2023 at 11:59 PM Weiwei Li wrote:
The MPP
On 2023/4/6 10:24, Alistair Francis wrote:
On Thu, Apr 6, 2023 at 12:14 PM liweiwei wrote:
On 2023/4/6 09:46, Alistair Francis wrote:
On Thu, Apr 6, 2023 at 10:56 AM liweiwei wrote:
On 2023/4/6 08:43, Alistair Francis wrote:
On Thu, Mar 30, 2023 at 11:59 PM Weiwei Li wrote:
The MPP
On 2023/4/7 04:22, Daniel Henrique Barboza wrote:
Hi,
This patch is going to break the sifive_u boot if I rebase
"[PATCH v6 0/9] target/riscv: rework CPU extensions validation"
on top of it, as it is the case today with the current
riscv-to-apply.next.
The reason is that the priv spec ve
On 2023/4/7 03:28, Richard Henderson wrote:
On 4/6/23 00:25, Weiwei Li wrote:
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
{
- if (newpriv > PRV_M) {
+ if (newpriv > PRV_M || newpriv == PRV_H) {
g_assert_not_reached();
}
Nit: if (test) { assert_
On 2023/4/7 03:33, Richard Henderson wrote:
On 4/6/23 00:25, Weiwei Li wrote:
+static target_ulong legalize_mpp(CPURISCVState *env, target_ulong
old_mpp,
+ target_ulong val)
+{
+ target_ulong new_mpp = get_field(val, MSTATUS_MPP);
+ bool mpp_invalid = (ne
On 2023/4/7 09:14, liweiwei wrote:
On 2023/4/7 04:22, Daniel Henrique Barboza wrote:
Hi,
This patch is going to break the sifive_u boot if I rebase
"[PATCH v6 0/9] target/riscv: rework CPU extensions validation"
on top of it, as it is the case today with the current
riscv-to-
On 2023/4/7 18:28, Daniel Henrique Barboza wrote:
On 4/6/23 22:14, liweiwei wrote:
On 2023/4/7 04:22, Daniel Henrique Barboza wrote:
Hi,
This patch is going to break the sifive_u boot if I rebase
"[PATCH v6 0/9] target/riscv: rework CPU extensions validation"
on top of it
On 2023/4/7 18:58, Daniel Henrique Barboza wrote:
On 4/7/23 00:30, Weiwei Li wrote:
Using implicitly enabled extensions such as Zca/Zcf/Zcd instead of their
super extensions can simplify the extension related check. However, they
may have higher priv version than their super extensions. So w
On 2023/4/8 03:25, Daniel Henrique Barboza wrote:
On 4/7/23 00:34, liweiwei wrote:
On 2023/4/7 09:14, liweiwei wrote:
On 2023/4/7 04:22, Daniel Henrique Barboza wrote:
Hi,
This patch is going to break the sifive_u boot if I rebase
"[PATCH v6 0/9] target/riscv: rework CPU exten
On 2023/4/7 23:32, Irina Ryapolova wrote:
Before changing the flow check for sv39/48/57.
According to specification (for Supervisor mode):
Sv39 implementations support a 39-bit virtual address space, divided into 4 KiB
pages.
Instruction fetch addresses and load and store effective addresses,
On 2023/4/10 20:29, Daniel Henrique Barboza wrote:
A CPU is declared static or not by changing the class attribute
'static'. For now the base class is defining every CPU as static via
riscv_cpu_class_init().
To change this setting for generic CPUs we'll need a different class
init for them. Th
On 2023/4/10 21:48, Daniel Henrique Barboza wrote:
Hi,
On 4/10/23 00:35, Weiwei Li wrote:
The patch tries to separate the multi-letter extensions that may
implicitly-enabled by misa.EXT from the explicitly-enabled cases, so
that the misa.EXT can truely disabled by write_misa().
With this sep
On 2023/4/10 22:13, Mayuresh Chitale wrote:
If misa.F and smstateen_fcsr_ok flag are clear then all the floating
point instructions must generate an appropriate exception.
Signed-off-by: Mayuresh Chitale
---
target/riscv/insn_trans/trans_rvf.c.inc | 24 ---
target/ris
On 2023/4/10 22:13, Mayuresh Chitale wrote:
If smstateen is implemented and sstateen0.fcsr is clear then the
floating point operations must return illegal instruction exception
or virtual instruction trap, if relevant.
typo. sstateen0 -> smstateen
And fcsr bit only work when F is not enabled
On 2023/4/10 21:48, Daniel Henrique Barboza wrote:
Hi,
On 4/10/23 00:35, Weiwei Li wrote:
The patch tries to separate the multi-letter extensions that may
implicitly-enabled by misa.EXT from the explicitly-enabled cases, so
that the misa.EXT can truely disabled by write_misa().
With this sep
On 2023/4/11 02:35, Daniel Henrique Barboza wrote:
On 4/10/23 11:20, liweiwei wrote:
On 2023/4/10 21:48, Daniel Henrique Barboza wrote:
Hi,
On 4/10/23 00:35, Weiwei Li wrote:
The patch tries to separate the multi-letter extensions that may
implicitly-enabled by misa.EXT from the
act support for qemu (available at
https://github.com/plctlab/plct-qemu/tree/plct-k-upstream-v2-with-act)
v2:
* optimize implementation for brev8, xperm, zip, unzip
* use aes related sbox array from crypto/aes.h
* move sm4_sbox to crypto/sm4.c, and share it with target/arm
liweiwei (7):
target
- reuse partial instructions of Zbb/Zbc extensions
- add brev8 packh, unzip, zip, etc.
Signed-off-by: liweiwei
Signed-off-by: wangjunqiang
---
target/riscv/bitmanip_helper.c | 74 ++
target/riscv/helper.h | 5 +
target/riscv/insn32.decode
Signed-off-by: liweiwei
Signed-off-by: wangjunqiang
---
disas/riscv.c | 171 +-
1 file changed, 170 insertions(+), 1 deletion(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 793ad14c27..eb1d36d1e5 100644
--- a/disas/riscv.c
+++ b/disas
Signed-off-by: liweiwei
Signed-off-by: wangjunqiang
---
target/riscv/cpu.c | 23 +++
target/riscv/cpu.h | 13 +
2 files changed, 36 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f812998123..a5ec182a86 100644
--- a/target/riscv/cpu.c
- share it between target/arm and target/riscv
Signed-off-by: liweiwei
Signed-off-by: wangjunqiang
---
crypto/meson.build | 1 +
crypto/sm4.c | 37 +
include/crypto/sm4.h | 6 ++
meson | 2 +-
target
Signed-off-by: liweiwei
Signed-off-by: wangjunqiang
---
target/riscv/crypto_helper.c| 446 ++
target/riscv/helper.h | 43 +++
target/riscv/insn32.decode | 42 +++
target/riscv/insn_trans/trans_rvk.c.inc | 467
- add SEED CSR
- add USEED, SSEED fields for MSECCFG CSR
Signed-off-by: liweiwei
Signed-off-by: wangjunqiang
---
target/riscv/cpu_bits.h | 9 ++
target/riscv/csr.c | 70 +
target/riscv/pmp.h | 8 +++--
3 files changed, 84 insertions
Signed-off-by: liweiwei
Signed-off-by: wangjunqiang
---
target/riscv/cpu.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a5ec182a86..fc7ccba672 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -661,7 +661,20 @@ static
test svinval implementation, specify cpu argument with 'x-svinval=true'.
Other two extensions are enabled by default.
This implementation can pass the riscv-tests for rv64ssvnapot.
liweiwei (3):
target/riscv: add support for svnapot extension
target/riscv: add support for svinval
Signed-off-by: liweiwei
Signed-off-by: wangjunqiang
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1 +
target/riscv/insn32.decode | 7 ++
target/riscv/insn_trans/trans_svinval.c.inc | 75 +
target
Signed-off-by: liweiwei
Signed-off-by: wangjunqiang
---
target/riscv/cpu_bits.h | 1 +
target/riscv/cpu_helper.c | 18 --
2 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 9913fa9f77..70391424b0 100644
It uses two PTE bits, but QEMU is sequentially consistent, So it has no effect
on QEMU currently.
Signed-off-by: liweiwei
Signed-off-by: wangjunqiang
---
target/riscv/cpu_bits.h | 4
target/riscv/cpu_helper.c | 9 +++--
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git
On 2023/4/11 17:02, Bin Meng wrote:
When reading a non-existent CSR QEMU should raise illegal instruction
exception, but currently it just exits due to the g_assert() check.
This actually reverts commit 0ee342256af9205e7388efdf193a6d8f1ba1a617,
Some comments are also added to indicate that pre
On 2023/3/8 20:34, chenyi2...@zju.edu.cn wrote:
From: Yi Chen
Trap accesses to hgatp if MSTATUS_TVM is enabled.
Don't trap accesses to vsatp even if MSTATUS_TVM is enabled.
Signed-off-by: Yi Chen
---
target/riscv/csr.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-
On 2023/3/9 23:02, CHEN Yi wrote:
-Original Messages-
*From:*liweiwei
*Sent Time:*2023-03-09 15:48:17 (Thursday)
*To:* chenyi2...@zju.edu.cn, qemu-devel@nongnu.org
*Cc:* "Palmer Dabbelt" , "Alistair Francis"
, "Bin Meng" ,
&q
On 2023/3/10 22:33, chenyi2...@zju.edu.cn wrote:
From: Yi Chen
- Trap satp/hgatp accesses from HS-mode when MSTATUS.TVM is enabled.
- Trap satp accesses from VS-mode when HSTATUS.VTVM is enabled.
- Raise RISCV_EXCP_ILLEGAL_INST when U-mode executes SFENCE.VMA/SINVAL.VMA.
- Raise RISCV_EXCP_VI
On 2023/3/11 00:42, Yi Chen wrote:
- Trap satp/hgatp accesses from HS-mode when MSTATUS.TVM is enabled.
- Trap satp accesses from VS-mode when HSTATUS.VTVM is enabled.
- Raise RISCV_EXCP_ILLEGAL_INST when U-mode executes SFENCE.VMA/SINVAL.VMA.
- Raise RISCV_EXCP_VIRT_INSTRUCTION_FAULT when VU-m
On 2023/3/15 00:49, Daniel Henrique Barboza wrote:
We're getting ready to use riscv_cpu_validate_set_extensions() to unify
the handling of write_misa() with the rest of the code base. But first
we need to deal with RVG.
The 'G' virtual extension enables a set of extensions in the CPU. At
this
On 2023/3/15 00:49, Daniel Henrique Barboza wrote:
We can set all RVG related extensions during realize time, before
validate_set_extensions() itself. It will also avoid re-enabling
RVG via write_misa() when the CSR start to using the same validation
code realize() does.
Note that we're settin
On 2023/3/15 00:49, Daniel Henrique Barboza wrote:
We have a chained dependency in riscv_cpu_validate_set_extensions()
related to RVV. If RVV is set, we enable other extensions such as
Zve64d, Zve64f and Zve32f, and these depends on misa bits RVD and RVF.
Thus, we're making RVV depend on RVD an
On 2023/3/15 00:49, Daniel Henrique Barboza wrote:
We have one last case where we're changing env->misa_ext* during
validation. riscv_cpu_disable_priv_spec_isa_exts(), at the end of
riscv_cpu_validate_set_extensions(), will disable cpu->cfg.ext_h and
cpu->cfg.ext_v if priv_ver check fails.
Thi
On 2023/3/15 00:49, Daniel Henrique Barboza wrote:
write_misa() must use as much common logic as possible. We want to open
code just the bits that are exclusive to the CSR write operation and TCG
internals.
Rewrite write_misa() to work as follows:
- supress RVC right after verifying that we'r
On 2023/3/16 04:37, Daniel Henrique Barboza wrote:
On 3/15/23 02:25, liweiwei wrote:
On 2023/3/15 00:49, Daniel Henrique Barboza wrote:
write_misa() must use as much common logic as possible. We want to open
code just the bits that are exclusive to the CSR write operation and
TCG
On 2023/3/19 04:04, Daniel Henrique Barboza wrote:
We can set all RVG related extensions during realize time, before
validate_set_extensions() itself. Put it in a separated function so the
validate function already uses the updated state.
Note that we're adding an extra constraint: ext_zfinx i
On 2023/3/19 04:04, Daniel Henrique Barboza wrote:
Allow write_misa() to enable RVG by changing riscv_cpu_enable_g()
slighty: instead of returning void, return the current env->misa_ext
value. This is then retrieved by 'val', which will add the RVG flag
itself, and then we'll skip validation an
On 2023/3/19 04:04, Daniel Henrique Barboza wrote:
Allow write_misa() to enable RVV like we did with RVG. We'll need a
riscv_cpu_enable_v() to enable all related misa bits and Z extensions.
This new helper validates the existing 'env' conf by using the existing
riscv_cpu_validate_v(). We'll als
On 2023/3/19 04:04, Daniel Henrique Barboza wrote:
set_misa() is setting all 'misa' related env states and nothing else.
But other functions, namely riscv_cpu_validate_set_extensions(), uses
the config object to do its job.
This creates a need to set the single letter extensions in the cfg
obje
On 2023/3/21 12:34, LIU Zhiwei wrote:
Vector implicitly enables zve64d, zve64f, zve32f sub extensions. As vector
only requires PRIV_1_10_0, these sub extensions should not require priv version
higher than that.
The same for Zfh.
Signed-off-by: LIU Zhiwei
LGTM.
Reviewed-by: Weiwei Li
Wei
On 2023/3/21 14:37, fei2...@intel.com wrote:
From: Fei Wu
Kernel needs to access user mode memory e.g. during syscalls, the window
is usually opened up for a very limited time through MSTATUS.SUM, the
overhead is too much if tlb_flush() gets called for every SUM change.
This patch saves addre
On 2023/3/21 16:40, Wu, Fei wrote:
On 3/21/2023 4:28 PM, liweiwei wrote:
On 2023/3/21 14:37, fei2...@intel.com wrote:
From: Fei Wu
Kernel needs to access user mode memory e.g. during syscalls, the window
is usually opened up for a very limited time through MSTATUS.SUM, the
overhead is too
On 2023/3/21 17:14, Wu, Fei wrote:
On 3/21/2023 4:50 PM, liweiwei wrote:
On 2023/3/21 16:40, Wu, Fei wrote:
On 3/21/2023 4:28 PM, liweiwei wrote:
On 2023/3/21 14:37, fei2...@intel.com wrote:
From: Fei Wu
Kernel needs to access user mode memory e.g. during syscalls, the
window
is usually
On 2023/3/21 20:00, Wu, Fei wrote:
On 3/21/2023 5:47 PM, liweiwei wrote:
On 2023/3/21 17:14, Wu, Fei wrote:
On 3/21/2023 4:50 PM, liweiwei wrote:
On 2023/3/21 16:40, Wu, Fei wrote:
On 3/21/2023 4:28 PM, liweiwei wrote:
On 2023/3/21 14:37,fei2...@intel.com wrote:
From: Fei Wu
Kernel
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