}
}
})
}
Tests not updated given I'm not currently proposing this for upstream.
Signed-off-by: Jonathan Cameron
---
hw/arm/virt-acpi-build.c | 60
hw/i2c/meson.build | 2 +-
2 files changed, 61 insertions(+), 1 deletion(-)
"mctp-i2c-controller"
}
}
})
}
}
To add devices to the bus use something like:
-device i2c_mctp_cxl_switch,bus=aspeed.i2c.bus.0,address=4,target=us0
Signed-off-by: Jonathan Cameron
---
include/hw/i386/pc.h | 1 +
hw/i386/acpi-build
The CCI and Fabric Manager APIs are used to configure CXL switches and
devices. DMTF has defined an MCTP binding specification to carry
these messages. The end goal of this work is to hook this
up to emulated CXL switches and devices to allow control of the
configuration.
Signed-off-by: Jonathan
A lot more needed here on what these are for and what can be done
with them.
Signed-off-by: Jonathan Cameron
---
docs/system/devices/cxl.rst | 27 +++
1 file changed, 27 insertions(+)
diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
index
s
used for the size part of the function name.
Reviewed-by: Fan Ni
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Ira Weiny
Signed-off-by: Jonathan Cameron
---
docs/devel/loads-stores.rst | 2 ++
include/qemu/bswap.h| 25 +
2 files changed, 27 insertion
to an unaligned 24 bit field
Jonathan Cameron (3):
hw/cxl: QMP based poison injection support
hw/cxl: Add poison injection via the mailbox.
hw/cxl: Add clear poison mailbox command support.
docs/devel/loads-stores.rst | 2 +
qapi/cxl.json | 21
include/hw/cxl/
}
}
Adjusted to select a device on your machine.
Note that the poison list supported is kept short enough to avoid the
complexity of state machine that is needed to handle the MORE flag.
Reviewed-by: Fan Ni
Reviewed-by: Ira Weiny
Acked-by: Markus Armbruster
Signed-off-by: Jonathan
Reviewed-by: Fan Ni
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 42 ++
1 file changed, 42 insertions(+)
diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index 1f74b26ea2..6c476ad7f4 100644
--- a/hw/cxl/cxl-mailbox-utils.c
Current implementation is very simple so many of the corner
cases do not exist (e.g. fragmenting larger poison list entries)
Reviewed-by: Fan Ni
Reviewed-by: Ira Weiny
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_device.h | 1 +
hw/cxl/cxl-mailbox-utils.c | 82
> > +# @temperature: Device temperature in degrees Celsius.
> > +#
> > +# @dirty-shutdown-count: Number of time the device has been unable to
>
> Number of times
>
> > +#determine whether data loss may have occurred.
> > +#
> > +# @corrected-volatile-error-count: Total
heral/cxl-mem0",
"log": "informational",
"flags": 1,
"type": 3,
"health-status": 3,
"media-status": 7,
"additional-status": 33,
"life-used": 30,
"temperature": -15,
&quo
.
To support CXL 3.0 the version of the device status register block needs
to be 2. Change the macro to allow for setting the version.
Signed-off-by: Ira Weiny
Reviewed-by: Fan Ni
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_device.h | 23 +---
include/hw/cxl
Following patches will need access to the mailbox return code
type so move it to the header.
Reviewed-by: Ira Weiny
Reviewed-by: Fan Ni
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_device.h | 28
hw/cxl/cxl-mailbox-utils.c | 28
the new infrastructure.
Signed-off-by: Ira Weiny
Reviewed-by: Fan Ni
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_device.h | 25 +
include/hw/cxl/cxl_events.h | 55 +
hw/cxl/cxl-events.c | 217
hw/cxl/cxl-mailbox-utils.c | 40
-off-by: Ira Weiny
Reviewed-by: Fan Ni
Reviewed-by: Davidlohr Bueso
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_device.h | 6 +-
include/hw/cxl/cxl_events.h | 23
hw/cxl/cxl-events.c | 33 ++-
hw/cxl/cxl-mailbox-utils.c | 106
From: Ira Weiny
To facilitate testing provide a QMP command to inject a general media
event. The event can be added to the log specified.
Signed-off-by: Ira Weiny
Reviewed-by: Fan Ni
Acked-by: Markus Armbruster
Signed-off-by: Jonathan Cameron
---
qapi/cxl.json | 74
t;nibble-mask": 37421234,
"bank-group": 7,
"bank": 11,
"row": 2,
"column": 77,
"correction-mask": [33, 44, 55,66]
}}
Acked-by: Markus Armbruster
Reviewed-by: Fan Ni
Reviewed-by: Ira Weiny
Signed-off-by:
: Markus Armbruster
Reviewed-by: Fan Ni
Reviewed-by: Ira Weiny
Signed-off-by: Jonathan Cameron
---
qapi/cxl.json | 53 +++
include/hw/cxl/cxl_events.h | 19
hw/mem/cxl_type3.c | 62 +
hw/mem
rsor patch converting existing
int128_get64(mr->size) users in this file over to that.
Thanks,
Jonathan
On Fri, 3 Mar 2023 15:09:08 +
Jonathan Cameron wrote:
> Current implementation is very simple so many of the corner
> cases do not exist (e.g. fragmenting larger poison list entries)
>
> Signed-off-by: Jonathan Cameron
Another case in here of directly accessing MemoryRegion->
> > diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
> > index 7e5ad65c1d..d589f78202 100644
> > --- a/include/hw/cxl/cxl_device.h
> > +++ b/include/hw/cxl/cxl_device.h
> > @@ -232,6 +232,14 @@ REG64(CXL_MEM_DEV_STS, 0)
> > FIELD(CXL_MEM_DEV_STS, MBOX_READY, 4, 1)
> >
ond
>
> Any clue what's going on?
Hi Raghu,
Yikes. Didn't think anyone would still use that series.
Not even sure I still have a tree with it on.
I'll try and bring up again and get back to you. Might be a little
while though.
Jonathan
>
>
> Regards
> Raghu
ucing chance of a clash with other changes
in flight. Hence this is an RFC to find out if people think this is
a good direction to go in.
Suggested-by: Michael S. Tsirkin
https://lore.kernel.org/qemu-devel/20230302055544-mutt-send-email-...@kernel.org/
Jonathan Cameron (4):
hw/acpi: Make Am
instances present.
Signed-off-by: Jonathan Cameron
---
This could be refactored so that the if (crs) and if (crs_range_set)
checks only occur once, but that then separates the iterating over the
groups and will leave us with two locations to keep up to date for
any future changes. If we did that it
Splitting the PXB parts out of DSDT will change these files.
Signed-off-by: Jonathan Cameron
---
tests/data/acpi/q35/SSDT.cxl| 0
tests/data/acpi/q35/SSDT.viot | 0
tests/qtest/bios-tables-test-allowed-diff.h | 4
3 files changed, 4 insertions(+)
diff --git a
numbers) then to create the DSDT + FACTP as normal.
After that create the SSDT, including rerunning some of the earlier
bus walking code (which will give the same answers).
Signed-off-by: Jonathan Cameron
---
RFC because:
- There are lots of ways this could be done and I'm not sure people
Signed-off-by: Jonathan Cameron
---
tests/data/acpi/q35/DSDT.cxl| Bin 9673 -> 8474 bytes
tests/data/acpi/q35/DSDT.viot | Bin 9470 -> 8429 bytes
tests/data/acpi/q35/SSDT.cxl| Bin 0 -> 1235 bytes
tests/data/acpi/q35/SSDT.viot
On Fri, 17 Mar 2023 16:37:20 +
Jonathan Cameron via wrote:
> On Fri, 17 Mar 2023 00:11:10 +0530
> Maverickk 78 wrote:
>
> > Hi
> >
> > I am trying mctp & mctpd with aspeed +buildroot(master) + linux v6.2
> > with Qemu 7.2.
> >
> >
>
Not a real problem yet as all supported architectures are
little endian, but continue to tidy these up when touching
code for other reasons.
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-component-utils.c | 10 --
hw/mem/cxl_type3.c | 9 ++---
2 files changed, 10
ted attempts to clear
a decoder out of order. That's been reported but not yet fixed.
Jonathan Cameron (2):
hw/cxl: Fix endian handling for decoder commit.
hw/cxl: Fix incorrect reset of commit and associated clearing of
committed.
hw/cxl/cxl-component-utils.c | 14 --
hw/mem/c
Not a real problem yet as all supported architectures are
little endian, but continue to tidy these up when touching
code for other reasons.
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-component-utils.c | 10 --
hw/mem/cxl_type3.c | 9 ++---
2 files changed, 10
On Tue, 21 Mar 2023 19:28:02 +
Fan Ni wrote:
> On Tue, Mar 21, 2023 at 06:00:11PM +0000, Jonathan Cameron wrote:
> > Not a real problem yet as all supported architectures are
> > little endian, but continue to tidy these up when touching
> > code for other reasons.
&
The hardware clearing the commit bit is not spec compliant.
Clearing of committed bit when commit is cleared is not specifically
stated in the CXL spec, but is the expected (and simplest) permitted
behaviour so use that for QEMU emulation.
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl
The hardware clearing the commit bit is not spec compliant.
Clearing of committed bit when commit is cleared is not specifically
stated in the CXL spec, but is the expected (and simplest) permitted
behaviour so use that for QEMU emulation.
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl
ly this is all moot if there is a constraint we can point to
in a specification.
BTW. I'm carrying a patch (it's on the gitlab tree) that I haven't
posted yet that lets you configure this restriction at runtime as
a similar potential host implementation restriction occurs for
PMEM vs
The hardware clearing the commit bit is not spec compliant.
Clearing of committed bit when commit is cleared is not specifically
stated in the CXL spec, but is the expected (and simplest) permitted
behaviour so use that for QEMU emulation.
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl
an option allowed by the CXL spec.
In common with many other areas the code did not take into account
big endian architectures, so fix that whilst we are here.
Note testing this exposed a kernel bug around repeated attempts to clear
a decoder out of order. That's been reported but not yet fixed.
it if anyone could give
> a word about that.
Needs someone to commit to maintaining the code + tests etc.
Whilst I don't mind helping, I don't have the bandwidth to do too much
on this in Qemu, but sounds like you might be the perfect person Marcelo :)
Jonathan
>
>
> Thank
On Tue, 01 Mar 2022 15:32:02 +
Alex Bennée wrote:
> Jonathan Cameron writes:
>
> > From: Ben Widawsky
> >
> > This is the beginning of implementing mailbox support for CXL 2.0
> > devices. The implementation recognizes when the doorbell is rung,
> > han
On Tue, 01 Mar 2022 18:08:31 +
Alex Bennée wrote:
> Jonathan Cameron writes:
>
> > From: Ben Widawsky
> >
> > This adds just enough of a root port implementation to be able to
> > enumerate root ports (creating the required DVSEC entries). What's n
On Tue, 01 Mar 2022 18:11:25 +
Alex Bennée wrote:
> Jonathan Cameron writes:
>
> > At this stage we can boot configurations with host bridges,
> > root ports and type 3 memory devices, so add appropriate
> > tests.
> >
> > Signed-off-by: Jonathan C
On Tue, 01 Mar 2022 18:17:35 +
Alex Bennée wrote:
> Jonathan Cameron writes:
>
> > From: Ben Widawsky
> >
> > A device's volatile and persistent memory are known Host Defined Memory
> > (HDM) regions. The mechanism by which the device is programmed to
On Tue, 01 Mar 2022 18:46:30 +
Alex Bennée wrote:
> Jonathan Cameron writes:
>
> > From: Ben Widawsky
> >
> > GET_FW_INFO and GET_PARTITION_INFO, for this emulation, is equivalent to
> > info already returned in the IDENTIFY command. To have a more robust
On Wed, 02 Mar 2022 10:01:48 +
Alex Bennée wrote:
> Jonathan Cameron writes:
>
> > From: Ben Widawsky
> >
> > This should introduce no change. Subsequent work will make use of this
> > new class member.
> >
> > Signed-off-by: Ben Wid
On Wed, 02 Mar 2022 10:03:34 +
Alex Bennée wrote:
> Jonathan Cameron writes:
>
> > From: Ben Widawsky
> >
> > Implement get and set handlers for the Label Storage Area
> > used to hold data describing persistent memory configuration
> > so that it c
On Wed, 26 Jan 2022 12:32:01 +
Alex Bennée wrote:
> Jonathan Cameron writes:
>
> > From: Ben Widawsky
> >
> > A CXL 2.0 component is any entity in the CXL topology. All components
> > have a analogous function in PCIe. Except for the CXL host bridge, all
>
On Fri, 28 Jan 2022 14:22:51 +
Jonathan Cameron wrote:
> On Wed, 26 Jan 2022 12:32:01 +
> Alex Bennée wrote:
>
> > Jonathan Cameron writes:
> >
> > > From: Ben Widawsky
> > >
> > > A CXL 2.0 component is any entity in the CXL
On Wed, 26 Jan 2022 18:07:40 +
Alex Bennée wrote:
> Jonathan Cameron writes:
>
> > From: Ben Widawsky
> >
> > A CXL device is a type of CXL component. Conceptually, a CXL device
> > would be a leaf node in a CXL topology. From an emulation perspective,
> &
On Wed, 26 Jan 2022 18:17:12 +
Alex Bennée wrote:
> Jonathan Cameron writes:
>
> > From: Ben Widawsky
> >
> > This implements all device MMIO up to the first capability. That
> > includes the CXL Device Capabilities Array Register, as well as all of
> &
On Wed, 26 Jan 2022 18:22:18 +
Alex Bennée wrote:
> Jonathan Cameron writes:
>
> > From: Ben Widawsky
> >
> > This is the beginning of implementing mailbox support for CXL 2.0
> > devices. The implementation recognizes when the doorbell is rung,
> > han
On Mon, 24 Jan 2022 17:16:50 +
Jonathan Cameron wrote:
> From: Ben Widawsky
>
> Implement get and set handlers for the Label Storage Area
> used to hold data describing persistent memory configuration
> so that it can be ensured it is seen in the same configuration
On Thu, 27 Jan 2022 11:55:47 +
Alex Bennée wrote:
> Jonathan Cameron writes:
>
> > From: Ben Widawsky
> >
> > CXL specification provides for the ability to obtain logs from the
> > device. Logs are either spec defined, like the "Command Effects Log&qu
On Thu, 27 Jan 2022 11:50:08 +
Alex Bennée wrote:
> Jonathan Cameron writes:
>
> > From: Ben Widawsky
> >
> > Per spec, timestamp appears to be a free-running counter from a value
> > set by the host via the Set Timestamp command (0301h). There are
> >
On Thu, 27 Jan 2022 13:59:56 +
Alex Bennée wrote:
> Jonathan Cameron writes:
>
> > From: Ben Widawsky
> >
> > This works like adding a typical pxb device, except the name is
> > 'pxb-cxl' instead of 'pxb-pcie'. An example command line wou
On Thu, 27 Jan 2022 14:06:42 +
Alex Bennée wrote:
> Jonathan Cameron writes:
>
> > From: Jonathan Cameron
> >
> > The next patch unifies some of the PCI host bridge DSDT
> > generation code and results in some minor changes to this file.
>
> I'
On Fri, 28 Jan 2022 18:20:01 +
Jonathan Cameron wrote:
> On Thu, 27 Jan 2022 13:59:56 +
> Alex Bennée wrote:
>
> > Jonathan Cameron writes:
> >
> > > From: Ben Widawsky
> > >
> > > This works like adding a typical pxb device, except
here those Intel parts are the type 3 devices.
All comments welcome!
Particular thanks to Alex Bennée for his review of v4.
Thanks,
Jonathan
Ben Widawsky (26):
hw/pci/cxl: Add a CXL component type (interface)
hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5)
hw/cxl/device: Int
components
should implement this interface. Implementing this interface allows the
core PCI code to treat these devices as special where appropriate.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
---
hw/pci/pci.c | 10 ++
include/hw/pci/pci.h
catered towards the eventual
implementation of a Type3 CXL.mem device, 8.2.8.5 in the CXL 2.0
specification.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
---
v5:
Include the impacts of the published CXL 2.0 Errata F4 which clarified
access permissions
From: Jonathan Cameron
The CXL emulation will be jointly maintained by Ben Widawsky
and Jonathan Cameron. Broken out as a separate patch
to improve visibility.
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a
awsky
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
---
v5:
Alex pointed out the odd handling of 8 byte accesses.
That lead to discovering a kernel bug around access to
the Cap Array Header for which a fix is no on the linux-...@vger.kernel.org
list.
We don't currently implement an
From: Ben Widawsky
CXL host bridges themselves may have MMIO. Since host bridges don't have
a BAR they are treated as special for MMIO. This patch includes
i386/pc support.
Signed-off-by: Ben Widawsky
Co-developed-by: Jonathan Cameron
Signed-off-by: Jonathan Cameron
---
hw/i386
alignment are managed by softmmu memory core.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
---
hw/cxl/cxl-device-utils.c | 109
hw/cxl/meson.build | 1 +
include/hw/cxl/cxl_device.h | 31 +-
3 files
From: Ben Widawsky
This opens up the possibility for more types of expanders (other than
PCI and PCIe). We'll need this to create a CXL expander.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
---
hw/pci-bridge/pci_expander_bridge.c | 11 +++--
emulated may want to handle commands
differently, and therefore would need a mechanism to opt in/out of the
specific generic handlers. As such, this is considered sufficient for
now, but may need more depth in the future.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex
S side, for now.
As of CXL 2.0 spec, only 1 sub structure is defined, the CXL Host Bridge
Structure (CHBS) which is primarily useful for telling the OS exactly
where the MMIO for the host bridge is.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
---
v5: Part of this patch moved ea
communication
between the host OS and the firmware running on the device. For our
purposes, we emulate both the firmware, implemented primarily in
cxl-mailbox-utils.c, and the hardware.
No commands are implemented yet.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
---
v5: Responses to
bus to the
correct type. This is less code and useful for debugging via simply
looking at the flags.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
---
hw/pci-bridge/pci_expander_bridge.c | 9 -
include/hw/pci/pci_bus.h| 7 +++
2
From: Ben Widawsky
This should introduce no change. Subsequent work will make use of this
new class member.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 3 +++
hw/mem/cxl_type3.c | 24 +---
include/hw/cxl
From: Jonathan Cameron
The next patch unifies some of the PCI host bridge DSDT
generation code and results in some minor changes to this file.
Signed-off-by: Jonathan Cameron
---
v5: No change, but Alex suggested we combine this and next
two patches. I'd like feedback from the bios t
From: Ben Widawsky
This works like adding a typical pxb device, except the name is
'pxb-cxl' instead of 'pxb-pcie'. An example command line would be as
follows:
-device pxb-cxl,id=cxl.0,bus="pcie.0",bus_nr=1
A CXL PXB is backward compatible with PCIe. What this means in practice
is that an ope
From: Ben Widawsky
Using the previously implemented stubbed helpers, it is now possible to
easily add the missing, required commands to the implementation.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
---
v5: Follow through on upper casing defines in
From: Ben Widawsky
This cleanup will make it easier to add support for CXL to the mix.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
---
v5: Make the PCI bus type a typed enum.
hw/i386/acpi-build.c | 39 ++-
1 file
From: Ben Widawsky
GET_FW_INFO and GET_PARTITION_INFO, for this emulation, is equivalent to
info already returned in the IDENTIFY command. To have a more robust
implementation, add those.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
---
v5: Follow through on rework of how
From: Ben Widawsky
Errata F4 to CXL 2.0 clarified the meaning of the timer as the
sum of the value set with the timestamp set command and the number
of nano seconds since it was last set.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
---
v5: Reponses to Alex's review.
- C
From: Jonathan Cameron
The consolidation of DSDT AML generation for PCI host bridges
lead to some minor ordering changes and the addition of _ADR
with a default of 0 for those case that didn't already have it.
Only DSDT.viot test is affected.
Changes all similar to:
Scope
se log commands.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
---
v5: Results of Alex's review.
- Follow through on v5 removal of mailbox handler related macros.
It was this patch where Alex highlighted the need to make that
change.
hw/cxl/cxl-
From: Jonathan Cameron
Both registers and the CFMWS entries in CDAT use simple encodings
for the number of interleave ways and the interleave granularity.
Introduce simple conversion functions to/from the unencoded
number / size. So far the iw decode has not been needed so is
it not implemented
Code based on i386/pc enablement.
The memory layout places space for 16 host bridge register regions after
the GIC_REDIST2 in the extended memmap.
The CFMWs are placed above the extended memmap.
Signed-off-by: Jonathan Cameron
Signed-off-by: Ben Widawsky
---
hw/arm/virt-acpi-build.c | 30
From: Jonathan Cameron
The concept of these is introduced in [1] in terms of the
description the CEDT ACPI table. The principal is more general.
Unlike once traffic hits the CXL root bridges, the host system
memory address routing is implementation defined and effectively
static once observable
From: Jonathan Cameron
Inorder to implement memory interleaving we need a means to proxy
the calls. Adding mem_ops allows such proxying.
Note should have no impact on use cases not using _dispatch_read/write.
For now, only file backed hostmem is considered to seek feedback on
the approach
y
Co-developed-by: Jonathan Cameron
Signed-off-by: Jonathan Cameron
---
hw/mem/cxl_type3.c | 54 ++
1 file changed, 54 insertions(+)
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index c4021d2434..da091157f2 100644
--- a/hw/mem/cxl_type3.c
+++ b/h
From: Jonathan Cameron
There are going to be some potential overheads to CXL enablement,
for example the host bridge region reserved in memory maps.
Add a machine level control so that CXL is disabled by default.
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
---
v5: From Alex
-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
---
hw/acpi/cxl.c | 59 +++
1 file changed, 59 insertions(+)
diff --git a/hw/acpi/cxl.c b/hw/acpi/cxl.c
index 442f836a3e..50efc7f690 100644
--- a/hw/acpi/cxl.c
+++ b/hw/acpi/cxl.c
@@ -60,6 +60,64
From: Ben Widawsky
CXL 2.0 specification adds 2 new dwords to the existing _OSC definition
from PCIe. The new dwords are accessed with a new uuid. This
implementation supports what is in the specification.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
---
v5: Fix for issue seen
The CXL expander bridge has several requirements but the one that
is checked first is that it is attached to a PCI Express bus,
not a PCI one so document that.
Signed-off-by: Jonathan Cameron
---
v5:
New patch - should probably be pushed down to introduction of pxb-cxl.
Will do that in v6
tport to a
specific CXL host bridge. For example:
-device cxl-rp,id=rp0,bus="cxl.0",addr=0.0,chassis=4
Like the host bridge patch, the ACPI tables aren't generated at this
point and so system software cannot use it.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
From: Jonathan Cameron
Accessor to get hold of the cxl state for a CXL host bridge
without exposing the internals of the implementation.
Signed-off-by: Jonathan Cameron
---
hw/pci-bridge/pci_expander_bridge.c | 7 +++
include/hw/cxl/cxl_component.h | 2 ++
2 files changed, 9
quot;
Note: Dropped PCDIMM info interfaces for now. They can be added if
appropriate at a later date.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 47 ++
hw/mem/Kconfig | 5 ++
hw/mem/cxl_t
From: Ben Widawsky
Following patches will add a new ACPI table, the
CXL Early Discovery Table (CEDT).
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
---
tests/data/acpi/pc/CEDT | 0
tests/data/acpi/q35/CEDT| 0
tests/qtest/bios-tables-test
From: Jonathan Cameron
These memops perform interleave decoding, walking down the
CXL topology from CFMWS described host interleave
decoder via CXL host bridge HDM decoders, through the CXL
root ports and finally call CXL type 3 specific read and write
functions.
Note that, whilst functional
From: Ben Widawsky
Implement get and set handlers for the Label Storage Area
used to hold data describing persistent memory configuration
so that it can be ensured it is seen in the same configuration
after reboot.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
---
v5:
Fix wrong
From: Jonathan Cameron
Once a read or write reaches a CXL type 3 device, the HDM decoders
on the device are used to establish the Device Physical Address
which should be accessed. These functions peform the required maths
and then directly access the hostmem->mr to fullfil the actual
operat
From: Ben Widawsky
Add a trivial handler for now to cover the root bridge
where we could do some error checking in future.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-component-utils.c | 31 +++
1 file changed, 31 insertions
This adds code to instantiate the slightly extended ACPI root port
description in DSDT as per the CXL 2.0 specification.
Basically a cut and paste job from the i386/pc code.
Signed-off-by: Jonathan Cameron
Signed-off-by: Ben Widawsky
---
v5:
No change to this patch, but build issue seen here
From: Jonathan Cameron
More sophisticated tests will come later, but for now deal
with the NULL case.
Signed-off-by: Jonathan Cameron
---
tests/data/acpi/pc/CEDT | Bin 0 -> 36 bytes
tests/data/acpi/q35/CEDT| Bin 0 -> 36 bytes
tests/data/acpi/vir
complex so a lot of steps will be needed.
Signed-off-by: Ben Widawsky
Co-developed-by: Jonathan Cameron
Signed-off-by: Jonathan Cameron
---
tests/qtest/cxl-test.c | 151
tests/qtest/meson.build | 4 ++
2 files changed, 155 insertions(+)
create mode 10
From: Jonathan Cameron
Simple function to search a PCIBus to find a port by
it's port number.
CXL interleave decoding uses the port number as a target
so it is necessary to locate the port when doing interleave
decoding.
Signed-off-by: Jonathan Cameron
---
hw/pci/pcie_port.c
From: Jonathan Cameron
Allow for the creation of the CEDT ACPI table without
qtest fails due to the unknown ACPI tables.
Signed-off-by: Jonathan Cameron
---
tests/data/acpi/virt/CEDT | 0
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
2 files changed, 1 insertion
From: Jonathan Cameron
Add the CFMWs memory regions to the memorymap and adjust the
PCI window to avoid hitting the same memory.
Signed-off-by: Jonathan Cameron
---
hw/i386/pc.c | 31 ++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/hw/i386/pc.c b
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