t cherry
picked
from a series that included ARM support but arm support hasn't landed yet
(and will be a while due to need for DT support).
I'll look at fixing both issues up. Or if you want to send a patch Raghu that
would
be even better!
Jonathan
>
>
> Regards
>
On Mon, 3 Apr 2023 16:03:20 +0530
Maverickk 78 wrote:
> Hi Jonathan
>
> Do you want me to modify the doc(remove size)? I can do that.
That would be great. Also whilst there, a second patch to modify
the architecture to be x86_64 would be good.
Thanks,
Jonathan
>
> Regards
On Fri, 24 Mar 2023 11:17:50 +0100
Thomas Huth wrote:
> On 07/12/2022 14.26, Thomas Huth wrote:
> > On 07/12/2022 14.21, Jonathan Cameron wrote:
> >> On Mon, 05 Dec 2022 14:59:39 +
> >> Alex Bennée wrote:
> >>
> >>> Jonathan Cameron via
On Fri, 17 Mar 2023 16:54:36 +
Jonathan Cameron via wrote:
> Michael Tsirkin raised that we have recently had churn in the bios-tables-test
> and perhaps it was worth factoring some parts of DSDT out as SSDT files.
> This is an attempt to do that for the entries from pxb-pcie an
On Wed, 5 Apr 2023 15:57:38 +0530
Raghu H wrote:
Hi Raghu,
Thanks for tidying this up! (and reporting it in the first place)
A few minor comments for v2.
A better title might be
docs/cxl: Remove incorrect CXL type 3 size parameter.
> cxl device typ3 size is read from the memory backend device
On Sun, 9 Apr 2023 22:18:28 +0200
Stefan Weil wrote:
> Signed-off-by: Stefan Weil
Acked-by: Jonathan Cameron
> ---
>
> If my change is okay I suggest to apply the patch for 8.0
> because it fixes documentation.
>
> Regards,
> Stefan W.
>
> docs/system/de
On Mon, 16 Jan 2023 14:37:23 +
Jonathan Cameron via wrote:
> On Fri, 13 Jan 2023 17:10:51 +
> Fan Ni wrote:
>
> > On Fri, Jan 13, 2023 at 09:47:25AM +, Jonathan Cameron wrote:
> >
> > > On Fri, 13 Jan 2023 00:27:55 +
> > > Fan Ni wr
meron. I'm fairly sure I grok it now.
> >
> > Summarizing to make sure: the cxl driver is providing what would be the
> > CXL.io (control) path, and the CXL.mem path is basically being simulated
> > by what otherwise would be a traditional PCI memory region. This explai
ing region / namespace in a
1HB 2RP 2EP test case. That is proving hard to replicate consistently
but doesn't seem to have anything to do with the emulation other than
perhaps we are opening up a race by responding slowly to something.
Jonathan Cameron (2):
hw/pci: Add pcie_coun
it.
Reported-by: Fan Ni
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-host.c | 31 +
hw/pci-bridge/pci_expander_bridge.c | 43 +
include/hw/cxl/cxl.h| 1 +
include/hw/cxl/cxl_component.h | 1 +
include/hw
: Jonathan Cameron
---
hw/pci/pcie_port.c | 38 ++
include/hw/pci/pcie_port.h | 2 ++
2 files changed, 40 insertions(+)
diff --git a/hw/pci/pcie_port.c b/hw/pci/pcie_port.c
index 687e4e763a..b709777e0c 100644
--- a/hw/pci/pcie_port.c
+++ b/hw/pci/pcie_port.c
On Mon, 23 Jan 2023 17:53:24 +
Fan Ni wrote:
> On Mon, Jan 23, 2023 at 12:17:10PM +0000, Jonathan Cameron wrote:
>
>
>
> > Until now, testing using CXL has relied up always using two root ports
> > below a host bridge, to work around a current assumption in the
nd results so should look like the code
in cmd_timestamp_get()
https://elixir.bootlin.com/qemu/latest/source/hw/cxl/cxl-mailbox-utils.c#L165
One other trivial comment inline.
Not sure if you are going to get back to these. I'm happy to just hack these
changes in if that is easier for you.
T
l.org/all/20230112102644.27830-1-jonathan.came...@huawei.com/
[PATCH v2 0/8] hw/cxl: CXL emulation cleanups and minor fixes for upstream
Jonathan Cameron (2):
hw/pci: Add pcie_count_ds_port() and pcie_find_port_first() helpers
hw/pxb-cxl: Support passthrough HDM Decoders unless overridden
hw/cx
: Jonathan Cameron
---
hw/pci/pcie_port.c | 38 ++
include/hw/pci/pcie_port.h | 2 ++
2 files changed, 40 insertions(+)
diff --git a/hw/pci/pcie_port.c b/hw/pci/pcie_port.c
index 687e4e763a..cae22e8b28 100644
--- a/hw/pci/pcie_port.c
+++ b/hw/pci/pcie_port.c
it.
Reported-by: Fan Ni
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-host.c | 31
hw/pci-bridge/pci_expander_bridge.c | 44 +
include/hw/cxl/cxl.h| 1 +
include/hw/cxl/cxl_component.h | 1 +
include/hw
On Wed, 25 Jan 2023 21:42:04 -0800
Ira Weiny wrote:
> Jonathan Cameron wrote:
> > v2: Thanks to Mike Maslenkin for review.
> > - Fix wrong parameter type to ct3d_qmp_cor_err_to_cxl()
> > - Rework use of CXLError local variable in ct3d_reg_write() to improve
> > cod
In addition avoid setting the time stamp twice.
>
> Fixes: fb64c5661d5f ("hw/cxl/events: Wire up get/clear event mailbox
> commands")
> Reported-by: Jonathan Cameron
> Signed-off-by: Ira Weiny
Hi Ira,
I'm going to split this patch as I am carrying a very simila
On Wed, 25 Jan 2023 21:37:28 -0800
Ira Weiny wrote:
> g_new0() will terminate the application if it fails. Remove the check.
>
> Fixes: fb64c5661d5f ("hw/cxl/events: Wire up get/clear event mailbox
> commands")
> Reported-by: Jonathan Cameron
> Signed-off-b
On Fri, 20 Jan 2023 14:24:50 +
Jonathan Cameron via wrote:
> CXL uses PCI AER Internal errors to signal to the host that an error has
> occurred. The host can then read more detailed status from the CXL RAS
> capability.
>
> For uncorrectable errors: support multiple i
bles-test.c data which is in
tests/data/acpi/q35/DSDT.cxl
We should update that test code as part of the volatile series as well
as it's using the deprecated memdev parameter - not critical
but never a good thing to leave old examples of what not to use in
the tests.
Thanks,
Jonathan
p.s.
On Thu, 26 Jan 2023 11:41:47 -0700
Dave Jiang wrote:
> On 1/26/23 11:24 AM, Jonathan Cameron wrote:
> > On Thu, 26 Jan 2023 11:07:37 -0700
> > Dave Jiang wrote:
> >
> > Hi Dave,
> >
> > That was quick!
> >
> >> Add a simple _DSM cal
On Thu, 26 Jan 2023 21:57:35 +
Fan Ni wrote:
> On Wed, Jan 25, 2023 at 03:27:03PM +0000, Jonathan Cameron wrote:
>
> > The CXL r3.0 specification allows for there to be no HDM decoders on CXL
> > Host Bridges if they have only a single root port. Instead, all accesses
&
On Fri, 27 Jan 2023 17:02:36 +
Fan Ni wrote:
> On Fri, Jan 27, 2023 at 10:01:49AM +0000, Jonathan Cameron wrote:
>
> > On Thu, 26 Jan 2023 21:57:35 +
> > Fan Ni wrote:
> >
> > > On Wed, Jan 25, 2023 at 03:27:03PM +, Jonathan Cameron wro
On Thu, 5 Jan 2023 14:38:07 +
Jonathan Cameron wrote:
> On Mon, 28 Nov 2022 10:01:56 -0500
> Gregory Price wrote:
>
> > Defines are starting to exceed line length limits, align them for
> > cleanliness before making modifications.
> >
> > Signed-off-by:
> diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c
> index e59ba22387..6893f54e28 100644
> --- a/tests/qtest/cxl-test.c
> +++ b/tests/qtest/cxl-test.c
> @@ -40,32 +40,46 @@
>"-device cxl-rp,id=rp2,bus=cxl.1,chassis=0,slot=2 " \
>"-device cxl-rp,id=rp3,bus=cxl.1,chassis=0,slot=
/jic23/qemu/-/commits/cxl-2023-01-11
Gregory Price (2):
hw/cxl: set cxl-type3 device type to PCI_CLASS_MEMORY_CXL
hw/cxl: Add CXL_CAPACITY_MULTIPLIER definition
Ira Weiny (3):
qemu/bswap: Add const_le64()
qemu/uuid: Add UUID static initializer
hw/cxl/mailbox: Use new UUID network order
msix_init_exclusive_bar() can fail, so if it does cleanup the address space.
Reviewed-by: Ira Weiny
Signed-off-by: Jonathan Cameron
---
hw/mem/cxl_type3.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index dae4fd89ca
Fix capitalization difference between struct name and typedef.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Ira Weiny
Signed-off-by: Jonathan Cameron
---
hw/pci-bridge/cxl_downstream.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
From: Gregory Price
Current code sets to STORAGE_EXPRESS and then overrides it.
Reviewed-by: Davidlohr Bueso
Reviewed-by: Ira Weiny
Signed-off-by: Gregory Price
Signed-off-by: Jonathan Cameron
---
hw/mem/cxl_type3.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw
From: Gregory Price
Remove usage of magic numbers when accessing capacity fields and replace
with CXL_CAPACITY_MULTIPLIER, matching the kernel definition.
Signed-off-by: Gregory Price
Reviewed-by: Davidlohr Bueso
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Jonathan Cameron
---
v2
Next patch will drop duplicate _UID entry so allow update.
Signed-off-by: Jonathan Cameron
---
v3: New patch
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
Noticed as this prevents iASL disasembling the DSDT table.
Reviewed-by: Ira Weiny
Signed-off-by: Jonathan Cameron
---
hw/i386/acpi-build.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 127c4e2d50..a584b62ae2 100644
--- a/hw/i386/acpi
Dropping the ID effects this table in trivial fashion.
Signed-off-by: Jonathan Cameron
---
v3: New patch to update the table.
tests/data/acpi/q35/DSDT.cxl| Bin 9636 -> 9622 bytes
tests/qtest/bios-tables-test-allowed-diff.h | 1 -
2 files changed, 1 deletion(-)
diff --gi
From: Ira Weiny
Gcc requires constant versions of cpu_to_le* calls.
Add a 64 bit version.
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Ira Weiny
Signed-off-by: Jonathan Cameron
---
v2: Update comment (Philippe)
---
include/qemu/bswap.h | 12
From: Ira Weiny
UUID's are defined as network byte order fields. No static initializer
was available for UUID's in their standard big endian format.
Define a big endian initializer for UUIDs.
Signed-off-by: Ira Weiny
Signed-off-by: Jonathan Cameron
---
include/qemu/u
ed-by: Philippe Mathieu-Daudé
Signed-off-by: Ira Weiny
Signed-off-by: Jonathan Cameron
---
v2:
Make it const (Philippe)
---
hw/cxl/cxl-device-utils.c | 2 +-
hw/cxl/cxl-mailbox-utils.c | 13 ++---
include/hw/cxl/cxl_device.h | 2 +-
3 files changed, 8 insertions(+), 9 deletions(-)
: {
"path": "/machine/peripheral/cxl-pmem0",
"type": "physical"
} }
Based on top of:
https://lore.kernel.org/qemu-devel/20230130143705.11758-1-jonathan.came...@huawei.com/T/#t
[PATCH v3 00/10] hw/cxl: CXL emulation cleanups and minor fixes
This register in AER should be both writeable and should
have a default value with a couple of the errors masked
including the Uncorrectable Internal Error used by CXL for
it's error reporting.
Signed-off-by: Jonathan Cameron
---
hw/pci/pcie_aer.c | 4
include/hw/pci/pcie_r
lass bit in the PCIe
Device Control Register is set.
Implement that branch thus enabling routing of ERR_COR, ERR_NONFATAL
and ERR_FATAL under OSes that set these bits appropriately (e.g. Linux)
Signed-off-by: Jonathan Cameron
---
hw/pci/pcie_aer.c | 10 +-
1 file changed, 9 insertions(+),
We are missing necessary config write handling for AER emulation in
the CXL root port. Add it based on pcie_root_port.c
Signed-off-by: Jonathan Cameron
---
hw/pci-bridge/cxl_root_port.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge
Done to avoid fixing ACPI route description of traditional PCI interrupts on q35
and because we should probably move with the times anyway.
Signed-off-by: Jonathan Cameron
---
hw/pci-bridge/cxl_root_port.c | 61 +++
1 file changed, 61 insertions(+)
diff --git a
This enables AER error injection to function as expected.
It is intended as a building block in enabling CXL RAS error injection
in the following patches.
Signed-off-by: Jonathan Cameron
---
hw/mem/cxl_type3.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/hw/mem/cxl_type3.c
hings worse for that support in the future.
Signed-off-by: Jonathan Cameron
---
v3: New patch.
hw/cxl/cxl-component-utils.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c
index 3edd303a33..737b4
This infrastructure will be reused for CXL RAS error injection
in patches that follow.
Signed-off-by: Jonathan Cameron
---
hw/pci/pci-internal.h | 1 -
include/hw/pci/pcie_aer.h | 1 +
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/pci/pci-internal.h b/hw/pci/pci-internal.h
"type": "internal",
"header": [ 1, 2, 4]
}
]
}}
...
{ "execute": "cxl-inject-correctable-error",
"arguments": {
"path": "/machine/peripheral/cxl-pmem0",
"type": "phy
On Fri, 27 Jan 2023 21:38:20 -0500
"Michael S. Tsirkin" wrote:
> On Thu, Jan 12, 2023 at 10:26:41AM +0000, Jonathan Cameron wrote:
> > Noticed as this prevents iASL disasembling the DSDT table.
> >
> > Reviewed-by: Ira Weiny
> > Signed-off-by: Jonathan Cam
the new [persistent-memdev] property.
>
> Partitioning volatile memory from persistent memory is not yet supported.
>
> Volatile memory is mapped at DPA(0x0), while Persistent memory is mapped
> at DPA(vmem->size), per CXL Spec 8.2.9.8.2.0 - Get Partition Info.
>
> Signed-of
From: Gregory Price
Defines are starting to exceed line length limits, align them for
cleanliness before making modifications.
Signed-off-by: Gregory Price
Signed-off-by: Jonathan Cameron
---
Changes since RFC v4:
Naming consistency improvements.
tests/qtest/cxl-test.c | 84
Now we have some kernel code to test this against (and it looks good)
I'd like to propose this series for upstream following 3 other series
already proposed for inclusion:
a)
https://lore.kernel.org/linux-cxl/20230130143705.11758-1-jonathan.came...@huawei.com/
[PATCH v3 00/10] hw/cxl: CXL emul
memory is mapped at DPA(0x0), while Persistent memory is mapped
at DPA(vmem->size), per CXL Spec 8.2.9.8.2.0 - Get Partition Info.
Signed-off-by: Gregory Price
Signed-off-by: Jonathan Cameron
---
Chances since RFC V4:
- Fixed up issue reported by Gregory of volatile regions being reported
lore.kernel.org/linux-cxl/20230130151327.32415-1-jonathan.came...@huawei.com/
[1]
https://lore.kernel.org/linux-cxl/20220620162056.16790-1-jonathan.came...@huawei.com/
Jonathan Cameron (3):
hw/cxl: QMP based poison injection support
hw/cxl: Add poison injection via the mailbox.
hw/cxl: Add clear poiso
Current implementation is very simple so many of the corner
cases do not exist (e.g. fragmenting larger poison list entries)
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 77 +
hw/mem/cxl_type3.c | 36 +
include/hw
Very simple implementation to allow testing of corresponding
kernel code. Note that for now we track each 64 byte section
independently. Whilst a valid implementation choice, it may
make sense to fuse entries so as to prove out more complex
corners of the kernel code.
Signed-off-by: Jonathan
ot;: "/machine/peripheral/cxl-pmem0",
"start": 2048,
"length": 256
}
}
Adjusted to select a device on your machine.
Note that the poison list supported is kept short enough to avoid the
complexity of state machine that is needed to handle the MORE
On Wed, 01 Feb 2023 13:14:06 +0100
Markus Armbruster wrote:
> Jonathan Cameron via writes:
>
> > Inject poison using qmp command cxl-inject-poison to add an entry to the
> > poison list.
> >
> > For now, the poison is not returned CXL.mem reads, but only via the
On Fri, 19 Nov 2021 18:53:43 +
Jonathan Cameron wrote:
> On Thu, 18 Nov 2021 17:52:07 -0800
> Ben Widawsky wrote:
>
> > On 21-11-18 15:20:34, Saransh Gupta1 wrote:
> > > Hi Ben and Jonathan,
> > >
> > > Thanks for your replies. I'm lookin
On Fri, 12 May 2023 17:08:03 +0800
Hao Zeng wrote:
> Qemu does not support qxl graphics cards in arm, it is recommended to enable
>
> Signed-off-by: Hao Zeng
Drive by comment.
> ---
> hw/arm/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/arm/Kconfig b/hw
On Thu, 11 May 2023 17:56:40 +
Fan Ni wrote:
> Since the early draft of DCD support in kernel is out
> (https://lore.kernel.org/linux-cxl/20230417164126.GA1904906@bgt-140510-bm03/T/#t),
> this patch series provide dcd emulation in qemu so people who are interested
> can have an early try. It
or the host to get the info.
>
> Signed-off-by: Fan Ni
Trivial formatting aside, looks good to me.
Jonathan
> ---
> hw/cxl/cxl-mailbox-utils.c | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox
On Thu, 11 May 2023 17:56:40 +
Fan Ni wrote:
> From: Fan Ni
>
> Per cxl spec 3.0, add dynamic capacity region representative based on
> Table 8-126 and extend the cxl type3 device definition to include dc region
> information. Also, based on info in 8.2.9.8.9.1, add 'Get Dynamic Capacity
>
uint8_t flags;
> > + uint8_t rsvd2[3];
> > + } QEMU_PACKED records[];
>
> Could you declare CXLDCD_Region as QEMU_PACKED and use it here instead of
> re-defining the region structure?
Could be done, but care needed on the endian conversions. I
to
do there before that matters and we can still have default config for any
regions we define now.
Jonathan
> ---
> hw/mem/cxl_type3.c | 32
> 1 file changed, 32 insertions(+)
>
> diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
> index 2b4
vices/$region/commit
> echo $region > /sys/bus/cxl/drivers/cxl_region/bind
>
> Signed-off-by: Fan Ni
Hi Fan,
A few comments inline,
Thanks,
Jonathan
> ---
> hw/cxl/cxl-mailbox-utils.c | 73 -
> hw/mem/cxl_type3.c | 1 +
>
On Thu, 11 May 2023 17:56:40 +
Fan Ni wrote:
> From: Fan Ni
>
> Per CXL spec 3.0, we implemented the two mailbox commands:
> Add Dynamic Capacity Response (Opcode 4802h) 8.2.9.8.9.3, and
> Release Dynamic Capacity Response (Opcode 4803h) 8.2.9.8.9.4.
>
> Signed-off-by: Fan Ni
> ---
> hw/
On Thu, 11 May 2023 17:56:40 +
Fan Ni wrote:
> From: Fan Ni
>
> Since fabric manager emulation is not supported yet, the change implements
> the functions to add/release dynamic capacity extents as QMP interfaces.
This makes sense at least as a stop gap.
>
> 1. Add dynamic capacity exten
On Thu, 11 May 2023 17:56:40 +
Fan Ni wrote:
> From: Fan Ni
>
> Before the change, read from or write to dynamic capacity of the memory
> device is not support as 1) no host backed file/memory is provided for
> it; 2) no address space is created for the dynamic capacity.
Ah nice. I should
ke this multi-headed, some amount of this state would need
> to be encapsulated in a shared memory region (or would it? I don't know, i
> haven't finished this thought experiment yet).
Someone (wherever the LD pool CCI is) needs to hold shared state.
Lots of options for that.
>
>
> =
> FIN
> =
>
> I realize this was a long. If you made it to the end of this email,
> thank you reading my TED talk. I greatly appreciate any comments,
> even if it's just "You've gone too deep, Gregory." ;]
:) You've only just got started. This goes much deeper!
>
> Regards,
> ~Gregory
To my mind there are a series of steps and questions here.
Which 'hotplug model'.
1) LD model for moving capacity
- If doing LD model, do MLDs and configurable switches first. Needed as a
step along the
path anyway. Deal with all the mess that brings and come back to MHD - as
you note it
only makes sense with a switch in the path, so MLDs are a subset of the
functionality anyway.
2) DCD model for moving cacapcity
- MH-SLD with a pool CCI used to do DCD operations on the LDs. Extension of
what Fan Ni is looking at. He's making an SLD pretend to be a device
where DCD makes sense - whilst still using the CXL type 3 device. We
probably shouldn't
do that without figuring out how to do an MHD-SLD - or at least a head that
we intend
to hang this new stuff off - potentially just using the existing type 3
device with
more parameters as one of the MH-SLD heads that doesn't have the control
interface and
different parameters if it does have the tunnel to the Pool CCI.
Implementing MCTP CCI. Probably a later step, but need to think what that
looks like.
I'm thinking we proxy it through to wherever the pool CCI ends up. Should be
easy enough
if a little ugly.
So question is whether it's worth a highly modular design, or we just keep
tacking
flexibility onto existing Type 3 device emulation. These are all type 3 devices
after all ;)
Lots of fun details to hammer out.
Jonathan
On Sun, 23 Apr 2023 17:51:33 +0100
Jonathan Cameron wrote:
> v5: Rebase including version number updates to 8.1
Hi Michael,
I asked a few people to look at the remaining couple of patches where
there were only my tags so now I think all the following have
had some review and I'm not
On Tue, 16 May 2023 02:20:07 -0400
Gregory Price wrote:
> On Mon, May 15, 2023 at 05:18:07PM +0100, Jonathan Cameron wrote:
> > On Tue, 21 Mar 2023 21:50:33 -0400
> > Gregory Price wrote:
> >
> > >
> > > Ambiguity #1:
> > >
> > &
.0 soon
given it's horrible having a mixture of spec versions for the references.
For future specs, we should only do this when sufficient X.Y references
have started to appear - I think that's true for r3.0 now.
Jonathan
> ---
> include/hw/cxl/cxl_component.h | 6 --
>
> > +/*
> > + * This is very inefficient, but good enough for now!
> > + * Also thed payload will always fit, so no need to handle the MORE flag
> > and
> > + * make this stateful.
> > + */
> > +static ret_code cmd_media_get_poison_list(struct cxl_cmd *cmd,
> > +
am not sure I understood what I am supposed to put in commit messages.
> Can you check the 4 patches on top of
> https://github.com/bgoglin/qemu/commits/hmat-noinitiator before I resend
> them to the list?
>
> Brice
>
I left a couple of trivial comments on github, but basically looks good
to me.
Jonathan
On Thu, 16 Jun 2022 15:19:48 +0100
Jonathan Cameron via wrote:
> Previously patches 40 and 41 of
> [PATCH v10 00/45] CXl 2.0 emulation Support
> https://lore.kernel.org/qemu-devel/20220429144110.25167-45-jonathan.came...@huawei.com/#r
>
> Now the base CXL support includin
On Fri, 24 Jun 2022 11:48:47 +0100
Peter Maydell wrote:
> On Thu, 16 Jun 2022 at 15:20, Jonathan Cameron
> wrote:
> >
> > Code based on i386/pc enablement.
> > The memory layout places space for 16 host bridge register regions after
> > the GIC_REDIST2 in the exte
On Fri, 24 Jun 2022 13:56:32 +0100
Peter Maydell wrote:
> On Fri, 24 Jun 2022 at 13:39, Jonathan Cameron
> wrote:
> >
> > On Fri, 24 Jun 2022 11:48:47 +0100
> > Peter Maydell wrote:
> > >
> > > This seems to be missing code to advertis
On Fri, 24 Jun 2022 15:08:44 +0100
Jonathan Cameron wrote:
> On Fri, 24 Jun 2022 13:56:32 +0100
> Peter Maydell wrote:
>
> > On Fri, 24 Jun 2022 at 13:39, Jonathan Cameron
> > wrote:
> > >
> > > On Fri, 24 Jun 2022 11:48:47 +0100
> > > Peter M
s: acpi: q35: update expected blobs *.hmat-noinitiators]
Hi Brice,
Given I reviewed on your github prior to you sending this and you've addressed
the few minor things I raised.
Reviewed-by: Jonathan Cameron
Nice to tidy this up.
Jonathan
>
> hw/core/machine.c
On Fri, 24 Jun 2022 16:01:42 +0100
Peter Maydell wrote:
> On Fri, 24 Jun 2022 at 15:54, Jonathan Cameron
> wrote:
> > Just occurred to me there is another barrier to an approach that adds
> > DT bindings.
> > I fairly sure hw/pci-bridge/pci_expander_bridge.c (PXB
On Fri, 24 Jun 2022 17:12:25 +0100
Peter Maydell wrote:
> On Thu, 16 Jun 2022 at 15:20, Jonathan Cameron
> wrote:
> >
> > Add a single complex case for aarch64 virt machine.
> >
> > Signed-off-by: Jonathan Cameron
> > -
On Mon, 27 Jun 2022 14:29:19 +0100
Peter Maydell wrote:
> On Mon, 16 May 2022 at 21:51, Michael S. Tsirkin wrote:
> >
> > From: Jonathan Cameron
> >
> > Both registers and the CFMWS entries in CDAT use simple encodings
> > for the number of interleave wa
Three more or less less unrelated fixes for recently added CXL code.
Jonathan Cameron (3):
hw/machine: Clear out left over CXL related pointer from move of state
handling to machines.
hw/i386/pc: Always place CXL Memory Regions after device_memory
hw/cxl: Fix size of constant in
broken_reserved_end flag was set.
Fixes: 6e4e3ae936e6 ("hw/cxl/component: Implement host bridge MMIO (8.2.5,
table 142)")
Reported-by: Igor Mammedov
Signed-off-by: Jonathan Cameron
---
hw/i386/pc.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/
This got left behind in the move of the CXL setup code from core
files to the machines that support it.
Link:
https://gitlab.com/qemu-project/qemu/-/commit/1ebf9001fb2701e3c00b401334c8f3900a46adaa
Signed-off-by: Jonathan Cameron
---
include/hw/boards.h | 1 -
1 file changed, 1 deletion
coding/decoding")
Fixes: Coverity CID 1488868
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_component.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/cxl/cxl_component.h b/include/hw/cxl/cxl_component.h
index 70b5018156..94ec2f07d7 100644
--- a/include/hw
t;
> It's the commit log that's corrupted.
>
> > Do whatever you want with them. I am not allowed to spend more time on this.
> >
> > Brice
>
> Maybe someone will fix up the log and repost. One can hope ..
>
We are planning to send out arm/virt support shortly including a similar test
that uses this series. So if no one else gets to it before hand we'll include
fixed up version of Brice's series with that.
Jonathan
t; fseek(fp, 0, SEEK_SET);
> > cdat->buf = g_malloc0(file_size);
>
> Pointless bzero in g_malloc0, however this code would be
> simplified using g_file_get_contents().
Agreed - switching this whole thing to g_file_get_contents()
will get rid of this code and be a
; +warn_report("CDAT: Found checksum mismatch in %s", cdat->filename);
> > +}
> > +cdat->entry_len = num_ent;
> > + cdat->entry = g_steal_pointer(&cdat_st);
> > +}
> > +
> > +void cxl_doe_cdat_init(CXLComponentState *cxl_cstate, Error **errp)
> > +{
> > +CDATObject *cdat = &cxl_cstate->cdat;
> > +
> > +if (cdat->filename) {
> > +ct3_load_cdat(cdat, errp);
> > +} else {
> > +ct3_build_cdat(cdat, errp);
> > +}
> > +}
>
> None of the callsites to this function check for it
> failing. In particular they do not assume "if I call
> this and it fails then I need to call cxl_doe_cdata_release()
> to have it clean up". It would probably be less confusing
> if the init function cleans up after itself, i.e. does not
> leave allocated memory pointed to by cdat->buf and so on.
Thanks Peter,
I'll wait for the other thread to resolve the follow up with
a patch set cleaning up remaining issues you've pointed out.
Jonathan
>
> thanks
> -- PMM
AT: Found checksum mismatch in %s", cdat->filename);
> > + }
> > +cdat->entry_len = num_ent;
> > +cdat->entry = g_steal_pointer(&cdat_st);
> > +}
> > +
> > +void cxl_doe_cdat_init(CXLComponentState *cxl_cstate, Error **errp)
> > +{
> > +CDATObject *cdat = &cxl_cstate->cdat;
> > +
> > +if (cdat->filename) {
> > +ct3_load_cdat(cdat, errp);
> > +} else {
> > +ct3_build_cdat(cdat, errp);
> > +}
> > +}
>
> None of the callsites to this function check for it
> failing. In particular they do not assume "if I call
> this and it fails then I need to call cxl_doe_cdata_release()
> to have it clean up". It would probably be less confusing
> if the init function cleans up after itself, i.e. does not
> leave allocated memory pointed to by cdat->buf and so on.
Agreed. Will make it cleanup and add the error checks at the two
callers.
Thanks,
Jonathan
>
> thanks
> -- PMM
On Thu, 6 Apr 2023 18:58:37 +0530
Raghu H wrote:
> Thanks Jonathan for quick review/comments on earlier patch, as suggested
> splitting into two separate patches
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg952999.html
>
> Removed the unsupported size option for c
onentState *cxl_cstate)
> cdat->free_cdat_table(cdat->built_buf, cdat->built_buf_len,
>cdat->private);
> }
> -if (cdat->buf) {
> -free(cdat->buf);
> -}
> +g_free(cdat->buf);
Keep the protection if moving to g_free(). Not all paths to this function
allocate cdat->buf
Protection was not needed when the call was free() though.
I have a followup patch that will deal with the other issues Peter pointed out.
I'll
send that once yours has been finalized.
Thanks,
Jonathan
> }
:14, Michael S. Tsirkin wrote:
> >>>>
> >>>> From: Jonathan Cameron
> >>>>
> >>>> The CXL r3.0 specification allows for there to be no HDM decoders on CXL
> >>>> Host Bridges if they have only a single root port. Instead, all access
On Tue, 11 Apr 2023 11:26:16 +0100
Peter Maydell wrote:
> On Wed, 8 Mar 2023 at 01:14, Michael S. Tsirkin wrote:
> >
> > From: Jonathan Cameron
> >
> > The CXL r3.0 specification allows for there to be no HDM decoders on CXL
> > Host Bridges if they have only
On Wed, 19 Apr 2023 14:57:54 +0100
Jonathan Cameron via wrote:
> On Tue, 11 Apr 2023 11:26:16 +0100
> Peter Maydell wrote:
>
> > On Wed, 8 Mar 2023 at 01:14, Michael S. Tsirkin wrote:
> > >
> > > From: Jonathan Cameron
> > >
> > > The C
On Wed, 19 Apr 2023 17:25:17 +0100
Peter Maydell wrote:
> On Wed, 19 Apr 2023 at 15:50, Jonathan Cameron
> wrote:
> >
> > On Wed, 19 Apr 2023 14:57:54 +0100
> > Jonathan Cameron via wrote:
> >
> > > On Tue, 11 Apr 2023 11:26:16 +0100
> > &
s the PXBCXLDev structure already provides
the equivalent grouping.
Patches are similar to those posted in the thread but rebased on v8.0.0.
Jonathan Cameron (2):
hw/pci-bridge: pci_expander_bridge fix type in pxb_cxl_dev_reset()
hw/pci-bridge: Make PCIe and CXL PXB Devices inherit from TYPE_PXB_DEV
-by: Peter Maydell
Signed-off-by: Jonathan Cameron
---
hw/pci-bridge/pci_expander_bridge.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/pci-bridge/pci_expander_bridge.c
b/hw/pci-bridge/pci_expander_bridge.c
index ead33f0c05..a78327b5f2 100644
--- a/hw/pci-bridge/pci_expande
PCI_DEVICE.
This allows simple use of PXB_DEV() etc rather than a custom function
+ removal of duplicated properties and moving the CXL specific
elements out of struct PXBDev.
Signed-off-by: Jonathan Cameron
---
hw/acpi/cxl.c | 11 +++---
hw/cxl/cxl-host.c | 4
an RFC as only lightly tested and I'm not sure what the reasoning
behind the separation of lifetimes originally was. As such perhaps this is
not the best route to fixing the issue.
Reported-by: Thomas Huth
Signed-off-by: Jonathan Cameron
---
hw/pci/pci_bridge.c
This was intended to be [RFC] for reasons given below.
+ I failed to CC Thomas who reported the issue. Not my finest hour.
On Thu, 20 Apr 2023 15:59:37 +0100
Jonathan Cameron wrote:
> The lifetime of the PCIBridgeWindows instance accessed via the windows pointer
> in struct PCIBri
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